CN1316607C - Semiconductor package with high heat dissipation performance and manufacturing method thereof - Google Patents

Abstract

A semiconductor package with high heat dissipation efficiency and a manufacturing method thereof are provided, namely, a plurality of conductive bumps are formed on a welding pad of an active surface of a chip, a heat dissipation sheet is bonded on a non-active surface of the chip, and the area of the heat dissipation sheet is larger than that of the chip; then, forming a packaging colloid to coat the radiating fin, the chip and the conductive lug, and exposing the surface (or the bottom) of the radiating fin, which is not adhered to the chip, and the end part of the conductive lug out of the packaging colloid; then, forming a plurality of conductive traces on the packaging colloid, and electrically connecting the conductive traces to the exposed end parts of the conductive bumps; laying a solder mask layer on the conductive trace, wherein the solder mask layer is provided with a plurality of openings, and the appointed part of the conductive trace is exposed by the openings and is welded with a plurality of solder balls; the area of the radiating fin connected with the chip is the same as that of the packaging piece, so that the heat generated by the chip can be effectively dissipated, and the radiating efficiency of the packaging piece is improved.

Description

Semiconductor package with high heat dissipation performance and manufacturing method thereof

technical field

The present invention relates to a semiconductor package and its manufacturing method, in particular to a semiconductor package with high heat dissipation efficiency and a method for manufacturing the semiconductor package.

Background technique

The semiconductor package carries at least one integrated circuit component, such as a semiconductor chip, and its size is developing towards thinner, lighter and smaller. For this reason, a chip scale package (chip scale package, CSP) has been developed at present, and its size is equal to or slightly larger than that of the chip.

FIG. 5 is a chip-scale package of US Patent No. 6,287,893, which directly forms build-up layers on the chip without using a chip carrier such as a substrate or a lead frame to carry the semiconductor chip. As shown in the figure, a plurality of build-up layers formed on the active surface 100 of the chip 10 includes: a dielectric layer 11 laid on the active surface 100 of the chip 10 and provided with a plurality of through holes 110, The bonding pads 101 on the chip 10 are exposed through the through holes 110 ; and a plurality of conductive traces 12 are formed on the dielectric layer 11 and electrically connected to the exposed bonding pads 101 on the chip 10 . Then, a solder repellent layer 13 is laid on the conductive trace 12, and a plurality of openings 130 penetrating through the solder repellent layer 13 are opened, so that the designated part of the conductive trace 12 is exposed through the opening 130 and soldered to the solder ball 14, The solder balls 14 serve as input/output (I/O) terminals of the package, and are electrically connected to external devices (not marked). However, the disadvantage of this chip-scale package structure is that it is limited by the size or size of the chip and cannot provide more surface area to carry a larger number of solder balls and electrically connect to the outside.

Therefore, US Patent No. 6,271,469 provides another build-up packaging structure formed on a chip, which can provide additional or more surface area for electrical connection with the outside world. As shown in FIG. 6 , this packaging structure utilizes an encapsulant 15 to cover the non-active surface 102 and the side surface 103 of the chip 10 , so that the active surface 100 of the chip 10 is exposed and flush with a surface 150 of the encapsulant 15 . After the dielectric layer 11 (hereinafter referred to as "the first dielectric layer") and the conductive trace 12 (hereinafter referred to as "the first conductive trace") are formed on the chip 10, the second dielectric layer is laid on the first conductive trace 12. The electrical layer 16 also opens a plurality of through holes 160 penetrating through the second dielectric layer 16 , so that a designated portion of the first conductive trace 12 is exposed through the through holes 160 . Next, a plurality of second conductive traces 17 are formed on the second dielectric layer 16 , so that the second conductive traces 17 are electrically connected to the exposed portions of the first conductive traces 12 . Then, the solder repellent layer 13 is laid on the second conductive trace 17 , so that the specified portion of the second conductive trace 17 is exposed through the opening 130 of the solder repellent layer 13 , and soldered to the solder ball 14 .

However, the disadvantage of the above-mentioned package structure is that when laser drilling (laser drilling) technology is used to open through holes through the first dielectric layer to expose the pads on the chip, because the pads on the chip are covered by the first dielectric layer However, it is often difficult for the laser to accurately identify the position of the solder pad, so that the opened through hole cannot accurately correspond to the position of the solder pad. Therefore, since the pads on the chip cannot be fully exposed, it is difficult to ensure the quality of the electrical connection between the conductive traces and the pads and the yield of the finished package. At the same time, in the above packaging structure (FIG. 6), the chip is completely covered by the packaging gel, which cannot dissipate the heat generated by the operation of the chip in time, which may cause problems such as overheating and damage to the chip.

Therefore, how to provide a semiconductor package with high heat dissipation performance to effectively dissipate the heat generated by the chip and ensure the quality of the electrical connection between the conductive trace and the pad is an important issue.

Contents of the invention

For overcoming the shortcoming of above-mentioned prior art, the main purpose of the present invention is to provide a kind of semiconductor package with high heat dissipation efficiency and its manufacturing method, make chip bonding a heat sink, the area of heat sink is the same as the area of package, The heat generated by the chip can be effectively dissipated, thereby improving the heat dissipation efficiency of the package.

Another object of the present invention is to provide a semiconductor package with high heat dissipation efficiency and its manufacturing method. A plurality of conductive bumps are formed on the pads of the chip to highlight the position of the pads and ensure the gap between the conductive traces and the pads. The electrical connection improves the good rate of the finished package.

In order to achieve the above and other objects, the present invention provides a semiconductor package with high heat dissipation performance, including: at least one chip with an active surface and a relative non-active surface, and a plurality of solder pads are formed on the active surface; a conductive bump, respectively formed on the pads of the chip; a heat sink, bonded to the non-active surface of the chip, and the area of the heat sink is larger than the area of the chip; a packaging colloid, covering the bonding surface of the heat sink and the chip, The chip and the conductive bump expose the surface of the heat sink that is not bonded to the chip and the end of the conductive bump to the packaging compound; a plurality of conductive traces are formed on the packaging compound and are electrically connected to the exposed end of the conductive bump ; a solder repellent layer, laid on the conductive trace, with a plurality of openings, so that the designated part of the conductive trace is exposed through the opening; and a plurality of solder balls, respectively formed on the exposed part of the conductive trace.

The process steps of the above-mentioned semiconductor package include the following steps: prepare a wafer, which is composed of a plurality of chips, each chip has an active surface and a relative non-active surface, and a plurality of welding pads are formed on the active surface; A plurality of conductive bumps are respectively formed on the pads; the wafer is cut to form a plurality of isolated chips, each chip has a plurality of conductive bumps; a heat sink module board is provided, which is composed of a plurality of heat sinks, so that each heat sink It is bonded to the non-active surface of at least one chip, and the area of the heat sink is larger than the area of the chip; an encapsulation compound is formed to cover the bonding surface of the heat sink module board and the chip, as well as all chips and conductive bumps, and make the heat sink module The surface of the board that is not bonded to the chip and the end of the conductive bump are exposed to the encapsulant; multiple conductive traces are formed on the encapsulant, so that the conductive trace is electrically connected to the exposed end of the conductive bump; the conductive trace Laying a solder repellent layer on the line, opening a plurality of openings through the solder repellent layer, exposing designated parts of the conductive traces through the openings; forming a plurality of solder balls on the exposed parts of the conductive traces; and cutting the encapsulant and A heat sink module board to separate the heat sinks to form a plurality of semiconductor packages with separate heat sinks.

The manufacturing method of the semiconductor package with high heat dissipation efficiency of the present invention can also be realized through the following steps: prepare a wafer, which is composed of a plurality of chips, each chip has an active surface and a relative non-active surface, and forming a plurality of pads on the surface; forming a plurality of conductive bumps on the pads of each chip; cutting the wafer to form a plurality of isolated chips, each chip having a plurality of conductive bumps; providing a heat sink module board, Consisting of a plurality of heat sinks, each heat sink is bonded to the non-active surface of at least one chip, and the area of the heat sink is larger than the area of the chip; a packaging gel is formed to cover the heat sink module board, all chips and conductive bumps, and The surface of the heat sink module board that is not bonded to the chip and the end of the conductive bump are exposed to the encapsulant; a plurality of first conductive traces are formed on the encapsulant, so that the first conductive traces are electrically connected to the conductive bump The exposed end; a dielectric layer is laid on the first conductive trace, and a plurality of through holes penetrating the dielectric layer are opened, and the designated part of the first conductive trace is exposed through the through holes; a plurality of second conductive traces are formed on the dielectric layer Two conductive traces, so that the second conductive trace is electrically connected to the exposed part of the first conductive trace; a solder repellent layer is laid on the second conductive trace, and a plurality of openings are opened through the solder repellent layer, and the second A designated portion of the conductive trace is exposed through an opening; a plurality of solder balls are respectively formed on the exposed portion of the second conductive trace; heat sink for semiconductor packages.

The above-mentioned semiconductor package has a heat sink directly bonded to the chip, and the heat sink exposes the encapsulating gel covering the chip, which has the same area as the package area, so it can effectively dissipate the heat generated by the chip, thereby improving the heat dissipation of the package. efficiency. Furthermore, a plurality of conductive bumps are directly formed on the pads of the chip, so that the ends of the conductive bumps expose the encapsulation gel covering the chip; the exposed ends of the conductive bumps protrude from the position of the pads on the chip for identification. The conductive traces formed on the encapsulant are electrically connected to the pads through the conductive bumps, thereby improving the yield of the finished package. Therefore, the semiconductor package does not need to expose the pads on the chip through the through holes formed in the first dielectric layer as in the prior art (Fig. It is difficult for laser drilling technology to accurately identify the position of the solder pad, and it is impossible to expose the solder pad accurately or completely, which leads to defects such as poor electrical connection between the solder pad and the conductive trace.

In summary, a semiconductor package with high heat dissipation performance and its manufacturing method according to the present invention, the chip is bonded to a heat sink, the area of the heat sink is the same as the area of the package, and the heat generated by the chip can be effectively dissipated. , thereby improving the heat dissipation efficiency of the package; in addition, a semiconductor package with high heat dissipation efficiency and its manufacturing method of the present invention form a plurality of conductive bumps on the pads of the chip to highlight the position of the pads and ensure the conduction The electrical connection between the trace and the welding pad improves the yield of the finished package.

Description of drawings

1 is a cross-sectional view of a semiconductor package according to Embodiment 1 of the present invention;

2A to 2F are schematic diagrams of steps in the manufacturing process of the semiconductor package of FIG. 1;

3 is a cross-sectional view of a semiconductor package according to Embodiment 2 of the present invention;

4 is a cross-sectional view of a semiconductor package according to Embodiment 3 of the present invention;

5 is a cross-sectional view of a conventional semiconductor package; and

FIG. 6 is a cross-sectional view of another conventional semiconductor package.

Detailed ways

Example 1

Embodiments of the semiconductor package with high heat dissipation performance and its manufacturing method of the present invention will be described in detail below with reference to FIG. 1 , FIG. 2A to FIG. 2F , FIG. 3 and FIG. 4 .

As shown in Figure 1, the semiconductor package of the present invention includes: at least one chip 20, has an active surface 200 and a relative non-active surface 201, and forms a plurality of welding pads 202 on the active surface 200; Blocks 21 are respectively formed on the soldering pads 202 of the chip 20; a heat sink 220 is bonded to the non-active surface 201 of the chip 20, and the area of the heat sink 220 is larger than the area of the chip 20; an encapsulant 23 covers the heat sink 220, the chip 20 and the conductive bump 21, so that the bottom 221 of the heat sink 220 and the end 210 of the conductive bump 21 are exposed to the encapsulation compound 23; a plurality of conductive traces 24 are formed on the encapsulation compound 23 and electrically connected to the The exposed end portion 210 of the conductive bump 21; a solder repellent layer 25, which is laid on the conductive trace 24 and is provided with a plurality of openings 250, so that the designated part of the conductive trace 24 is exposed through the opening 250; Balls 26 are formed on exposed portions of the conductive traces 24, respectively.

The above-mentioned semiconductor package is manufactured by the process steps shown in FIGS. 2A-2F .

First, as shown in FIG. 2A, a wafer 2 is prepared, consisting of a plurality of chips 20, each chip 20 has an active surface 200 and a relative non-active surface 201, and multiple chips are formed on the active surface 200 of each chip 20. pads 202. Next, a bumping or stud bumping step is performed to form a conductive bump 21 on each pad 202 of the chip 20. The conductive bump 21 can be a solder bump with high lead content. Solder bump (highlead solder bump), gold solder bump (gold bump), or gold stud bump (gold stud bump), etc.

Next, as shown in FIG. 2B , a singulation operation is performed to cut the wafer 2 to form a plurality of isolated chips 20 , and each chip 20 has a plurality of conductive bumps 21 .

As shown in FIG. 2C, a heat sink module plate (heat sink module plate) 22 is provided, which is composed of a plurality of heat sinks 220, so that each heat sink 220 is connected to at least one non-conductive chip 20 separated by an adhesive (adhesive) 27. The active surface 201 is bonded, and the area of each heat sink 220 is greater than the area of the corresponding chip 20; the heat sink module board 22 is made of a conductive metal material such as copper, and the adhesive 27 is preferably made of a thermally conductive Viscose.

Then, carry out a molding (molding) process, utilize existing resin material (such as epoxy resin etc.) The bottom 221 of the chip 22 (or the surface not bonded to the chip 20 ) exposes the encapsulant 23 .

As shown in FIG. 2D, part of the encapsulant 23 is removed by grinding (grinding, such as mechanical grinding), so that the end 210 of the conductive bump 21 is exposed and flush with the surface 230 of the encapsulant 23; A build-up layer is formed on the exposed conductive bump 21; the larger heat sink 220 or heat sink module board 22 enables the packaging compound 23 formed thereon to provide more surface area (ie, the packaging compound 23) for subsequent formation of build-up layers and more input/output (input/output, I/O) terminals (not marked).

Next, using existing technology such as photolithography, a plurality of conductive traces 24 are formed on the surface 230 of the encapsulant 23, so that each conductive trace 24 is electrically connected to the exposed end portion 210 of at least one conductive bump 21. To connect, the conductive trace 24 is made of a conductive material such as copper, aluminum, or alloys thereof.

As shown in Figure 2E, after the conductive trace 24 is formed on the encapsulant 23, a solder repellant layer 25 is laid on the conductive trace 24, and a plurality of openings 250 penetrating the solder repellent layer 25 are opened, so that the conductive trace 24 The designated portion of the conductive trace 24 is exposed through the opening 250, and the exposed portion of the conductive trace 24 may be a terminal. Then, carry out an existing screen printing (screen printing) operation, form a solder ball 26 on the exposed part (terminal) of each conductive trace 24, solder ball 26 is used as the input/output terminal of semiconductor package, makes chip 20 It is electrically connected with external devices (not marked, such as printed circuit boards, etc.).

Finally, as shown in FIG. 2F , a single operation is performed to cut the encapsulant 23 and the heat sink module board 22 to separate the heat sinks 220 to form a plurality of semiconductor packages with separate heat sinks 220 .

The above-mentioned semiconductor package is to make a heat sink directly bonded to the chip, and the heat sink exposes the encapsulating gel covering the chip, which has the same area as the package area, so it can effectively dissipate the heat generated by the chip, thereby improving the package. cooling efficiency. Furthermore, a plurality of conductive bumps are directly formed on the soldering pads of the chip, so that the ends of the conductive bumps are exposed outside the encapsulation gel covering the chip; the exposed ends of the conductive bumps protrude from the position of the soldering pads on the chip for Identification, so that the conductive traces formed on the packaging compound are electrically connected to the pads through the conductive bumps, and the yield of the finished package is improved. Therefore, the semiconductor package does not need to expose the pads on the chip through the through holes formed in the first dielectric layer as in the prior art (Figure 5 and Figure 6), which overcomes the problem of opening the through holes of the first dielectric layer Advanced laser drilling technology is difficult to accurately identify the position of the pad, and cannot expose the pad accurately or completely, resulting in poor electrical connection between the pad and the conductive trace.

Example 2

FIG. 3 shows a semiconductor package of Embodiment 2 of the present invention. As shown in the figure, the structure of the semiconductor package is roughly the same as that of the semiconductor package in Embodiment 1 above. Lay a dielectric layer 28 on the first conductive trace 24, and use such as laser drilling (laser drilling) technology to open a plurality of through holes (via) 280 through the dielectric layer 28, so that the first conductive trace 24 The designated portion is exposed through the through hole 280 . Next, a plurality of second conductive traces 29 are formed on the dielectric layer 28 , and each second conductive trace 29 is electrically connected to the exposed portion of at least one first conductive trace 24 .

Then the solder repellent layer 25 is laid on the second conductive trace 29, and a plurality of openings 250 penetrating the solder repellent layer 25 are opened, so that the designated part of the second conductive trace 29 is exposed through the opening 250, and the second conductive trace 29 The exposed portion of may be a terminal. Then, carry out existing screen printing (screen printing) operation, on the exposed part (terminus) of each second conductive trace 29, form the solder ball 26 as the input/output end of semiconductor package, to communicate with external device (not marked) into an electrical connection.

Therefore, in addition to the effect achieved by the semiconductor package of the above-mentioned embodiment 1, the dielectric layer and the second conductive trace can form a build-up layer on the chip, which improves the flexibility of the conductive trace layout in the package, and makes the chip more effective. It is electrically connected to solder balls and external devices for operation.

Example 3

FIG. 4 shows a semiconductor package according to Embodiment 3 of the present invention. As shown in the figure, the structure of the semiconductor package is roughly the same as that of the semiconductor package in Embodiment 1 above, the difference is that the surface 223 where the heat sink 220 is bonded to the chip 20 forms a plurality of grooves 222, forming the encapsulation compound 23. The resin material and the adhesive 27 for bonding the chip 20 and the heat sink 220 are filled in the groove 222, which can increase the adhesion between the surface 223 of the heat sink 220 and the encapsulation compound 23 and the chip 20; or, make the surface 223 of the heat sink 220 The roughness (not marked) also helps to improve the adhesion between the heat sink 22 and the encapsulant 23 and the chip 20 .

Claims (20)

1. A semiconductor package with high heat dissipation performance, characterized in that the package comprises: At least one chip has an active surface and an opposite non-active surface, and a plurality of pads are formed on the active surface; A plurality of conductive bumps are respectively formed on the pads of the chip; A heat sink, bonded to the non-active surface of the chip, the area of the heat sink is larger than the area of the chip; An encapsulation compound that covers the heat sink, the chip and the conductive bump, so that the surface of the heat sink that is not bonded to the chip and the end of the conductive bump expose the encapsulation compound; and A plurality of first conductive traces are formed on the encapsulant and electrically connected to the exposed ends of the conductive bumps. 2. The semiconductor package according to claim 1, further comprising: a solder repellent layer, laid on the first conductive trace, and provided with a plurality of openings, so that the first conductive trace Specified portions of the wires are exposed through the openings. 3. The semiconductor package as claimed in claim 2, wherein a plurality of solder balls are respectively formed on the exposed portions of the first conductive traces. 4. The semiconductor package according to claim 1, characterized in that the package comprises: a dielectric layer laid on the first conductive trace and provided with a plurality of through holes, the designation of the first conductive trace Parts are exposed through through holes. 5 . The semiconductor package as claimed in claim 4 , wherein a plurality of second conductive traces are formed on the dielectric layer and electrically connected to exposed portions of the first conductive traces. 6. The semiconductor package as claimed in claim 5, wherein a solder repellant layer is laid on the second conductive trace, and a plurality of openings are provided, and a designated part of the second conductive trace is exposed through the opening . 7. The semiconductor package as claimed in claim 6, wherein a plurality of solder balls are respectively formed on the exposed portions of the second conductive traces. 8 . The semiconductor package as claimed in claim 1 , wherein the surface where the heat sink is bonded to the chip has a plurality of grooves to increase the adhesion between the surface, the encapsulant and the chip. 9. The semiconductor package as claimed in claim 1, wherein the bonding surface of the heat sink and the chip is roughened to increase the adhesion between the surface, the encapsulant and the chip. 10. The semiconductor package of claim 1, wherein the conductive bumps are selected from the group consisting of solder bumps, high-lead solder bumps, gold solder bumps, and gold plugs. 11. A method for manufacturing a semiconductor package with high heat dissipation performance, characterized in that the method comprises the following steps: Prepare a wafer, which is composed of a plurality of chips, each chip has an active surface and an opposite non-active surface, and a plurality of welding pads are arranged on the active surface; Forming a plurality of conductive bumps on the bonding pads of each chip; dicing the wafer to form a plurality of discrete chips, each chip having a plurality of conductive bumps; Provide a heat sink module board, which is composed of a plurality of heat sinks, each heat sink is bonded to the non-active surface of at least one chip, and the area of the heat sink is larger than the area of the chip; Form an encapsulation gel to cover the heat sink module board and all chips and conductive bumps, and the surface of the heat sink module board that is not bonded to the chip and the end of the conductive bump are exposed to the encapsulation gel; forming a plurality of conductive traces on the encapsulant, so that the conductive traces are electrically connected to the exposed ends of the conductive bumps; Laying a solder repellant layer on the conductive trace, opening a plurality of openings through the solder repellent layer, so that the designated part of the conductive trace is exposed through the opening; forming a plurality of solder balls respectively on the exposed portions of the conductive traces; and cutting the encapsulant and the heat sink module board, and separating each heat sink to form a plurality of semiconductor packages with separate heat sinks. 12 . The method according to claim 11 , wherein the end of the conductive bump is exposed by removing the top portion of the encapsulant by grinding. 13 . 13. The method of claim 11, wherein the conductive bumps are selected from the group consisting of solder bumps, high-lead solder bumps, gold solder bumps, and gold plugs. 14 . The method according to claim 11 , wherein the surface where the heat sink module board is bonded to the chip has a plurality of grooves to increase the adhesion between the surface, the encapsulation compound and the chip. 15 . 15 . The method according to claim 11 , wherein the bonding surface of the heat sink module board and the chip is roughened to increase the adhesion between the surface, the encapsulation compound and the chip. 15 . 16. A method for manufacturing a semiconductor package with high heat dissipation performance, characterized in that the method comprises the following steps: Prepare a wafer, which is composed of a plurality of chips, each chip has an active surface and an opposite non-active surface, and a plurality of welding pads are formed on the active surface; Forming a plurality of conductive bumps on the bonding pads of each chip; Dicing the wafer to form a plurality of isolated chips, each chip has a plurality of conductive bumps; Provide a heat sink module board, which is composed of a plurality of heat sinks, each heat sink is bonded to the non-active surface of at least one chip, and the area of the heat sink is larger than the area of the chip; Form an encapsulant to cover the heat sink module board and all chips and conductive bumps, and expose the encapsulant on the surface of the heat sink module board that is not bonded to the chip and the end of the conductive bump; forming a plurality of first conductive traces on the encapsulant, so that the first conductive traces are electrically connected to the exposed ends of the conductive bumps; laying a dielectric layer on the first conductive trace, opening a plurality of through holes penetrating through the dielectric layer, and a designated part of the first conductive trace is exposed through the through holes; forming a plurality of second conductive traces on the dielectric layer such that the second conductive traces are electrically connected to exposed portions of the first conductive traces; Laying a solder repellent layer on the second conductive trace, opening a plurality of openings penetrating through the solder repellent layer, and exposing a designated portion of the second conductive trace through the openings; forming a plurality of solder balls respectively on the exposed portions of the second conductive traces; and The encapsulant and the heat sink module board are cut to separate the heat sinks to form a plurality of semiconductor packages with separate heat sinks. 17 . The method according to claim 16 , wherein the exposed portion of the end of the conductive bump is removed by grinding technology to remove the encapsulant. 18 . 18. The method of claim 16, wherein the conductive bumps are selected from the group consisting of solder bumps, high-lead solder bumps, gold solder bumps, and gold plugs. 19. The method according to claim 16, wherein the surface where the heat sink module board is bonded to the chip has a plurality of grooves to increase the adhesion between the surface, the encapsulation compound and the chip. 20. The method according to claim 16, characterized in that the surface of the heat sink module board bonded to the chip is roughened to increase the adhesion between the surface and the packaging colloid and the chip.

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