GB1318775A - Encoders - Google Patents

Abstract

1318775 Analogue/digital converters PLESSEY TELECOMMUNICATIONS RESEARCH Ltd 24 Nov 1971 [24 Aug 1970] 40661/70 Heading G4H In an analogue-n bit digital converter in which a first coding operation derives from the analogue input the r most significant bits of the digital signal and the second coding operation derives the s least significant bits (r + s > n), the least significant bit(s) of the r bits and the most significant bit(s) of the s bits are combined to derive the n bit output signal. In the embodiment of Fig. 2, in which an 11 bit output is obtained from two coding operations each deriving 6 bits, with switches 23, 30 in the position shown, a bias signal of 5 units is subtracted from the sampled input signal before it is fed to a coder 24 to derive the six most significant bits. Switches 23, 40 are then changed over and the contents of the coder 24 are read into a store 26 connected to output logic 33 and a decoder 29 (for example a ladder network). The resulting analogue signals from the decoder is subtracted from the input signal, the difference signal being amplified by 2<SP>5</SP> before being fed to decoder 24 to derive the six least significant bits. Subsequently the output logic 33 adds the least significant bit of the first coding operation and the most significant bit of the second coding operation to obtain the required output. In a second embodiment (Fig. 3) a bias voltage of 2<SP>5</SP> is subtracted from the input signal after it has been sampled in a sampling circuit 42, the resulting signal being fed to a first coder 44 to derive the most significant bits which are then fed to a store 47 connected to a decoder 49 and output logic 48. The output of the decoder is subtracted from the output of a second sampling circuit 45 receiving the sampled input from the first circuit 42, the difference signal being amplified by 2<SP>5</SP> before being fed to a second coder 51 to derive the least significant bits. As in the embodiment of Fig. 2 the output logic 48 combines the 12 bits to produce an 11 bit signal. A delay 53 is included to enable sampling circuit 45 to read in the contents of the sampling circuit 42 before a new sample is taken. This results in fine decoding of one sample occurring simultaneously with the coarse encoding of the succeeding sample. Diodes 40 (Fig. 2), 43 (Fig. 3) are included to prevent one of the two coding operations having an effect on the other. The apparatus described reduces errors due to inaccuracy in the coders. Modifications: (1) The apparatus may be extended to more than two coding operations; (2) the bias of 2<SP>5</SP> may alternatively be applied in the opposite sense to the amplified difference in the second coding operation; (3) the number of bits derived in the two coding operations may be different; (4) the fine and coarse coding operations may overlap by more than one bit and (5) if the signals are slowly varying the sample and hold circuits may be dispensed with.