GB1395922A - Method and apparatus for generating a traveling display - Google Patents

Abstract

1395922 Control of displays BUNKER RAMO CORP 24 May 1972 [8 Sept 1971] 24515/72 Heading G4H [Also in Division H4] Apparatus for generating a travelling display on a cathode ray tube C.R.T. 10, Fig. 1, incorporates means for advancing information across the display at a rate which varies with the rate at which input data is received. Information displayed on the C.R.T. 10 is cyclically refreshed with a raster pattern made up of lines of characters formed by selectively intensifying seven index points on each of five strokes (Fig. 3): synchronizing pulses 12 control three ramp generators for stroke generation, line generation (horizontal retrace), and line spacing and frame retrace respectively, the horizontal retrace pulses being supplied to C.R.T. 10 via a variable delay 14. Data is fed via an input buffer register 32 to a random access memory 24, each line being stored in a separate segment (Fig. 4), in each of which positions 4-51 store data being displayed whereas positions 1-3, 52-56 store buffer characters for updating the display. A detector 51 assigns incoming data to the appropriate segment, and a detector 36 increments a counter 48 which indicates the address in 24 at which the next incoming character is to be stored (character 2, in Fig. 4). A character counter 50 stores the address in 24 of the first character being displayed (4, in Fig. 4); a stroke counter 50 counts modulo 7 to increment the character counter and to control delay 14. On the occurrence of the first frame sync. pulse FR1, the count (2) in 48 is fed to a counter 66 and a buffer counter 62 is set to the value 8; the counts (4, 2) in 50 and 66 are compared at 68, a "no match" signal 70 opening a gate 72 so that subsequent FR pulses can increment 66 and decrement 62. When 66 and 50 agree, the count in 62 indicates the number of new buffer characters (6, in Fig. 4), and is passed through a gate 80 by a "match" signal 78 to a detector circuit 82-85, where it sets a "shift 1" or a "shift 2" flip-flop. The output 98 or 126 from the particular set flip-flop is fed back to enable one of gates 100 or 128 so that pulses FR can increment the stroke counter by 1 or 2. The horizontal retrace pulse passing through 14 is delayed by a number of strokes equal to the stroke count 106 (2 strokes for data of Fig. 4): while the retrace pulse is being delayed, a clock 22 continues to read out from memory 24, so that memory 24 becomes out of phase with the delay: thus an effective stroke shift operation is performed, the display shifts to the left (here by 2 strokes) and the first two strokes (Fig. 4 data) of the first buffer character 2 are displayed. The above process continues until all the buffer characters have been displayed, the display lines shifting to the left all the while.