JPH038173A - Magnetic reproducing device - Google Patents

Abstract

PURPOSE:To obtain a regenerative data having reduced bit errors by changing outputs between a regenerative data of a viterbi decoding circuit and a regenerative data of a circuit for decoding a regenerative signal based on a signal level of the regenerative signal. CONSTITUTION:A regenerative signal SRF is inputted via an amplifier circuit 18, an equalizer circuit 19 and a arithmetic processing circuit 20 to an A/D converter circuit 24, and is converted into an input data yk with a period of rising and falling the signal level of the signal SRF. The data yk is decoded into the regenerative data DPBV by viterbi decoding circuits 28 and 30 after being divided into an even number group and an odd number group. On the other hand, an output signal of the circuit 20 is detected in signal level by the decoding circuit 50, and is decoded into the regenerative data DPBB. The regenerative data DPBV and DPBB are detected as to coincidence/noncoincidence of a continuous 5-bit data by a changeover circuit 56, and when noncoincidence of a data of >=2 bits is obtained, the regenerative data DPBB in place of the regenerative data DPBV is outputted to an error detection correcting circuit 71, so that the regenerative data DPB having reduced bit errors is obtained.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B. Outline of the invention C. Prior art Problems to be solved by the invention This is suitable for use in video tape recorders.

B Summary of the Invention The present invention enables a magnetic reproducing device to output decoded data with fewer bleeps as needed by switching and outputting decoded data output from two types of decoding circuits. .

At this time, by switching the decoded data based on the comparison result of the reproduced data, the probability data, the operation mode, and the signal level of the reproduced signal, reproduced data with reduced bit errors can be obtained.

Furthermore, decoded data can be easily obtained by detecting changes in predetermined bits of data input to the Viterbi decoding circuit.

C. Prior Art Conventionally, in a general video tape recorder as this type of magnetic reproducing device, a video signal is recorded and reproduced using, for example, a frequency-modulated analog signal.

D. 8 Points to be Solved by the Invention By converting the video signal into a digital signal and recording it on a magnetic tape, it is considered that deterioration in image quality can be effectively avoided no matter how many times dubbing is performed.

However, when recording and reproducing digital signals on magnetic tape, the occurrence of bit errors is unavoidable.

On the other hand, in order to convert video signals into digital signals and record them, the recording density must be increased.
In this case, in order to obtain a reproduced image with little deterioration in image quality no matter how many times it is dubbed, it is necessary to reduce this bit error and reliably decode the recorded data.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a magnetic reproducing device that can reduce bit errors.

Means for Solving Efo1 Problem In order to solve this problem, the present invention utilizes a partial response method to reproduce the predetermined data D□0 recorded on the magnetic recording medium 14. In the playback device 1, an analog-to-digital conversion circuit 24 converts the signal level of the playback signal S□ into a digital signal yk at a predetermined period, and an analog-to-digital conversion circuit 24
Based on the output data y output from
The Viterbi decoding circuit 28.30 decodes □ and the reproduced signal S
A decoding circuit 50 decodes the reproduced signal 5IIF based on the signal level of 0, and decoded data DP++v and D decoded by the Viterbi decoding circuit 28, 30 and the decoding circuit 50.
A switching circuit 56 that switches and outputs Plm is provided.

Furthermore, in the second invention, the switching circuit 56 selects the Viterbi decoding circuit 28.30 based on the comparison result DCOMF of the decoded data D□9 and D□ decoded by the Viterbi decoding circuit 28.30 and the decoding circuit 50. Then, the decoded data D FIV and D FIR decoded by the decoding circuit 50 are switched and output.

Furthermore, in the third invention, the switching circuit 56 selects the decoded data D□9 and D □Switch and output.

Furthermore, in the fourth invention, the switching circuit 56 selects the Viterbi decoding circuit 28 based on the operating mode of the magnetic reproducing device l.
．． 30 and decoded data D P decoded by the decoding circuit 50
Switch and output MV and D pmm.

On the other hand, in the fifth invention, the switching circuit 56 is
Playback signal S. The decoded data D decoded by the Viterbi decoding circuit 28, 30 and the decoding circuit 50 based on the signal level of
□9 and D□ are switched and output.

Furthermore, in the sixth invention, the decoding circuit 50 receives the output data y output from the analog-to-digital conversion circuit 24.
, and decodes the reproduced signal S□ based on the detection result.

By switching and outputting the decoded data DPIV and □ decoded by the F-action Viterbi decoding circuit 28, 30 and the decoding circuit 50, decoded data D□, □ with fewer bit errors can be generated as needed.
and □ can be output, and bit errors can be reduced accordingly.

At this time, the comparison result D of the decoded data DP□ and DPIB decoded by the Viterbi decoding circuit 28.30 and the decoding circuit 50
Based on COMF, decoded data D□9 and □ are output from the Viterbi decoding circuit 28, 30 and the decoding circuit 50.
By switching the bit errors, bit errors can be reduced with a simple configuration.

Similarly, the Viterbi decoding circuit 28.30 calculates the probability data Δ of the Viterbi decoding circuit 28.30 based on the signal level of the reproduced signal sur or the operation mode of the magnetic reproducing device 1.
Even if the decoded data D WmV and D□ decoded by the decoding circuit 50 are switched, bit errors can be reduced with a simple configuration.

At this time, if the decoding circuit 50 detects a change in the predetermined bits D□, [)ys of the output data y output from the analog-to-digital conversion circuit 24, and decodes the reproduced signal S0 based on the cough detection result, Decoded data D□ can be obtained with a simple configuration.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) First Embodiment In FIG. 1, 1 indicates a video tape recorder as a whole, and an analog-to-digital conversion circuit 2 is configured to operate with a clock signal 5e11 that is four times as large as the subcarrier signal.
A video signal Sv is given to .

As a result, from the analog-to-digital conversion circuit 2 to 8
A digital video signal Dv of approximately 25
MBPS) data DI.

On the other hand, the error correction circuit (ECC) 6
The data-compressed digital video signal D11 is received together with the digitally processed audio signal DA, and shuffling, addition of codes for error correction, etc. are performed, and as a result, as shown in FIG.
The recording data D□ of S) (FIG. 2(A)) is output.

(Gl-1) Precoat circuit On the other hand, as shown in FIG. 3, the precoat circuit 8 is
The exclusive OR circuit 8A receives the recording data D□, and the output of the exclusive OR circuit 8A is sent to the two-stage delay circuits 8B and 8C which operate at the repetition frequency of the recording data D□. The signal is fed back to the input terminal of the exclusive OR circuit 8A via the signal line.

As a result, the precoat circuit 8 outputs the recording data DI! The arithmetic processing expressed by the following formula is sequentially performed on c, and recorded data D□ is obtained.

Using the correlation between the data, the precoat data D□(
Convert to Figure 2 (B)).

Here, MOD2 represents the remainder of 2.

That is, as shown in FIG. 4, when recording and reproducing signals on a magnetic tape, the CN ratio deteriorates at lower frequencies because the electromagnetic conversion system such as the magnetic head has differential characteristics. As the frequency increases, the CN ratio similarly deteriorates due to the magnetization characteristics of the magnetic tape.

Therefore, in magnetic recording/reproducing systems, when recording and reproducing digital video signals, there is a characteristic that the frequency band in which a good CN ratio can be obtained is narrow.

Therefore, when recording digital video signals, select a recording method that concentrates the signal spectrum near the maximum CN ratio, thereby effectively avoiding deterioration of the CN ratio of the reproduced signal. It is necessary to efficiently record and reproduce digital video signals.

Therefore, in this embodiment, a digital video signal is recorded and reproduced using the class (1) partial response method, which is one of the high-efficiency encoding methods.

In other words, in a magnetic recording/reproducing system, the CN ratio deteriorates at low and high frequencies, so its frequency characteristics are expressed as class ■ partial responses using delay operator D, as shown in Figure 5. (1-D") frequency characteristic) can be expressed approximately as I(ω).

・By the way, the frequency ω at which the response is minimum. has the following relationship with respect to the delay time T expressed by the delay operator D as shown in the following equation (2).

Therefore, by selecting the delay amount represented by the delay operator D to a predetermined value, it is possible to concentrate the signal spectrum in the vicinity where the CN ratio is maximum.

On the other hand, the transfer function of the entire reproduction system is expressed by the following formula % formula % (1
) (3), the transfer function of the entire recording/reproducing system can be set to 1 for the arithmetic processing of the precoat circuit 8, and the frequency characteristics of the recording/reproducing system can be effectively used to efficiently convert digital video signals. Can be recorded and played back well.

As shown in FIG. 6, the precoat circuit 8 divides the precoat data D□ into predetermined blocks and outputs the divided blocks to the adder circuit 9.

The adder circuit 9 adds predetermined data Dp before and after each block of the precoat data D□, and thereby sends the precoat data to the magnetic heads 12A and 12B via the amplifier circuit 10 to which the postamble and preamble data have been added. Data D□ is output.

Furthermore, in this embodiment, the magnetic heads 12A and 12
B are arranged on a rotating drum (not shown) at angular intervals of 180 degrees, and thereby precoat data D□ to which a postamble and a preamble have been added,
(2) Data is recorded on each recording track of the magnetic tape 14 in units of blocks.

Incidentally, in the preamble, the precoat data DPM
A reference signal with a frequency of 15 [M7] consisting of 172 repetition frequencies of 30 (MHz) is recorded, and the frequency of the reference signal is a frequency ω that satisfies equation (2).

has been selected to be.

Therefore, in this embodiment, the clock signal is formed based on the reference signal of frequency 15 [M7] obtained from the preamble, and the reproduced signal SIF is processed based on the clock signal. There is.

(Gl-2) Reproduction system On the other hand, the magnetic heads 16A and 16B provide the reproduction signal S□ (FIG. 2(C)) to the arithmetic processing circuit 20 via the amplifier circuit I8 and the equalizer circuit 19.

As shown in FIG. 7, the arithmetic processing circuit 20 includes an adder circuit 2]
and a delay circuit 22, whereby the reproduced signal S□
, the arithmetic processing of (1+D) is executed.

On the contrary! Since the magnetic conversion system has differential characteristics, the reproduced signal 5IIF is converted to (1
-D), and is represented by a frequency characteristic as shown by a broken line in FIG.

Therefore, during playback, the precoat data D during recording is
The PI is corrected as a whole according to equation (3), and the frequency characteristics of the magnetic recording/reproducing system are effectively utilized to efficiently record/reproduce digital video signals.

In this way, the output signal sr whose amplitude changes according to the logic level of the recording data DRfc is generated via the arithmetic processing circuit 20.
(Fig. 2(D)) can be obtained.

On the other hand, the analog-to-digital conversion circuit 24 converts the signal level of the output signal SF into a digital value at the rising and falling cycles of the signal level of the reproduced signal S□, and the resulting input data yk is sent to the selection circuit 26. Output to.

The selection circuit 26 sequentially switches the contacts in synchronization with the input data y, thereby converting the input data yk into even and odd series data D. and DYE and output to the Viterbi decoding circuits 28 and 30.

(Gl-3) Viterbi decoding circuit As shown in FIGS. 8 and 9, performing the arithmetic processing of (1-D") on the reproduced signal S
3. 2 consecutive precoat data D□
Since this means performing subtraction processing with a clock cycle delay, if input data yk is separated into even and odd series, (1-D) It is possible to obtain input data Vw on which the arithmetic processing has been performed.

On the other hand, in a magnetic recording/reproducing system, the magnetic head 1
Since noise is mixed in the tM1 conversion system consisting of 2A, 12B, 16A, 16B and the magnetic tape 14, as shown in FIG.
") can be equivalently expressed as an arithmetic processing circuit 31 and an addition circuit 32 that adds noises S and l to the output signal SF of the arithmetic processing circuit 31.

Therefore, when separating the input data y for each even number series and odd number series, the precoat data D
It can be rewritten with an arithmetic processing circuit 33 for (1-D) for □ and an addition circuit 34 that adds noise SN to the output signal S of the arithmetic processing circuit 33.

As a result, when decoding input data yk divided into even and odd sequences, the value b of precoat data DPI
It is possible to utilize the fact that there is a (1-D) correlation between the input data y*% yh*+... for 11, t)+141,..., and to use this correlation, The value of pre-coated data D□ before noise is mixed in
By detecting 1*1, . . . , the reproduced data D□ can be decoded with reduced bit errors.

In this embodiment, based on this premise, the reproduced data D0 is obtained by applying the Viterbi decoding method, and as shown in FIG. The input data )'k, )'kle1, . . . are decoded using the circuit 28 (30).

In other words, if the calculation process (1-D) is performed on the pre-coated data D□, the calculation result of value 2 or value -2 will be obtained for the continuous data of values 1, -1 or values -1, 1, respectively. Obtainable.

Therefore, as shown in Fig. 13, in the output signal SF (Fig. 13 (A)) mixed with noise, the peak value fluctuates around the value 2, and as shown by the symbol PI, there is a pulse-like noise. becomes mixed in.

As a result, in the Viterbi decoding circuit 28 (30),
Sequentially, for example, the values 1.8, ■, 2, -1.7.0. 0.8
,...input data 1*, Vk*I...
...(Fig. 13 (B)) is input, and the input data y
k, )'m*+ .

The latch circuit 41 receives data DI of the decoding result output from the comparison circuit 43 (that is, corresponding to input data yk).
It has a memory means 44 and a switch means 45 configured to store probability data Δk of the comparison circuit 4.
When data D ranging from 0 to 1 and -1 is output, the switch means 45 is turned on.

Thereby, the latch circuit 41 takes in the data output from the adder circuit 39 and updates the probability data Δk.

Incidentally, in this case, data of value O is stored as the initial value of the probability data Δ.

On the other hand, the adder circuit 38 sends the probability data Δk stored in the latch circuit 41 (corresponding to the human input data yk before I clock cycles) and the subtracted data D2 of the input data ym** to the comparator circuit 40. It is designed to output.

The comparison circuit 40 converts the subtraction data D□ into data D3 (hereinafter referred to as predicted input value) with values 1.0 and -1 at a threshold level of ±1, and converts the predicted input HD into data D3 (hereinafter referred to as predicted input value). Make it 39.

That is, the certainty data Δk and the input data 7m
When the relationship of the following formula % formula % (4) holds true for ++, the predicted input value ri is set to the value 1, and the probability data Δk stored in the memory means 44 is
is updated to probability data Δ(k+1) expressed by the following formula (5).

On the other hand, when the relationship of the following formula % formula % (6) is established, the predicted human power 11Dz is set to the value -1, and the probability data Δk stored in the memory means 44 is calculated by the following formula % formula % ( 7) Update the probability data Δ(k+1) expressed as follows.

Furthermore, when the relationship of the following formula % formula (8) is established, the predicted input value ri is set to the value 0, and the probability data Δk is changed to the probability expressed by the following formula 6 formula (9) The data is updated to Δ(k+1).

As shown in Figure 14, when the value of the input data 'met changes by 1 or more with respect to the probability data Δk (Figure 14 (A)), the prediction is made in the opposite direction to the direction of the change. This means setting the input value ri to the value -1 or the value 1, and updating the new probability data Δ(k+1) to a value smaller by the value l than the value of the input data 7m++ (Fig. 14 (B) )).

Therefore, if the value of ++ in the input data)' changes significantly beyond the area indicated by diagonal lines, a predicted input value of 1 or -1 is obtained, and the corresponding human data y. The probability data Δ(k+, 1) is updated according to the value of 1. However, if it does not change significantly beyond the shaded area, the predicted input value of value O is output, and the probability is updated to Δ(k+, 1). data Δ
(k+1) is retained as is.

As a result, as shown in FIG. 15, if the predicted input value y1 of the first line is obtained, the input data y1.

When the value of y falls, it can be determined that the value of the input data y at least one crotter period ago would have risen significantly on the positive side.

Therefore, input data y1. ．． It can be seen that even when large noise is mixed in at the timing of , the value of the precoat data exhibits changes other than the transition from the value -1 to the value 1 and the transition where the value -1 is maintained.

Conversely, as shown in FIG. 16, when the predicted input value D3 of value -1 is obtained, the input data y1. ．． If the value of y rises, it can be determined that the value of input data y at least one clock period ago would have fallen significantly on the negative side.

Therefore, even if a large amount of noise is mixed in at the timing of input data 7m++, the value of the precoat data will fall from value 1 to value -1 and will be maintained at value 1! ! It can be seen that changes other than migration occurred.

On the other hand, as shown in FIG. 17, if the predicted input value RI of the value O is obtained, the input data
＊+ means that the change was small, and even if large noise is mixed in, the value of the pre-coated data will not change other than the transition from value -1 to value 1 and the transition from value 1 to value -1. I can see that it was presented.

Therefore, as shown in FIG. 18, if predicted input values of value 1 and value O are obtained consecutively, precoat data D□
It can be seen that the value of is either a transition in which the diameter value 1 continues falling from the value 1 to the value -1, or a transition in which the value 1 continues.

On the other hand, the prediction input (il!D 3
If is obtained, this indicates that a change other than the transition rising from the value -1 to the value 1 and the transition remaining at the value -1 has occurred, so that the continuous precoat data D□ from two clock cycles ago It is determined that the value of is a transition in which the diameter value 1 that falls from the value 1 to the value -1 continues.

Similarly, when the predicted input value of value -I is obtained, followed by the predicted input value of value l, when the predicted input value of value -1 is obtained, the value of precoat data D0 is obtained. It can be seen that the value rose from the value -1 to the value 1.

Thus, the transition of the precoat data D9 can be determined based on the continuous predicted human power MD3, and thereby the recorded data I)mtc can be decoded.

Furthermore, at this time, the probability data Δ has (4) to (
9) As expressed in equation 9, when input data y changes by 1 or more, it is updated according to the value of input data yk, so the larger the absolute value of that value, the more the predicted input value It can be determined that the transition of the precoat data D□ determined by is more reliable.

Based on this detection principle, the Viterbi decoding circuit 28 (30) sequentially updates the probability data Δk, and based on the updated probability data Δk and the predicted input value D3,
Detect transitions in input data yk.

In other words, the value 1 for the probability data Δk of the value O
．． When the input data y, I of 8 is input, the value -1,8
By obtaining the subtraction data, the predicted input value RI with the value -1 is output (Figure 13 (B)), and the certainty data Δk is updated to the value 0.8 (Figure 13 (D)). )).

Next, when *+ is input to input data 7 with a value of 1.2,
The subtraction data of the value -0,4 is obtained, and the predicted input value of the value 0 is outputted.In this case, since the switch means 45 is held in the off state, the data of the value 0.8 is obtained. Δ
k is held in the latch circuit 41.

In contrast, the following input data with values -1, 7)'to
When + is input, subtraction data with a value of 2.5 is obtained, a predicted input value D3 with a value of 1 is output, and the probability data Δk is updated to a value of 0.7.

As a result, the input data yk has a value of 1.8. 1 to value 1.
It is possible to detect that the precoat data D□ continues to have values 1 and 1 until the input data 2)'k41.

In this way, the values of the precoat data D□ can be sequentially detected based on the predicted human power value D3.

The comparator circuit 43 outputs data D of the decoding result of [1] when the probability data Δk has a value of 0 or more, whereas when the probability data Δk takes a negative value, it outputs the data D of the decoding result of [1].
By outputting the data D of the decoding result of 1, the rising and falling edges of the input data yk are detected based on the certainty data Δk.

The data memory circuit 45 has 20 stages of shift register circuits connected in series, and is configured to temporarily store the data D as a result of decoding.

Further, the data memory circuit 45 stores the data D, which is the decoding result of logic levels "1" and "-1".

After converting the data into logic level "1" and "0" data, respectively, the logic level is inverted based on the control signal SC output from the control circuit 46.

The control circuit 46 determines the transition of the precoat data Dpx (FIG. 13(D)) based on the result of multiplying the decoding result data D output from the multiplication circuit 48 and the predicted input value.
is detected, and a control signal S is output according to the detection result.

Thereby, the data D of the decoding result is inverted as necessary, and the pre-coated data is decoded.

Furthermore, the data memory circuit 45 is configured to have an exclusive OR circuit connected to its output stage, and thereby performs (1-D) arithmetic processing on the decoded precoated data.
Decode to playback data.

In this way, in the Viterbi decoding circuit 2B (30), by decoding the input data by utilizing the (1-D) relationship between the preceding and succeeding data, it is possible to avoid cases where noise is mixed and the CN ratio is low. However, it is now possible to decode data with significantly fewer bit errors.

The selection circuit 49 reproduces reproduced data D□ which is the decoded data decoded by the Viterbi decoding circuits 28 and 30.

and I) pat, and by sequentially switching the contacts, the data divided into an even number series and an odd number series is returned to the original arrangement and output.

(Gl-4) Decoding Circuit 50 By the way, in the class ① partial response method, instead of using the Viterbi decoding circuit, the reproduced signal SIF can be decoded based on the signal level of the reproduced signal.

That is, the output signal S output from the arithmetic processing circuit 20
Predetermined reference levels ■□□ and Vat□ are set for the signal level of F (FIG. 2 (D)), and the reference level V is set. 2. and V□2! By obtaining a comparison result between the output signal SF and the output signal SF, the output signal S can be decoded.

However, in the Viterbi decoding circuit 2B (30),
Since it uses the (1-D) correlation between data,
Data with fewer bit errors can be obtained than when decoding is performed based on the signal level.

Therefore, if the Viterbi decoding circuit is applied to a digital video tape recorder, the digital video signal can be reliably reproduced.

However, since data is decoded using the correlation between data, if a bit error occurs, there is a risk that a number of consecutive bits will occur (this is called error propagation below C).

Therefore, in this embodiment, the Viterbi decoding circuit 2B (
30) and a decoding circuit 50 that uses the signal level as a reference, bit errors can be reduced.

That is, as shown in FIG. 19, the decoding circuit 50 supplies the output signal SF to the peak detection circuit 51 to detect the rising signal level of the output signal SF.

Further, the peak detection circuit 51 divides the detection results to predetermined comparison reference levels ■□□ and ■□7! are generated and output to the non-inverting input terminals and inverting input terminals of comparison circuits 52 and 53, respectively.

On the other hand, the comparison circuits 52 and 53 receive the output signal SF at the remaining inverting input terminals and non-inverting input terminals, and output the comparison results to the exclusive OR circuit 54.

As a result, the amplitude of the output signal SF is set to the reference level V+tpy+ and V□8 via the exclusive OR circuit 54.
When the value changes more than 1, it is possible to obtain the reproduced data D Pam having the value l, and it is possible to decode the reproduced signal S0 using the signal level of the reproduced signal S0 as a reference.

(Gl-5) Switching times W! 56 As shown in FIG. 20, in the switching circuit 56, the reproduced data DP output from the Viterbi decoding circuits 28 and 30
IV is applied to the shift register circuit 58.

As shown in FIG. 21, the shift register circuit 58 receives a second clock signal 5ctC synchronized with the reproduced data DPIv.
Five stages of latch circuits operating as shown in FIG. 1(A)) are connected in series, so that playback data Dpmv
(FIG. 21(B)) and the reproduced data D□9 which is sequentially delayed by one clock period with respect to the reproduced data D07.
It is designed to output .

Further, the shift register circuit 58 outputs the reproduced data D PI
Delayed playback data D delayed by 5 clock cycles with respect to IV
□Latch circuit 60 following VDL (Figure 21 (D))
The signal is output to the switch circuit 61 via A.

On the other hand, the shift register circuit 62 is configured similarly to the shift register circuit 58, and the shift register circuit 62 is configured to
Reproduction data D, . . . of the decoding circuit 50.

(FIG. 21(C)).

Incidentally, the delay time of the delay circuit 63 is the reproduction data D□
This delay time is selected to be equal to the delay time of 9, so that the corresponding reproduced data D, , D□ are input to the shift register circuits 58 and 62 at the same timing.

Thus, in the shift register circuit 62, similarly to the shift register circuit 58, 5
Delayed reproduction data D2□ delayed by a clock cycle. , (second
1(E)) can be obtained, and the delayed reproduction data DPI can be obtained via the latch circuit 60B. , the switch circuit 61
It is designed to output to .

Furthermore, in the shift register circuit 62, it is possible to obtain the reproduced data D F I m delayed by one clock period sequentially with respect to the reproduced data D□3, and the reproduced data D PIN and the reproduced data D delayed by one clock period can be obtained. □ are applied to the remaining input terminals of the exclusive OR circuits 59A to 59E.

As a result, the reproduced data DPlv and the reproduced data D FIB are transmitted through the exclusive OR circuits 59A to 59M.
Detection result D C0, 4Po, D cosp+ where the logic level rises when the data of each bit does not match
, D cospz , D comps and D CQMP
4 (Fig. 21 (Fl) to (F5)) can be obtained.

In this way, the reproduced data D sequentially delayed by one clock period
PIV and □ are five exclusive OR circuits 5
By inputting data to 9A to 59H, a comparison result I) co□ can be obtained for five consecutive pieces of data.

The addition circuit 64 receives the comparison result. , and the comparison result D cowp with logic level "1". ~'I)co□
4 is added.

On the other hand, the comparator circuit 65 is configured to compare the addition result with predetermined reference data DrM, and thereby the value 2
When a larger addition result is obtained, the output signal I)11,
The logic level of 111 (FIG. 21(G)) is raised.

On the other hand, the AND circuits 66A to 66E
5, and receive the comparison results Dco of exclusive OR circuits 59A to 59E, respectively.
nptr, DI:0NFI, Dcoxrt, I)c
o□, and I)co□4, thereby output signal D W I N of the comparator circuit 65. rises, the comparison results of exclusive OR circuits 59A to 59E are displayed: Dcowro, DCOMPI, DcoMpz
%D,. 0. and DCO1lP4 are output to OR circuits 67A to 67E, respectively.

Therefore, when the output signal 41NI1 rises via the AND circuits 66A to 66B, the successive 5-bit comparison results D cospo , D CONFI , D co ,
tt, D. □, and. Switching data D generated by outputting M□! wo, Dsw+% Dtwz, Dsim
z and . . . (FIG. 21 (Hl) to (H5)) can be obtained.

The OR circuits 67A to 67E are each a latch circuit 67A.
The comparison results Dcosro are connected in series through 67E and output to the OR circuits 67A to 67E.
, Dco+4. +, Dca, 4pt, Dcomps
Andri,. , 4P4 is temporarily stored, and the following OR circuit 67B
It is designed to output from 67H to 67H.

As a result, the corresponding comparison result D
C0NFI, D co, 4y+, D C0NPZ,
I) co□3 and DCOMF4 can be obtained, and in this example, the comparison results are as follows. spo, DCC
IMPI, D conrz, D CQMP3 and DC
When the logic level of ONP4 rises, the switch circuit 6
1 contact from playback data D□9 to playback data D Full
It is designed to be switched.

Thus, only when two or more bits of consecutive five-bit data do not match, the output signal Dhl of the comparator circuit 65
Since the IHD is configured to rise, the reproduction data D, which is obtained by switching the mismatched data from the reproduction data DpHv of the Viterbi decoding circuit 28 and 30 to the reproduction data DPSm of the decoding circuit 50, (Fig. 21 (I) )), and the reproduced data D□ is transferred to the latch circuit 67.
It is designed to be output via .

In fact, when a bit error occurs in the Viterbi decoding circuit 28, 30, it is characterized by a series of bit errors, whereas in the decoding circuit 50, the bit error tends to occur sporadically.

Therefore, when counting the number of data that does not match among consecutive data, when the count value is large, there is a high probability that a bit error has occurred in the Viterbi decoding circuit, whereas when the count value is small, the probability that a bit error has occurred in the Viterbi decoding circuit is high. The probability that a bit error has occurred increases.

Therefore, only when the count value is large, the Viterbi decoding circuit 2
8.30 reproduction data D Decoding circuit 50 in place of PMV
Reproduction data D, 1. By outputting , bit errors can be reduced accordingly.

Thus, in this embodiment, the number of consecutive data is selected to be 5 bits, and when the count value exceeds 2, the reproduced data D psv is switched to D Pam and output.

Therefore, the playback data D psv and 76. Based on the comparison results of Viterbi decoding circuit 28.30 and decoding circuit 50
The reproduced data D pmv and D Full are switched and outputted, thereby making it possible to reduce bit errors.

(Gl-6) Processing of reproduced data In contrast, the error detection and correction circuit 71 processes the reproduced data D2. ((E) in FIG. 2), detects bit errors, corrects the bit errors, and then separates data into an audio signal SAPII and a video signal.

The data expansion circuit 72 receives the data of the video signal separated by the error detection and correction circuit 71, and expands the data in the opposite way to the data compression circuit 4.

In this way, the video signal Sv□ can be obtained via the digital-to-analog conversion circuit 73.

(Gl-7) Operation of the embodiment In the above configuration, the video signal Sv is converted into the digital video signal Dv by the analog-to-digital conversion circuit 2, and then the data D of about 25 [MB P S] is converted by the data compression circuit 4. compressed into

The compressed data D, together with the audio signal DA, is subjected to processing such as shuffling and addition of an error correction code in the error correction circuit 6, and is converted into recording data D□ of 30 [MBPS].

The recording data D1c is subjected to the arithmetic processing of equation (2) in the precoat circuit 8 and converted to precoat data DPI, and then divided into blocks and recorded on the magnetic tape 14, and at the same time, the standard of frequency 15 (MHz) is recorded. A preamble is formed that records the signal.

On the other hand, the reproduced signal 5IIF output from the magnetic heads 16A and 16B is inputted to the analog-to-digital conversion circuit 24 via the amplifier circuit 18, the equalizer circuit 19, and the arithmetic processing circuit 20, thereby converting the reproduced signal SRF
The signal level is converted into input data yk at the rising and falling cycles.

After the manual data y is divided into an even number series and an odd number series, it is applied to the Viterbi decoding circuits 28 and 30, whereby the input data yk is decoded into reproduced data DPIO (D?□).

Reproduction data D□. Andri 2. , are returned to their original arrangement in the selection circuit 49, and as a result, the Viterbi decoding circuit 28
and 30, decoded reproduction data D□9 is obtained.

On the other hand, the signal level of the output signal S of the arithmetic processing circuit 20 is detected by the demodulation circuit 50, and based on the detection result, the reproduced data D11. is decrypted.

Reproduction data D□, and D21. When the switching circuit 56 detects a match or mismatch in data in consecutive 5 bits, and when data with 2 or more bits of mismatch is obtained, the playback data D□, instead of the playback data D, □, is subjected to error detection and correction. The signal is outputted to the circuit 71, whereby reproduced data DP11 with reduced pings can be obtained.

In this way, the reproduced data DPI+ is transmitted to the error detection and correction circuit 71.
, a data expansion circuit 72 and a digital-to-analog conversion circuit 73, the video signal 5VPH is converted to
is converted to

(Gl-8) Effects of Embodiment According to the above configuration, the reproduced data D□7 of the Viterbi decoding circuit 28.30 and the reproduced data D23. By switching and outputting the reproduction data D pan instead of the reproduction data D PNV only when the number of consecutive data that do not match is equal to or greater than a predetermined value, based on the comparison result with the reproduction data D PNV,
Bit errors can be reduced, and thus it is possible to reproduce digital video signals recorded at high density and effectively avoid deterioration in image quality.

(G2) Second Embodiment FIG. 22, in which parts corresponding to those in FIG. 1 are denoted by the same reference numerals, shows a second embodiment.
The decoding circuit is constructed using the following.

That is, the exclusive OR circuit 75 converts the upper 2 bits of data D, &9. It is designed to receive the following.

Incidentally, the analog-to-digital conversion circuit 24 is configured to convert the output signal S into output data y in two's complement representation.

Therefore, as shown in FIG. 23, the upper 2 bits of data D
When either A or Dys rises to logic "1", it is possible to obtain reproduction data DPIm whose logic level rises to logic "1", and in this case, the signal level of output signal SF rises or falls significantly. , the logic level can be raised to logic "1".

In this way, the decoding circuit can be configured with one exclusive OR circuit 75, and the configuration of its subunits can be simplified.

According to the configuration shown in FIG. 22, a change in the upper two bits of the output data yk output from the analog-to-digital conversion circuit 24 is detected, and the reproduced signal S□ is decoded based on the detection result, thereby simplifying the configuration. A decoding circuit can be constructed using the above decoding circuit, and a video tape recorder with a simple construction can be obtained as a subdivision of the decoding circuit.

(G3) Third Embodiment FIG. 24, in which parts corresponding to those in FIG. Based on the standard, playback data D
Switch Psv and DP□.

That is, as described above, the Viterbi decoding circuits 28 and 30 create the likelihood data Δk and the predicted input value D3 by using the (1-D) correlation between the preceding and succeeding data, and also calculate the likelihood from the value. The input data yk is decoded based on the data Δk and the predicted input value.

Therefore, if the reproduction data D□ is output instead of the reproduction data D□9 only when the probability data Δk representing the probability of the data D is less than a predetermined value, reliable reproduction data D□ can be obtained. The reproduced data DPIM can be output in place of the reproduced data DPIV only when the reproduced data DPIV cannot be reproduced, and bit errors can be reduced accordingly.

Therefore, in this embodiment, the Viterbi decoding circuits 28 and 30 sequentially and alternately supply likelihood data Δk to the comparison circuit 78 in synchronization with the input data yk.

The comparison circuit 78 is configured to compare the values of the predetermined reference data DItF and the probability data Δ, and thereby switch the switch circuit 61 when the probability data Δk is less than a predetermined value. .

As a result, the reproduced data D0. When it is not certain, the reproduction data D□ is output instead of the reproduction data DPmV.

According to the configuration shown in FIG. 24, the reproduced data D of the Viterbi decoding circuits 28 and 30 is based on the probability data Δk.
By switching and outputting the reproduced data D□1 of the decoding circuit 50 and the reproduced data D□9, it is possible to output the reproduced data DFO instead of the reproduced data DPIIV when the reproduced data D□ is not certain, and the bits are accordingly reduced. Errors can be reduced.

(G4) Fourth Embodiment As shown in FIG. 25, in this embodiment, the playback data D
□9 and DPIm are switched and output.

That is, as shown in FIG. 26, in a video tape recorder, when the operation mode is switched from normal playback mode to variable speed playback mode, the envelope of the playback signal S□ (FIGS. 26(A) and (B)) changes. It changes into an abacus bead shape, and the signal level of the reproduced signal 5IIF partially decreases.

Therefore, in the portion where the signal level has decreased, bit errors increase in the Viterbi decoding circuits 28, 30 and decoding circuit 50.

In this case, in the decoding circuit 50, bit errors increase in accordance with the signal level of the reproduced signal S0.

However, in the Viterbi decoding circuit 28 and 30, since the correlation between the preceding and succeeding data is used, error transmission is unavoidable once a bit error occurs.In this case, when the signal level drops below a predetermined level, the bit Errors increase.

Therefore, in this embodiment, when the operation mode is switched from the normal playback mode to the variable speed playback mode, the playback data D PIN of the decoding circuit 50 is output in place of the playback data D□9 of the Viterbi decoding circuits 28 and 30. This is intended to reduce bit errors in variable speed playback mode.

That is, as shown in FIG. 27, a control circuit 80 having a microcomputer circuitry receives a variable speed playback mode switching signal S from the control circuit of the video tape recorder. . (FIG. 27(A)) is input, the control signal Sc (FIG. 27(B)) output to the switch circuit 6I is raised,
The output of the switch circuit 61 is switched from the reproduced data D PIV to the reproduced data D91 (FIG. 27(C)).

This makes it possible to reduce bit errors in the playback data D□ even when the video tape recorder switches to variable speed playback mode.

According to the configuration shown in FIG. 25, when the operation mode of the video tape recorder becomes the variable speed playback mode, the playback data D□7 of the Viterbi decoding circuit 28.
By outputting the reproduced data D□, it is possible to reduce bit errors in the reproduced data DPIl in the variable speed reproduction mode.

(G5) Fifth Embodiment As shown in FIG. 28, in this embodiment, the envelope of the reproduced signal SRF is detected, and based on the detection result, the reproduced data D□ and D Pal are switched and output. .

That is, as described above with reference to FIG.
When the signal level of
Bit errors increase more than Im.

Therefore, bit errors can be reduced by switching and outputting the reproduced data DP, v, and D□ using the signal level of the reproduced signal 5IIF as a reference.

Furthermore, by doing this, bit errors in the reproduced data DPI can be reduced not only when the signal level decreases in the variable speed reproduction mode, but also when the signal level of the reproduced signal S□ decreases due to dropouts, etc. can do.

That is, the envelope detection circuit 82 detects the reproduced signal SII
, is subjected to envelope detection, and the detected output signal is provided to the comparison circuit 83.

The comparison circuit 83 is configured to switch the contacts of the switch circuit 61 based on the comparison result between a predetermined reference level and the detected output signal, and when the signal level of the reproduced signal S□ decreases, the reproduced data D□ of the Viterbi decoding circuit 28.3o is changed. , the reproduction data DPI11 of the decoding circuit 5o is output.

According to the configuration shown in FIG. 28, a decrease in the signal level of the reproduced signal s0 is detected, and based on the detection result, the reproduced data D□ and D
By switching and outputting P, , it is possible to reduce bit errors in the reproduced data DPI in the variable speed reproduction mode or when dropout occurs.

(G6) Other embodiments (1) In the first embodiment described above, when the reproduced data DPMV and D Although the case has been described in which the reproduction data D□ is switched and output, the present invention is not limited to the case where the discrepancy is 2 bits or more, and various values can be selected.

In other words, the number of bits should be selected in accordance with the electromagnetic conversion characteristics of the electromagnetic conversion system, the data transmission rate, etc., so that the bit error in the reproduced data D□ is minimized. The number of bits may be changed accordingly.

Furthermore, since the conditions for minimizing bit errors may vary depending on the recording/reproducing state, etc., the probability data Δk output from the Viterbi decoding circuit, the signal level of the reproduced signal Sl, and the operation of the video tape recorder concerned. The number of bits may be switched depending on the mode or the like.

(2) Similarly, in the first embodiment described above, regarding the continuous 5-bit data, the reproduced data D□ and D□
, but the present invention is not limited to 5-bit data, and various values can be selected.

In this case as well, the number of bits can be selected to various values so as to minimize bit errors in the reproduced data D□, and may be selected depending on, for example, the type of magnetic tape, as well as the probability data Δk and the reproduced signal SIF. The number of bits may be switched depending on the signal level of the video tape recorder, the operation mode of the video tape recorder, etc.

(3) Further, in the first embodiment described above, the case was described in which the number of unmatched data is counted for the continuous playback data D□9 and D Pam, but the present invention, contrary to this, The number of data may be counted, and in this case, when the number of matching data is less than a predetermined value, the reproduction data DPmV may be switched to the reproduction data D□ and output.

(4) Further, in the first embodiment described above, the case was described in which the reproduced data D FIV is output when the reproduced data match, but the present invention, contrary to this, outputs the reproduced data D FIV and When D□, match, reproduction data D□ may be output.

In this case, if mismatched data is obtained and the number of mismatched data is less than a predetermined value, bit errors can be reduced by switching the mismatched data to reproduced data DPIV.

(5) Furthermore, in the second embodiment described above, a change in the upper two bits of the output data yk is detected, and the reproduction signal S is generated based on the detection result. Although the present invention is not limited to this, the point is that it is sufficient to detect changes in predetermined bits of the output data of the analog-to-digital conversion circuit 24, and if necessary, detect changes in, for example, the upper three bits. May be detected.

Furthermore, in this case, the envelope of the reproduced signal S0 may be detected, and the number of bits to be detected and the pattern thereof may be switched according to the detection result. In this way, the envelope can be detected and the pattern can be changed to follow changes in the signal level of the reproduced signal S□. Then, the reference level for decoding (i.e., V□Fl and V in FIG. 2(A)
(corresponding to □□) can be easily switched.

Also in this case, the number of bits to be detected depends on the type of magnetic tape, the certainty data Δk, the operating mode of the video tape recorder, etc.
The pattern may be switched.

(6) Furthermore, in the second embodiment described above, when the reproduction data D□7 and DP□ are switched and output based on the comparison result of the reproduction data D2.7 and □,
Although the case has been described in which a decoding circuit that detects a change in a predetermined bit output from the analog-to-digital conversion circuit 24 is applied, the present invention is not limited to this, and for example, this decoding circuit can be applied to the third to fifth embodiments. It may also be applied.

(7) Furthermore, in the above embodiment, a case was described in which the input data y, yk, 5, . . . were decoded using the Viterbi decoding circuit 28. The present invention is not limited to this, and can be widely used with various Viterbi decoding circuits.

In this case, in the third embodiment, instead of the certainty data Δ described above for equations (4) to (9), the certainty data Δk expressed by the following equation % equation % (10) is used. Just use it.

That is, as shown in FIG. 29, in a general Viterbi decoding circuit, when obtaining a decoding result for one piece of successive data, the probability up to data d8 is set to 1.
When transitioning from the previous value 1 data and the previous value - 1
The decoded data is obtained by detecting the transition with greater probability.

Therefore, r represents the probability of transitioning from the previous value 1 data. , ゛ and the one before! f, which represents the probability of transitioning from data of −1, 3. −
The probability data Δk of equation (10) expressed as the difference between
Even when using the Viterbi decoding circuit 28.30 to which Ferguson's algorithm is applied, bit errors can be reduced.

(8) Furthermore, in the above-mentioned embodiment, as a result of comparing the playback data DIIV and D
Based on the signal level of the reproduced signal S□, the reproduced data D
Although the case has been described in which PIV, V, and ■ are switched and output, the present invention is not limited to this, and by combining these, for example, based on the comparison result of the reproduction data DP, V, and □ and the probability data Δk. , playback data D PIV
and D□ may be switched and output.

(9) Further, in the above-described embodiments, a case was described in which a digital video signal was recorded and reproduced, but the present invention is not limited to this, and can be widely applied to cases in which various digital signals are reproduced.

0ΦFurthermore, in the above-mentioned embodiment, a case was described in which data recorded on a magnetic tape is reproduced, but the present invention is not limited to magnetic tapes, but can be widely applied to magnetic reproducing apparatuses using magnetic recording media. .

Effects of the H invention As described above, according to the first invention, by switching and outputting the reproduced data of the Viterbi decoding circuit and the reproduced data of the decoding circuit that decodes the reproduced signal based on the signal level of the reproduced signal. , it is possible to obtain a magnetic reproducing device that can effectively reduce bit errors.

In this case, according to the second to fifth inventions, a magnetic reproducing device is obtained in which bit errors are reduced by switching based on the comparison result of the reproduced data, the certainty data, the operation mode, and the signal level of the reproduced signal, respectively. be able to.

Furthermore, according to the sixth invention, by detecting a change in a predetermined bit of data output from the analog-to-digital conversion circuit to the Viterbi decoding circuit, it is possible to easily obtain reproduced data based on the signal level of the reproduced signal. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a video tape recorder according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining its operation, and FIG. 3 is a block diagram showing a precoat circuit.
Figure 4 is a characteristic curve diagram showing the frequency characteristics of the magnetic recording/reproducing system, Figure 5 is a characteristic curve diagram explaining the class ■ partial response method, Figure 6 is a route map showing pre-coated data, and Figure 7 is a characteristic curve diagram showing the frequency characteristics of the magnetic recording/reproducing system. Block diagram showing the arithmetic processing circuit, No. 8
10 and 11 are block diagrams showing an equivalent circuit of a magnetic recording/reproducing system. FIG. 12 is a block diagram showing a Viterbi decoding circuit. 13 to 18 are diagrams to explain the operation, FIG. 19 is a block diagram showing the decoding circuit, FIG. 20 is a block diagram showing the switching circuit, and FIG. 21 is a signal waveform to explain the operation. 22 is a block diagram showing the second embodiment, FIG. 23 is a chart for explaining its operation, FIG. 24 is a block diagram showing the third embodiment, and FIG. 25 is a block diagram showing the third embodiment.
The figure is a block diagram showing the fourth embodiment, FIG.
FIG. 7 is a signal waveform diagram for explaining the operation, FIG. 28 is a block diagram showing the fifth embodiment, and FIG. 29 is a route diagram for explaining the operation. l...Video tape recorder, 8...
Precoat circuit, 14...Magnetic tape, 20.
... Arithmetic processing circuit, 24 ... Analog-digital conversion circuit, 28.30 ... Viterbi decoding circuit, 50 ... Decoding circuit, 56 ...・Switching circuit.

Claims (6)

[Claims] (1) In a magnetic reproducing device that uses the partial response method to reproduce predetermined recorded data recorded on a magnetic recording medium, analog-to-digital conversion converts the signal level of the reproduced signal into a digital signal at a predetermined period. a Viterbi decoding circuit that decodes the reproduced signal based on output data output from the analog-to-digital conversion circuit; a decoding circuit that decodes the reproduced signal based on the signal level of the reproduced signal; 1. A magnetic reproducing device comprising a Viterbi decoding circuit and a switching circuit that switches and outputs decoded data decoded by the decoding circuit. (2) The switching circuit switches and outputs the decoded data decoded by the Viterbi decoding circuit and the decoding circuit based on a comparison result of the decoded data decoded by the Viterbi decoding circuit and the decoding circuit. A magnetic reproducing device according to claim 1, characterized in that the magnetic reproducing device is configured to do the following. (3) The switching circuit, based on the certainty data of the Viterbi decoding circuit,
2. The magnetic reproducing device according to claim 1, wherein the Viterbi decoding circuit and the decoded data decoded by the decoding circuit are switched and outputted. (4) A patent claim characterized in that the switching circuit switches and outputs the Viterbi decoding circuit and the decoded data decoded by the decoding circuit based on the operation mode of the magnetic reproducing device. The magnetic reproducing device according to item 1. (5) The switching circuit is configured to switch and output the Viterbi decoding circuit and the decoded data decoded by the decoding circuit based on the signal level of the reproduced signal. The magnetic reproducing device according to scope 1. (6) A patent claim characterized in that the decoding circuit detects a change in a predetermined bit of the output data output from the analog-to-digital conversion circuit, and decodes the reproduced signal based on the detection result. Range 1st term, 2nd term, 3rd term
5. The magnetic reproducing device according to item 4, item 5, or item 5.