TW480404B - Memory card with signal processing element - Google Patents

Abstract

A memory card having a memory bus controller is provided which card has a signal processing element preferably a digital signal processor (DSP) thereon, which card is used in a computer system as add-on memory. Also, a method of using such a card in a computer system is provided. The memory bus controller and the signal processing element are programmed to pass all the addresses in the memory on the card and the associated data received from the CPU to the signal processing element where they are stored in memory. The signal processing element is programmed to perform selected operations on the addresses and/data irrespective of whether the signal processing element has control of the system bus. These operations can include keeping track of read/write operations and locations of these operations. This information can be easily accessed by the computer system and used for memory optimization. The DSP can also ""snoop"" the memory bus when it is unavailable to the control of the DSP, i.e. when the system has control of the memory bus. The memory bus controller passes addresses and data to the DSP as it is received. When the DSP receives addresses that are in its normal or regular range, or other selected ranges, for processing in the memory. The DSP can capture the data and do ""early"" processing or pre-processing of this information before the DSP gains control of the memory.

Description

480404 V. Description of the Invention (1) Background of the Invention The present invention relates generally to a memory card having a signal processing element thereon; and particularly to a memory bus having a signal processing element thereon when the memory bus is not available to the signal processing element , Related to the memory SI MM s (single coaxial memory module) or DI MM s (dual coaxial memory module) that receive data from the selected address and perform operations on it. Background Information The use of signal processing components, especially digital signal processing components (DSPs), is being proposed as components on memory cards and memory boards for use in computers. The purpose is to allow DSP to use some parts of memory when that memory is not being used by the system. This provides significant cost savings by making a sufficiently large block of memory available for DSP without adding a completely separate system memory bus, and additional memory to the DSP. This generates more computing power at a lower cost. However, traditionally, the DSP can access the memory only when the system does not control the memory bus of the free space. This keeps D S P idle and therefore low utilization for a considerable period of time. SUMMARY OF THE INVENTION In accordance with the present invention, a memory card having a memory bus controller is provided, the card having the same. One is preferably a signal processing element of a digital signal processor (DSP). The card is used as additional memory in a computer system. In addition, a method for using such a card in a computer system is provided. The memory bus controller and signal processing components are planned to be transferred to the memory on the card

O: \ 64 \ 64666.ptd Page 6 480404 V. All the addresses in the description of the invention (2), and the relevant data received from the central processing unit, to the signal processing components stored in the memory. The signal processing element is planned to perform selected operations on those addresses and data, regardless of whether the signal processing element controls the system bus. These operations may include tracking read / write operations and the location of these operations. This information can be easily accessed by computer systems and used for memory optimization. When D S P control is not available, that is, when the system controls the memory bus, D S P can also detect the π memory bus. When D S P receives the address of its processing or normal range in memory, or other selected range addresses, the memory bus controller passes the address and data to D S P as it receives it. Before DS can gain control of the memory, DS can retrieve data and perform "early" processing or pre-processing of this information. Brief Description of the Drawings Figure 1 is a high-order graphic of DIMM with a digital signal processor (DSP) mounted thereon according to the present invention; and Figure 2 is a flowchart of the "detection" logic of DSP according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT (s) Referring now to those drawings, and now, FIG. 1, a specific embodiment of the present invention is shown as being implemented in a personal computer 6 having a central processing unit. A memory module 8 is provided, such as a D I M M or S I M M, which includes a printed circuit card 10 having one of a plurality of memory chips in the form of synchronous dynamic random access memories (SDRAMs) 12a to 12h. (It should be understood that the number of SDRAMs can be more or less, and they can be arranged in one or more storage areas, as is well known in the art.) Synchronous DRAMs 12a-12h, yes traditional·

480404 V. Description of the invention (3) SDRAMs' are configured and arranged to store both data bits and check bits written to them by the computer system 6. Each of the SDRAMs 12a-12h has a memory location 13a-1 3h reserved for a signal processing element which will now be described. The circuit card 10 has a memory bus, which includes a memory data bus 4 and a memory address / control bus 16; a system clock line 18 ', a wait line 2 0, and an interrupt request also appear. Line 2 2. Memory data bus 1 4 ′ Memory address / control bus 丨 6, system clock 8, wait line -20 and interrupt request line 22 are all connected to the input / output connector, sometimes called pin 26. Those input / output connectors 26 provide an interface to the system memory controller 28, which is part of the central processing unit or computer 6. The system memory controller 28 also controls a peripheral connection interface (pc I) bus_30 (and other optionally not shown buses). The PCI bus 30 has a device such as the code 32 on it. The memory card 10 also has a memory bus controller 34, which is connected to the memory data bus 14, the memory address / control bus 16, the system clock 18, 'wait line 2', and interrupt request line 2 2. The bus controller 34 is connected to a signal processing element 36, which in a preferred embodiment is a digital signal processor (DSP). A particularly useful DSP is any of the TMS 320C54X series produced by Texas Instruments. This particular DSP series product includes an external cache or draft memory 38. The memory bus controller 34 and the DSP 36 are used to transfer various control signals, addresses, and data between the memory bus controller 34 and the DSP 36. One chip address bus 40 and one chip data bus Row 4 2 and control line 44 are connected to each other. In addition, an interrupt bus 46 and an indicator

Page 8 480404 V. Description of the Invention (4) The bus 48 connects the bus controller 34 to the DSP 36. Memory data bus 1 4 has f E T (Field Effect Transistor) switch 5 0 on it. (It should be understood that the memory data bus 14 is composed of multiple lines, one line per bit, and one FET 5 per bit line.) The memory data bus 14 may be an 8-bit bus, a 6-bit bus' a 32-bit bus, or a 64-bit bus, and it does include any number of data A data bus of any size of the line is required ... In addition, a system address / control bus 16 includes a FET switch 52. In the specific embodiment of Xingfujia, the system clock line 8 is also connected to DSp 36. However, if the timing used on the card is different from the timing used in the CPU, it should be understood that a separate clock can be provided to This DSP. However, the preferred embodiment for the big case is to use the system clock to remember those functions and functions on the body module. … = Line 5? '5 8 level one or two-line serial bus, provided to the connector to two contacts 26, the two contacts 26 and the system memory control: For example, the memory is-attached, X you 1a The present invention can be combined in any memory subsystem to go to 4 'whether it is a " pluggable " additional memory. Α 二 ί When the group t has not been fetched or written by the CPU through the memory controller 28, or other functions, the DSP is set to cause: When these tasks are performed, FETs are, ^, if, when the central processing unit wants to access the memory module s 疋, the memory controller 2δ can address the memory resources.

Page 9 480404 V. Description of the invention (5) The material bus 14 and the memory module 8 on the memory address / control bus 60, so as to perform the traditional reading of SDRAM s 1 2 a-1 2 h / Write operation. According to the invention, D S P 3 6 performs several functions. One of these functions is under the control of the memory bus controller 34, receiving system writes from the memory bus controller 34 to DRAM s 1 2 a-1 2 h, and reading from it All addresses and related information are taken, regardless of whether those addresses are in the DSP range 1 3 a-1 3 h. A program is loaded into the DSPS cache memory 38, which will stamp the time and track the activity, for example the number of reads and writes and the location where at least some data is stored. This information is stored and accessed by the computer system 6 through the memory bus controller 34, and this information is used for memory optimization. These operations may include, for example, but are not limited to, time domain analysis of addresses / data, and spectral analysis (F F T or D C T) to determine hot spots in memory. System 6 can use this data to optimize the distribution of the data, and to maximize execution efficiency and minimize power requirements. This activity of D S P 3 6 occurs in the system, rather than D S P, which controls the period of memory, thus increasing the use of D S P 3 6. Another function that DSP 3 6 can perform is to write π-probe to those addresses (or other selected addresses if needed) in areas 13a-13h of memory chips 12a-12h allocated to DSP 3 6 π system bus. If there is a write to an address in this range, the DSP 36 can retrieve the address and data and perform any necessary early processing operations, even if the DS P 36 cannot access the memory chip 1 2 a-1 2 h. When the information from the central processing unit of the computer system 6 is received, it is stored in the cache memory 38 and then discarded when the pre-processed information is available and stored in the cache memory 38. Then when D S P 3 6 take

O: \ 64 \ 64666.ptd Page 10 480404 V. Description of the invention (6) When the DRAMs 12a-12h are accessed, it will have pre-processed information and can write this information in its processed form Enter the memory chip address in the allocated locations 1 3 a-1 3 h. These early processing operations may include determining the frequency of the address by performing a Fourier Transforni (FFT). Data compression can also be performed, and the output of a finite impulse response (F I R) filter used as a sampler of an analog to digital converter is calculated and written to the address in the area 1 3 a-1 3 h. If necessary, for example, if the bus controller 34 operates at a faster speed than D S P 36, a bus controller 70 may be provided with a buffer 70 for data to be written to the DSP 36. Figure 2 is a flow chart describing the operation of a program to detect the π system bus to enable the DSP 36 to perform early processing operations. After the main system is initialized. If the detection program has not yet been stored, the main processor or the central The processor 6 loads the π-detection program to be executed by the DS P 36, and enters the cache or manuscript memory 38. (If necessary, the detection program can be made to reside in the cache 38 of the DS P 36. To avoid the need to load this program during the initialization of the CPU. However, it is better to have this program reside in the system 6 so that various programs can be used, not just those that are permanently stored in the cache 3 8 Within.) The central processing unit of computer system 6 enables the memory bus controller detection logic to detect the logic in DS P 36 to "detect" the selected address range, which will usually be allocated to DS P 3 6 address range, but may also include addresses outside this range. Then the computer 6 starts normal operation and accesses the DRAM memory 1 2 a-12 h with the memory controller as needed. Π detection program in D S P 3 6 π monitor memory bus control

O: \ 64 \ 64666.ptd Page 11 480404 V. Description of Invention (7) Controller 34.

When it finds an address in the π probe π logic or program range of the address, the found address and related data and access time are stored in the buffer 7 (if any) ' And an interrupt is sent from the bus controller φ |] to the DSP 36 on the interrupt bus 4 6. (If D S P 36 is at least as fast as the memory bus controller 34, then a buffer may not be needed in the memory bus controller 34.) In such a case, the address, related data and time stamp are passed directly to DS 36. Then DSP 3 6 accesses this address and data and time stamp in buffer 7 0 of memory bus controller 3 4 and stores this in cache 3 0 0 and then DSP 36 executes its Regardless of the planned processing algorithm (for example, FFT or FIT waver or data compression), the processed results are stored in the cache memory 38, and the received data that is no longer needed is discarded. If the DSP 3 + 6 has not approved the access to the memory bus, it continues to detect the memory, the bus controller's address in the range it has planned, and the reception and processing are appropriate = data. When the access of § () 36 #DRAMs i2a_12h is approved, the pre-processed result is written from cache 38 to the bits pointed to in DRAMs 12 & -12 ^ 1 ^% #

fThis ’, by this, the detection function—DS ° P 36 can handle the blame in any pre-planned crime address’ even though p 36 does not control the memory bus. 0

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Claims (1)

480404 VI. Application Patent Scope 1. A memory module of a computer system with a central processing unit, comprising: a printed circuit card; a memory chip on the printed circuit card; a memory on the printed circuit card A memory bus control element configured to communicate with the memory chip and the memory bus; a switch in the memory bus to selectively connect and separate the memory bus and the memory bus A central processing unit; a signal processing element on the printed circuit card, configured to communicate with the memory bus control element and the memory chips via the memory bus control element, and to control the memory bus control element Programming in the system to pass the selected address and related data from the central processing unit to the signal processing element; the signal processing element is planned to operate on the received data; and in the memory bus controller The program planning includes selectively connecting and separating the signal processing element via the memory bus controller. And the programming of these memory chips. 2. For example, the memory module of the scope of patent application, wherein the selected address includes all the addresses of the memory chip on the memory card. 3. The memory module of item 1 of the patent application scope, in which the area of the memory chip is reserved for the signal processing element, and those selected addresses include the reserved address less than all the addresses of the memory chip. O: \ 64 \ 64666.ptd Page 13 480404 t. Patent application scope 4. For the memory module of the first patent application scope, the program planning in the signal processing element includes when the signal processing element When separated from the memory chip, the programming of the data processing function is performed. 5. For the memory module of the fourth scope of the patent application, the programming in the signal processing element includes writing the data processed by the signal processing element when the signal processing element has the access right of the memory chip. To the memory chip. 6. The memory module according to item 1 of the patent application scope, wherein the signal processing element includes a cache memory for storing data received from the central processing unit. 7. For the memory module in the first item of the patent application scope, the memory bus control element includes a program plan from the central processing unit to write the selected program to the signal processing element. 8. If the memory module of the first patent application scope, the signal processing element is a digital signal processor. 9. For example, the memory module of the scope of patent application, wherein the program planning in the signal processing element includes a program planning for performing a spectral analysis to determine a hot spot in the memory. 10. The memory module according to item 3 of the scope of patent application, wherein the program planning in the signal processing element includes executing a selection from a group of fast Fourier transform, data compression, and finite impulse response filters. Programming of at least one of the operations. 1 1. A computer system including a central processing unit, including a memory subsystem, the memory subsystem including: Page 14 480404 VI. Patented memory chip; a memory bus; a memory bus control element configured to communicate with the memory chip and the memory bus; the memory bus in the memory bus A switch to selectively connect and separate the memory bus and the central processing unit; a signal processing element configured to communicate with the memory bus control element and the memory chips via the memory bus control element; Programming in the memory bus control element to pass the selected address and related data from the central processing unit to the signal processing element; the signal processing element is planned to operate on the received data; and The program planning in the memory bus controller includes a program planning for selectively connecting and separating the signal processing element and the memory chips via the memory bus controller. 1 2 · The computer system according to item 11 of the patent application scope, wherein the selected address includes all addresses of the memory chip on the memory card. 1 3 · The computer system of item 11 in the scope of patent application, in which the area of the memory chip is reserved for the signal processing element, and those selected addresses including the reserved address are less than all the addresses of the memory chip. 14. The computer system according to item 11 of the scope of patent application, wherein the program planning in the signal processing element includes a program planning for performing a data processing function when the signal processing element is separated from the memory chip. 1 5. The computer system according to item 14 of the scope of patent application, wherein the signal Page 15 480404 VI. Scope of patent application The program planning in the processing element includes the program planning of writing the data processed by the signal processing element into the memory chip when the signal processing element has the access right of the memory chip. 16 · The computer system according to item 11 of the patent application scope, wherein the signal processing element includes a cache memory for storing data received from the central processing unit. \ 1 7 · If the computer system of item 11 of the scope of patent application, the memory bus control element includes the program planning from the central processing unit to write the selected program to the signal processing element. 1 8 · The computer system according to item 11 of the patent application scope, wherein the signal processing element is a digital signal processor. 19 · The computer system according to item 12 of the scope of patent application, wherein the program planning in the signal processing element includes program planning for performing a spectral analysis to determine the hot spots in the memory. 2 〇 The computer system according to item 13 of the patent application scope, wherein the program planning in the signal processing element includes executing a selection from a group of fast Fourier transform, data compression, and finite impulse response filters Programming of at least one operation. 2 1. —A method for operating a memory subsystem of a central processing unit connected to a computer system, and the memory subsystem has a selectively connectable to the central processing unit and is controlled by a memory bus A memory bus controlled by the component and a signal processing component connected to the memory bus control component include the following steps: passing the selected address and related data from the central processing unit to the Page 16 480404 VI. Patent application range signal processing element; performing the operation of the data transmitted from the central processing unit in the signal processing element; and selectively connecting the signal processing through the memory bus control element Components to the memory chips or the central processing unit. 2 2 · According to the 21st winter method in the scope of patent application, wherein the selected address includes all addresses of the memory chip on the memory card. 2 3 · The method according to item 21 of the patent application, wherein the area of the memory chip is reserved for the signal processing component, and those selected addresses include the reserved address less than all the addresses of the memory chip. 2 4. The method according to item 21 of the patent application scope, wherein when the signal processing element is separated from the memory chip, the signal processing element performs a data processing function. 25. The method of claim 24, wherein when the signal processing element has access to the memory chip, the processing element writes the data it processes to the memory chip. 26. The method of claim 21, wherein the signal processing element includes a cache memory for storing data received from the central processing unit. 2 7. The method according to item 21 of the patent application scope, wherein the memory bus control element includes a program plan from the central processing unit to write the selected program to the signal processing element. 2 8. The method according to item 21 of the patent application scope, wherein the signal processing element is a digital signal processor. Page 17 480404 VI. Patent Application Range 2 9. The method according to item 22 of the patent application range, wherein the signal processing element performs a spectral analysis to determine the hot spots in the memory. 30. The method of claim 21, wherein the signal processing element performs at least one operation selected from the group of fast Fourier transform, data compression, and finite impulse response filters. 3 1 · If the memory module of the first patent application scope is further characterized by a buffer in the memory bus controller for temporarily storing data, address, And time information. 3 2 · The computer system according to item 11 of the patent application scope is further characterized by a buffer in the memory bus controller for temporarily storing data, address, and time before the signal processing component is retrieved. Information. 3 3 · The method according to item 21 of the scope of patent application, further characterized by a buffer in the memory bus controller, for 'temporarily storing lean materials, addresses, and time before the signal processing element operates. Information. Page 18