TW480404B - Memory card with signal processing element - Google Patents

Memory card with signal processing element Download PDF

Info

Publication number
TW480404B
TW480404B TW089115139A TW89115139A TW480404B TW 480404 B TW480404 B TW 480404B TW 089115139 A TW089115139 A TW 089115139A TW 89115139 A TW89115139 A TW 89115139A TW 480404 B TW480404 B TW 480404B
Authority
TW
Taiwan
Prior art keywords
memory
signal processing
processing element
patent application
memory bus
Prior art date
Application number
TW089115139A
Other languages
Chinese (zh)
Inventor
Bruce G Hazelzet
Christopher P Miller
Clarence R Ogilvie
Paul C Stabler
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/386,543 external-priority patent/US6446163B1/en
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW480404B publication Critical patent/TW480404B/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

A memory card having a memory bus controller is provided which card has a signal processing element preferably a digital signal processor (DSP) thereon, which card is used in a computer system as add-on memory. Also, a method of using such a card in a computer system is provided. The memory bus controller and the signal processing element are programmed to pass all the addresses in the memory on the card and the associated data received from the CPU to the signal processing element where they are stored in memory. The signal processing element is programmed to perform selected operations on the addresses and/data irrespective of whether the signal processing element has control of the system bus. These operations can include keeping track of read/write operations and locations of these operations. This information can be easily accessed by the computer system and used for memory optimization. The DSP can also ""snoop"" the memory bus when it is unavailable to the control of the DSP, i.e. when the system has control of the memory bus. The memory bus controller passes addresses and data to the DSP as it is received. When the DSP receives addresses that are in its normal or regular range, or other selected ranges, for processing in the memory. The DSP can capture the data and do ""early"" processing or pre-processing of this information before the DSP gains control of the memory.

Description

480404 五、發明說明(1) 發明背景 發明領域 本發明大體與其上有信號處理元件的記憶卡有關;且特 別是與當記憶體匯流排對信號處理元件是不可得時,其上 具有信號處理元件,以從選擇的位址接收資料並在其上執 行運作的記憶體S I MM s (單同軸記憶體模組)或D I MM s (雙同 軸記憶體模組)有關。 背景資訊 信號處理元件的使用,特別是數位信號處理元件 (D S P s ),正提出當成記憶卡和記憶板上的元件以使用在電 腦中。其目的是當那個記憶體未被系統利用時,允許D S P 使用記憶體的某些部分。藉由使記憶體充分地大的區塊可 為D S P使用,而不增加一完全分開的系統記憶體匯流排、 和額外的記憶體給DSP,這提供了重大的費用節省。這以 較低的成本產生較多的計算能力。然而,傳統上,只有當 系統未控制閒置空間的記憶體匯流排時,DSP才可存取記 憶體。這維持D S P空閒而因此,對相當時間期間低度利 用。 發明概要 依照本發明,提供一種具有一記憶體匯流排控制器的記 憶卡,該卡上有。一最好為一數位信號處理器(D S P )的信號 處理元件。該卡使用在一電腦系統中當成附加記憶體。另 外,提供在一電腦系統中使用一此種卡的方法。記憶體匯 流排控制器和信號處理元件規劃成,傳遞在卡上的記憶體480404 V. Description of the Invention (1) Background of the Invention The present invention relates generally to a memory card having a signal processing element thereon; and particularly to a memory bus having a signal processing element thereon when the memory bus is not available to the signal processing element , Related to the memory SI MM s (single coaxial memory module) or DI MM s (dual coaxial memory module) that receive data from the selected address and perform operations on it. Background Information The use of signal processing components, especially digital signal processing components (DSPs), is being proposed as components on memory cards and memory boards for use in computers. The purpose is to allow DSP to use some parts of memory when that memory is not being used by the system. This provides significant cost savings by making a sufficiently large block of memory available for DSP without adding a completely separate system memory bus, and additional memory to the DSP. This generates more computing power at a lower cost. However, traditionally, the DSP can access the memory only when the system does not control the memory bus of the free space. This keeps D S P idle and therefore low utilization for a considerable period of time. SUMMARY OF THE INVENTION In accordance with the present invention, a memory card having a memory bus controller is provided, the card having the same. One is preferably a signal processing element of a digital signal processor (DSP). The card is used as additional memory in a computer system. In addition, a method for using such a card in a computer system is provided. The memory bus controller and signal processing components are planned to be transferred to the memory on the card

O:\64\64666.ptd 第6頁 480404 五、發明說明(2) 中所有位址、和從中央處理器所收到的相關資料,到它們 儲存於記憶體中的信號處理元件。信號處理元件規劃成對 那些位址和資料執行所選擇的運作,不論此信號處理元件 是否控制系統匯流排。這些運作可包括追蹤讀取/寫入運 作和這些運作的位置。此資訊可容易地由電腦系統存取, 和用來做記憶體最佳化。 當對D S P的控制是不可得時,也就是當系統控制記憶體 匯流排時,D S P也可π探測π記憶體匯流排。當D S P接收在它; 對記憶體中的處理之規定或正常範圍、或其他所選擇範圍 的位址時,記憶體匯流排控制器如它所收到的一樣傳遞位 址和資料到D S Ρ。在D S Ρ取得記憶體的控制之前,D S Ρ可擷_ 取資料和進行此資訊的”早期”處理或預先處理。 圖式概述 圖1是依照本發明其上裝設有一數位信號處理器(DSP)的 D I Μ Μ之一高階圖形;和 圖2是依照本發明D S Ρ的”探測”邏輯之一流程圖。 較佳具體實施例(s )詳述 現在參照那些圖式而,目前,圖1 ,本發明的一具體實 施例顯示為實施在有一中央處理器的一個人電腦6中。提 供一記憶體模組8,例如一 D I Μ Μ或S I Μ Μ,其包括具有同步 動態隨機存取記憶體(SDRAMs ) 12a到12h形式的多個記憶^ 晶片之一印刷電路卡10。(應該了解的是SDRAMs的數目可攀 能較多或較少,且它們可安排在一或更多的儲存區中,如 該項技藝中所廣為週知。)同步DRAMs 12a-12h,是傳統的·O: \ 64 \ 64666.ptd Page 6 480404 V. All the addresses in the description of the invention (2), and the relevant data received from the central processing unit, to the signal processing components stored in the memory. The signal processing element is planned to perform selected operations on those addresses and data, regardless of whether the signal processing element controls the system bus. These operations may include tracking read / write operations and the location of these operations. This information can be easily accessed by computer systems and used for memory optimization. When D S P control is not available, that is, when the system controls the memory bus, D S P can also detect the π memory bus. When D S P receives the address of its processing or normal range in memory, or other selected range addresses, the memory bus controller passes the address and data to D S P as it receives it. Before DS can gain control of the memory, DS can retrieve data and perform "early" processing or pre-processing of this information. Brief Description of the Drawings Figure 1 is a high-order graphic of DIMM with a digital signal processor (DSP) mounted thereon according to the present invention; and Figure 2 is a flowchart of the "detection" logic of DSP according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT (s) Referring now to those drawings, and now, FIG. 1, a specific embodiment of the present invention is shown as being implemented in a personal computer 6 having a central processing unit. A memory module 8 is provided, such as a D I M M or S I M M, which includes a printed circuit card 10 having one of a plurality of memory chips in the form of synchronous dynamic random access memories (SDRAMs) 12a to 12h. (It should be understood that the number of SDRAMs can be more or less, and they can be arranged in one or more storage areas, as is well known in the art.) Synchronous DRAMs 12a-12h, yes traditional·

480404 五、發明說明(3) SDRAMs ’配置和安排成儲存由電腦系統6寫入到它們的資 料位元和檢查位元兩者。SDRAMs 12a—12h的每一個有記憶 體位置13a-1 3h保留給目前將描述的一信號處理元件。電 路卡1 0有一記憶體匯流排,其包括一記憶體資料匯流排丨4 和一記憶體位址/控制匯流排1 6 ;也出現一系統時鐘線路 1 8 ’ 一等待線路2 〇和一中斷請求線路2 2。記憶體資料匯流 排1 4 ’記憶體位址/控制匯流排丨6,系統時鐘8,等待線路-20和中斷請求線路22全部連接到輸入/輸出連接器,有時· 稱為接腳26。那些輸入/輸出連接器26提供對系統記憶體 控制器28的一介面,其為中央處理器或電腦6之一部份。 系統記憶體控制器28也控制一週邊連接介面(pc I)匯流排_ 30(和其他可選擇地未顯示之匯流排)。pci匯流排3〇其上 有例如編碼3 2的裝置。 記憶卡1 0也有一記憶體匯流排控制器34,其連接到記憶 體資料匯流排1 4,記憶體位址/控制匯流排1 6,系統時鐘 1 8 ’等待線路2 〇,和中斷請求線路2 2。匯流排控制器3 4連 接到一信號處理元件3 6,其在較佳具體實施例中,是一數 位信號處理器(D SP )。一種特別地有用的DSP是由德州儀器 (Texas Instruments)公司所生產的TMS 320C54X系列的任 何一種。這個特定的DSP系列產品包括一外部快取或草稿馨 薄記憶體38。記憶體匯流排控制器34和DSP 36由,在記憶 體匯流排控制器34和DSP 36之間傳遞各種控制信號、位址· 和資料的,一晶片位址匯流排4〇、一晶片資料匯流排4 2和 控制線路44互相連接。另外,一中斷匯流排46和一指示器480404 V. Description of the invention (3) SDRAMs' are configured and arranged to store both data bits and check bits written to them by the computer system 6. Each of the SDRAMs 12a-12h has a memory location 13a-1 3h reserved for a signal processing element which will now be described. The circuit card 10 has a memory bus, which includes a memory data bus 4 and a memory address / control bus 16; a system clock line 18 ', a wait line 2 0, and an interrupt request also appear. Line 2 2. Memory data bus 1 4 ′ Memory address / control bus 丨 6, system clock 8, wait line -20 and interrupt request line 22 are all connected to the input / output connector, sometimes called pin 26. Those input / output connectors 26 provide an interface to the system memory controller 28, which is part of the central processing unit or computer 6. The system memory controller 28 also controls a peripheral connection interface (pc I) bus_30 (and other optionally not shown buses). The PCI bus 30 has a device such as the code 32 on it. The memory card 10 also has a memory bus controller 34, which is connected to the memory data bus 14, the memory address / control bus 16, the system clock 18, 'wait line 2', and interrupt request line 2 2. The bus controller 34 is connected to a signal processing element 36, which in a preferred embodiment is a digital signal processor (DSP). A particularly useful DSP is any of the TMS 320C54X series produced by Texas Instruments. This particular DSP series product includes an external cache or draft memory 38. The memory bus controller 34 and the DSP 36 are used to transfer various control signals, addresses, and data between the memory bus controller 34 and the DSP 36. One chip address bus 40 and one chip data bus Row 4 2 and control line 44 are connected to each other. In addition, an interrupt bus 46 and an indicator

第8頁 480404 五、發明說明(4) 匯流排48將匯流排控制器34連結到DSP 36。 記憶體資料匯流排1 4其上有f E T (場效電晶體)開關5 0。 (應該了解的是記憶體資料匯流排1 4由多重線路組成,每 —位元一條線路,且對每_位元線路有一FET 5 〇)。記憶 體資料匯流排1 4可能是一 8位元匯流排,一丨6位元匯流 排’一 3 2位元匯流排,或一 6 4位元匯流排,而的確包括無 論何種數目的資料線路的任何大小之資料匯流排是必需… 的。另外,在系統位址/控制匯流排16中有FET開關52。在 幸父佳具體實施例中系統時鐘線路丨8也連接到DSp 3 6 ;然 二’如果在卡上使用與中央處理器中所用的時序不同之時 斤’應該了解—分開的時鐘可提供給此DSP。然而,對大 事例的較佳具體實施例是使用系統時鐘以 憶體模組上的那些功能和㈣。 … =線5? ’ 5 8級成的一二線序列匯流排,提供來連接 器到二個接點26,此二接點26與系統記憶體控:; 記ίΖί說^插;的具體實施例,,記憶體是-附加 中,X你1a 本發明可結合在任何記憶體子系統 去4 ’匕疋否為一"可插接"附加記憶體。 Α二ί ^體t組未被中央處理器透過記憶體控制器28定址 取或寫入功能、或其他功能時,DSP的哞夕 置因:而當這些工作進行時,仙⑼和 組時,FETs是,^,如果,當中央處理器要存取記憶體模 s疋閉路的,而記憶體控制器2δ可定址記憶體資Page 8 480404 V. Description of the Invention (4) The bus 48 connects the bus controller 34 to the DSP 36. Memory data bus 1 4 has f E T (Field Effect Transistor) switch 5 0 on it. (It should be understood that the memory data bus 14 is composed of multiple lines, one line per bit, and one FET 5 per bit line.) The memory data bus 14 may be an 8-bit bus, a 6-bit bus' a 32-bit bus, or a 64-bit bus, and it does include any number of data A data bus of any size of the line is required ... In addition, a system address / control bus 16 includes a FET switch 52. In the specific embodiment of Xingfujia, the system clock line 8 is also connected to DSp 36. However, if the timing used on the card is different from the timing used in the CPU, it should be understood that a separate clock can be provided to This DSP. However, the preferred embodiment for the big case is to use the system clock to remember those functions and functions on the body module. … = Line 5? '5 8 level one or two-line serial bus, provided to the connector to two contacts 26, the two contacts 26 and the system memory control: For example, the memory is-attached, X you 1a The present invention can be combined in any memory subsystem to go to 4 'whether it is a " pluggable " additional memory. Α 二 ί When the group t has not been fetched or written by the CPU through the memory controller 28, or other functions, the DSP is set to cause: When these tasks are performed, FETs are, ^, if, when the central processing unit wants to access the memory module s 疋, the memory controller 2δ can address the memory resources.

第9頁 480404 五、發明說明(5) 料匯流1 4和記憶體位址/控制匯流排6 0上的記憶體模組8, 以對S D R A M s 1 2 a - 1 2 h往返執行傳統的讀取/寫入運作。 依照本發明,D S P 3 6執行幾種功能。這些功能中的一 種,是在記憶體匯流排控制器3 4的控制之下,從記憶體匯 流排控制器3 4接收系統來往寫入到D R A M s 1 2 a - 1 2 h、和從 其讀取之所有位址和相關的資料,不論那些位址是否是在 D S P範圍1 3 a - 1 3 h當中。一程式載入到D S P s快取記憶體3 8 中,其將對活動戳記時間和追蹤,舉例來說讀取和寫入的 數目和其中至少儲存了一些資料的位置。這個資訊由電腦 系統6藉由記憶體匯流排控制器3 4儲存和存取,且此資訊 利用作記憶體最佳化。這些運作可包括,舉例來說,但不 限制在,位址/資料的時域分析、和光譜分析(F F T或 D C T ),以決定記憶體中的熱門點。系統6可使用這個資料 將資料的分佈最佳化,和使執行效率最大化與將電力需求 減到最少。D S P 3 6的這個活動發生在系統,而非D S P,控 制記憶體的期間,因此增加D S P 3 6的利用。 D S P 3 6可執行的另一功能是對分配給D S P 3 6之記憶體晶 片12a -12h的區域13a - 13h中的那些位址(或如果需要,其 他所選擇的位址)之寫入π探測π系統匯流排。如果對這個 範圍中的一位址有一寫入,DSP 36可擷取位址和資料,並 執行任何必需的早期處理運作,即使D S Ρ 3 6不能夠存取記 憶體晶片1 2 a - 1 2 h。當收到來自電腦系統6的中央處理器之 資訊時,它儲存在快取記憶體38中,然後當預先處理的資 訊可用且儲存在快取記憶體3 8中時廢棄。然後當D S P 3 6取Page 9 480404 V. Description of the invention (5) The material bus 14 and the memory module 8 on the memory address / control bus 60, so as to perform the traditional reading of SDRAM s 1 2 a-1 2 h / Write operation. According to the invention, D S P 3 6 performs several functions. One of these functions is under the control of the memory bus controller 34, receiving system writes from the memory bus controller 34 to DRAM s 1 2 a-1 2 h, and reading from it All addresses and related information are taken, regardless of whether those addresses are in the DSP range 1 3 a-1 3 h. A program is loaded into the DSPS cache memory 38, which will stamp the time and track the activity, for example the number of reads and writes and the location where at least some data is stored. This information is stored and accessed by the computer system 6 through the memory bus controller 34, and this information is used for memory optimization. These operations may include, for example, but are not limited to, time domain analysis of addresses / data, and spectral analysis (F F T or D C T) to determine hot spots in memory. System 6 can use this data to optimize the distribution of the data, and to maximize execution efficiency and minimize power requirements. This activity of D S P 3 6 occurs in the system, rather than D S P, which controls the period of memory, thus increasing the use of D S P 3 6. Another function that DSP 3 6 can perform is to write π-probe to those addresses (or other selected addresses if needed) in areas 13a-13h of memory chips 12a-12h allocated to DSP 3 6 π system bus. If there is a write to an address in this range, the DSP 36 can retrieve the address and data and perform any necessary early processing operations, even if the DS P 36 cannot access the memory chip 1 2 a-1 2 h. When the information from the central processing unit of the computer system 6 is received, it is stored in the cache memory 38 and then discarded when the pre-processed information is available and stored in the cache memory 38. Then when D S P 3 6 take

O:\64\64666.ptd 第10頁 480404 五、發明說明(6) 得對DRAMs 12a-12h的存取時,它將會有預先處理的資訊 並能將此資訊以它處理過的形式寫入到所分配的位置 1 3 a - 1 3 h中的記憶體晶片位址。這些早期處理運作可包括 藉由執行一快速傅立葉轉換(Fourier Transforni)(FFT)決 定位址的頻率。也可執行資料壓縮,而且計算當成一類比 對數位轉換器的取樣器之有限脈衝回應(F I R)濾波器的輸 出,被寫入區域1 3 a - 1 3 h中的位址。 如果必要,舉例來說,如果匯流排控制器3 4以一比D S P 3 6快的速度運作,可提供匯流排控制器一緩衝區7 0給要寫 到DSP 36的資料。 圖2是描述用_以”探測π系統匯流排以使DSP 36執行早期 處理運作的程式之操作的流程圖。在主系統的初始化.之 後,如果探測程式還沒駐存,主處理器或中央處理器6載 入D S Ρ 3 6要執行的π探測π程式,進入快取或稿紙簿記憶體 3 8之内。(如果需要,探測程式可做成駐存在D S Ρ 3 6的快 取38中,以避免需要在中央處理器的初始化時載入此程 式。然而,讓此程式駐存在系統6中是較佳的,以便可使 用各種程式,而不只是那些永久地駐存到快取3 8之内 的。)電腦系統6的中央處理器使記憶體匯流排控制器探測 邏輯能夠探測D S Ρ 3 6中的邏輯,以”探測'’所選擇的位址範 圍,此範圍通常將在分配給D S Ρ 3 6的位址範圍當中,但也 可能包含在這個範圍之外的位址。然後電腦6啟動正常的 運作,以記憶體控制器如需要的存取DRAM記憶體 1 2 a - 1 2 h。在D S P 3 6中的π探測程式π監控記憶體匯流排控O: \ 64 \ 64666.ptd Page 10 480404 V. Description of the invention (6) When the DRAMs 12a-12h are accessed, it will have pre-processed information and can write this information in its processed form Enter the memory chip address in the allocated locations 1 3 a-1 3 h. These early processing operations may include determining the frequency of the address by performing a Fourier Transforni (FFT). Data compression can also be performed, and the output of a finite impulse response (F I R) filter used as a sampler of an analog to digital converter is calculated and written to the address in the area 1 3 a-1 3 h. If necessary, for example, if the bus controller 34 operates at a faster speed than D S P 36, a bus controller 70 may be provided with a buffer 70 for data to be written to the DSP 36. Figure 2 is a flow chart describing the operation of a program to detect the π system bus to enable the DSP 36 to perform early processing operations. After the main system is initialized. If the detection program has not yet been stored, the main processor or the central The processor 6 loads the π-detection program to be executed by the DS P 36, and enters the cache or manuscript memory 38. (If necessary, the detection program can be made to reside in the cache 38 of the DS P 36. To avoid the need to load this program during the initialization of the CPU. However, it is better to have this program reside in the system 6 so that various programs can be used, not just those that are permanently stored in the cache 3 8 Within.) The central processing unit of computer system 6 enables the memory bus controller detection logic to detect the logic in DS P 36 to "detect" the selected address range, which will usually be allocated to DS P 3 6 address range, but may also include addresses outside this range. Then the computer 6 starts normal operation and accesses the DRAM memory 1 2 a-12 h with the memory controller as needed. Π detection program in D S P 3 6 π monitor memory bus control

O:\64\64666.ptd 第11頁 480404 五、發明說明(7) 制器34。O: \ 64 \ 64666.ptd Page 11 480404 V. Description of Invention (7) Controller 34.

當發現在位址的π探測π邏輯或程式範圍當中之一位址 時,所發現的位址和相關的資料與存取的時間是缓衝健存 在緩衝區7 〇中(如有一個)’且一中斷從έ己憶體匯流排控φ|】 器在中斷匯流排4 6上送到D S P 3 6。(如果D S P 3 6的速度至 少是如記憶體匯流排控制器3 4的一樣快,那麼在記憶體匯 流排控制器3 4中可能不需要一緩衝區)。在如此的情況 中,位址,相關的資料和時間戳記直接地傳遞到D S P 3 6。 然後DSP 3 6存取在記憶體匯流排控制器3 4的緩衝區7 0中之 此位址和資料與時間戳記,並將此儲存在快取記憶體3 8 中0 然後DSP 36執行它所被規劃的無論何種處理演算法(舉 例來說F F T或F I T遽波器或資料壓縮)^處理的結果儲存在 快取記憶體38中,而不再需要的所接收資料被廢棄。 如果DSP 3+6未被核可對記憶體匯流排的存取,它繼續探 測記憶,匯流排控巧器在對它所規劃的範圍中之位址,且 接收和处理適當=貢料。當核可〇§{) 36 #DRAMs i2a_12h 的存取時,預先處理的結果從快取38寫入到DRAMs 12&-12^1中所指向的那些位^%#When it finds an address in the π probe π logic or program range of the address, the found address and related data and access time are stored in the buffer 7 (if any) ' And an interrupt is sent from the bus controller φ |] to the DSP 36 on the interrupt bus 4 6. (If D S P 36 is at least as fast as the memory bus controller 34, then a buffer may not be needed in the memory bus controller 34.) In such a case, the address, related data and time stamp are passed directly to DS 36. Then DSP 3 6 accesses this address and data and time stamp in buffer 7 0 of memory bus controller 3 4 and stores this in cache 3 0 0 and then DSP 36 executes its Regardless of the planned processing algorithm (for example, FFT or FIT waver or data compression), the processed results are stored in the cache memory 38, and the received data that is no longer needed is discarded. If the DSP 3 + 6 has not approved the access to the memory bus, it continues to detect the memory, the bus controller's address in the range it has planned, and the reception and processing are appropriate = data. When the access of § () 36 #DRAMs i2a_12h is approved, the pre-processed result is written from cache 38 to the bits pointed to in DRAMs 12 & -12 ^ 1 ^% #

f此’以此,,探測”功—能,DS°P 36可處理在任何預先規劃 的犯圍之位址中的責訊’即使 p 36未控制記憶體匯流 排0fThis ’, by this, the detection function—DS ° P 36 can handle the blame in any pre-planned crime address’ even though p 36 does not control the memory bus. 0

第12頁Page 12

Claims (1)

480404 六、申請專利範圍 1. 一種具有一中央處理單元的電腦系統之記憶體模組, 包含: 一印刷電路卡; 在該印刷電路卡上的記憶體晶片, 在該印刷電路卡上的一記憶體匯流排; 一記憶體匯流排控制元件,配置成與該記憶體晶片和 該記憶體匯流排通訊; 在該記憶體匯流排中的開關,以選擇地連接和分離該 記憶體匯流排和該中央處理單元; 一在該印刷電路卡上的信號處理元件,配置成經由該 記憶體匯流排控制元件與該記憶體匯流排控制元件和該等 記憶體晶片通訊, 在該記憶體匯流排控制元件中的程式規劃,以從中央 處理單元傳遞所選擇的位址和相關的資料到該信號處理元 件; 該信號處理元件規劃成對該所接收的資料操作;及 在該記憶體匯流排控制器中的該程式規劃,包括經由 該記憶體匯流排控制器選擇性地連接和分離該信號處理元 件與該等記憶體晶片的程式規劃。 2. 如申請專利範圍第1項之記憶體模組,其中該所選擇 的位址包括在該記憶卡上該記憶體晶片的所有位址。 3 ·如申請專利範圍第1項之記憶體模組,其中記憶體晶 片的區域保留給信號處理元件,而那些所選擇的位址包括 該保留的位址比記憶體晶片的所有位址少。480404 VI. Application Patent Scope 1. A memory module of a computer system with a central processing unit, comprising: a printed circuit card; a memory chip on the printed circuit card; a memory on the printed circuit card A memory bus control element configured to communicate with the memory chip and the memory bus; a switch in the memory bus to selectively connect and separate the memory bus and the memory bus A central processing unit; a signal processing element on the printed circuit card, configured to communicate with the memory bus control element and the memory chips via the memory bus control element, and to control the memory bus control element Programming in the system to pass the selected address and related data from the central processing unit to the signal processing element; the signal processing element is planned to operate on the received data; and in the memory bus controller The program planning includes selectively connecting and separating the signal processing element via the memory bus controller. And the programming of these memory chips. 2. For example, the memory module of the scope of patent application, wherein the selected address includes all the addresses of the memory chip on the memory card. 3. The memory module of item 1 of the patent application scope, in which the area of the memory chip is reserved for the signal processing element, and those selected addresses include the reserved address less than all the addresses of the memory chip. O:\64\64666.ptd 第13頁 480404 t、申請專利範圍 4. 如申請專利範圍第1項之記憶體模組,其中在該信號 處理元件中的該程式規劃,包括當該信號處理元件與該記 憶體晶片分離時,執行資料處理功能的程式規劃。 5. 如申請專利範圍第4項之記憶體模組,其中在該信號 處理元件中的該程式規劃,包括當信號處理元件有該記憶 體晶片的存取權力時,寫入其所處理的資料到該記憶體晶 片的程式規劃。 6 ·如申請專利範圍第1項之記憶體模組,其中該信號處 理元件包括用來儲存從該中央處理單元所接收的資料之快 取記憶體。 7. 如申請專利範圍第1項之記憶體模組,其t該記憶體 匯流排控制元件包括從中央處理單元寫入所選擇的程式到 該信號處理元件之程式規劃。 8. 如申請專利範圍第1項之記憶體模組,其中該信號處 理元件是一數位信號處理器。 9. 如申請專利範圍第2項之記憶體模組,其中在該信號 處理元件中的該程式規劃,包括執行光譜分析以決定該記 憶體中的熱門部位之程式規劃。 1 0.如申請專利範圍第3項之記憶體模組,其中在該信號 處理元件中的該程式規劃,包括執行從快速傅立葉轉換、 資料壓縮、和有限脈衝回應濾波器的群體中所選擇出的至 少一運作之程式規劃。 1 1. 一種含有一中央處理單元的電腦系統,包括一記憶 體子系統,該記憶體子系統包含:O: \ 64 \ 64666.ptd Page 13 480404 t. Patent application scope 4. For the memory module of the first patent application scope, the program planning in the signal processing element includes when the signal processing element When separated from the memory chip, the programming of the data processing function is performed. 5. For the memory module of the fourth scope of the patent application, the programming in the signal processing element includes writing the data processed by the signal processing element when the signal processing element has the access right of the memory chip. To the memory chip. 6. The memory module according to item 1 of the patent application scope, wherein the signal processing element includes a cache memory for storing data received from the central processing unit. 7. For the memory module in the first item of the patent application scope, the memory bus control element includes a program plan from the central processing unit to write the selected program to the signal processing element. 8. If the memory module of the first patent application scope, the signal processing element is a digital signal processor. 9. For example, the memory module of the scope of patent application, wherein the program planning in the signal processing element includes a program planning for performing a spectral analysis to determine a hot spot in the memory. 10. The memory module according to item 3 of the scope of patent application, wherein the program planning in the signal processing element includes executing a selection from a group of fast Fourier transform, data compression, and finite impulse response filters. Programming of at least one of the operations. 1 1. A computer system including a central processing unit, including a memory subsystem, the memory subsystem including: 第14頁 480404 六、申請專利範圍 記憶體晶片; 一記憶體匯流排; 一記憶體匯流排控制元件,配置成與該記憶體晶片和 該記憶體匯流排通訊; 在該記憶體匯流排中的開關,以選擇地連接和分離該 記憶體匯流排和該中央處理單元; 一信號處理元件,配置成經由該記憶體匯流排控制元 件與該記憶體匯流排控制元件及該等記憶體晶片通訊; 在該記憶體匯流排控制元件中的程式規劃,以從中央 處理單元傳遞所選擇的位址和相關的資料到該信號處理元 件; 該信號處理元件規劃成對該所接收的資料操作;及 在該記憶體匯流排控制器中的該程式規劃,包括經由 該記憶體匯流排控制器選擇性地連接和分離該信號處理元 件與該等記憶體晶片的程式規劃。 1 2 ·如申請專利範圍第1 1項之電腦系統,其中該所選擇 的位址包括在該記憶卡上該記憶體晶片的所有位址。 1 3 ·如申請專利範圍第1 1項之電腦系統,其中記憶體晶 片的區域保留給信號處理元件,而那些所選擇的位址包括 該保留的位址比記憶體晶片的所有位址少。 1 4.如申請專利範圍第1 1項之電腦系統,其中在該信號 處理元件中的該程式規劃,包括當該信號處理元件與該記 憶體晶片分離時,執行資料處理功能的程式規劃。 1 5.如申請專利範圍第1 4項之電腦系統,其中在該信號Page 14 480404 VI. Patented memory chip; a memory bus; a memory bus control element configured to communicate with the memory chip and the memory bus; the memory bus in the memory bus A switch to selectively connect and separate the memory bus and the central processing unit; a signal processing element configured to communicate with the memory bus control element and the memory chips via the memory bus control element; Programming in the memory bus control element to pass the selected address and related data from the central processing unit to the signal processing element; the signal processing element is planned to operate on the received data; and The program planning in the memory bus controller includes a program planning for selectively connecting and separating the signal processing element and the memory chips via the memory bus controller. 1 2 · The computer system according to item 11 of the patent application scope, wherein the selected address includes all addresses of the memory chip on the memory card. 1 3 · The computer system of item 11 in the scope of patent application, in which the area of the memory chip is reserved for the signal processing element, and those selected addresses including the reserved address are less than all the addresses of the memory chip. 14. The computer system according to item 11 of the scope of patent application, wherein the program planning in the signal processing element includes a program planning for performing a data processing function when the signal processing element is separated from the memory chip. 1 5. The computer system according to item 14 of the scope of patent application, wherein the signal 第15頁 480404 六、申請專利範圍 處理元件中的該程式規劃,包括當信號處理元件有該記憶 體晶片的存取權力時,寫入其所處理的資料到該記憶體晶 片的程式規劃。 1 6 ·如申請專利範圍第1 1項之電腦系統,其中該信號處 理元件包括用來儲存從該中央處理單元所接收的資料之快 取記憶體。 \ 1 7 ·如申請專利範圍第1 1項之電腦系統,其中該記憶體 匯流排控制元件包括從中央處理單元寫入所選擇的程式到 該信號處理元件之程式規劃。Page 15 480404 VI. Scope of patent application The program planning in the processing element includes the program planning of writing the data processed by the signal processing element into the memory chip when the signal processing element has the access right of the memory chip. 16 · The computer system according to item 11 of the patent application scope, wherein the signal processing element includes a cache memory for storing data received from the central processing unit. \ 1 7 · If the computer system of item 11 of the scope of patent application, the memory bus control element includes the program planning from the central processing unit to write the selected program to the signal processing element. 1 8 ·如申請專利範圍第1 1項之電腦系統,其中該信號處 理元件是一數位信號處理器。 1 9 ·如申請專利範圍第1 2項之電腦系統,其中在該信號 處理元件中的該程式規劃,包括執行光譜分析以決定該記 憶體中的熱門部位之程式規劃。 2 〇.如申請專利範圍第1 3項之電腦系統,其中在該信號 處理元件中的該程式規劃,包括執行從快速傅立葉轉換、 資料壓縮、和有限脈衝回應濾波器的群體中所選擇出的至 少一運作之程式規劃。1 8 · The computer system according to item 11 of the patent application scope, wherein the signal processing element is a digital signal processor. 19 · The computer system according to item 12 of the scope of patent application, wherein the program planning in the signal processing element includes program planning for performing a spectral analysis to determine the hot spots in the memory. 2 〇 The computer system according to item 13 of the patent application scope, wherein the program planning in the signal processing element includes executing a selection from a group of fast Fourier transform, data compression, and finite impulse response filters Programming of at least one operation. 2 1. —種操作連接到電腦系統的一中央處理單元之一記 憶體子系統的方法,且其t該記憶體子系統具有可選擇性 地連接到中央處理單元且由一記憶體匯流排控制元件控制 的一記憶體匯流排和一連接至記憶體匯流排控制元件之信 號處理元件,包含下列之步驟: 從中央處理單元傳遞所選擇的位址和相關的資料到該2 1. —A method for operating a memory subsystem of a central processing unit connected to a computer system, and the memory subsystem has a selectively connectable to the central processing unit and is controlled by a memory bus A memory bus controlled by the component and a signal processing component connected to the memory bus control component include the following steps: passing the selected address and related data from the central processing unit to the 第16頁 480404 六、申請專利範圍 信號處理元件; 在該信號處理元件中執行來自該中央處理單元所傳遞 的該資料之操作;及 經由該記憶體匯流排控制元件,選擇性地連接該信號 處理元件至該等記憶體晶片或該中央處理單元。 2 2 ·如申請專利範圍第2 1項冬方法,其中該所選擇的位 址包括在該記憶卡上該記憶體晶片的所有位址。 2 3 ·如申請專利範圍第2 1項之方法,其中記憶體晶片的 區域保留給信號處理元件,而那些所選擇名位址包括該保 留的位址比記憶體晶片的所有位址少。 2 4.如申請專利範圍第21項之方法,其中當該信號處理 元件與該記憶體晶片分離時,該信號處理元件執行資料處 理功能。 2 5.如申請專利範圍第24項之方法,其中當信號處理元 件有該記憶體晶片的存取權力時,該處理元件寫入其所處 理的資料到該記憶體晶片。 2 6.如申請專利範圍第2 1項之方法,其中該信號處理元 件包括用來儲存從該中央處理單元所接收的資料之快取記 憶體。 2 7.如申請專利範圍第2 1項之方法,其中該記憶體匯流 排控制元件包括從中央處理單元寫入所選擇的程式到該信 號處理元件之程式規劃。 2 8.如申請專利範圍第2 1項之方法,其中該信號處理元 件是一數位信號處理器。Page 16 480404 VI. Patent application range signal processing element; performing the operation of the data transmitted from the central processing unit in the signal processing element; and selectively connecting the signal processing through the memory bus control element Components to the memory chips or the central processing unit. 2 2 · According to the 21st winter method in the scope of patent application, wherein the selected address includes all addresses of the memory chip on the memory card. 2 3 · The method according to item 21 of the patent application, wherein the area of the memory chip is reserved for the signal processing component, and those selected addresses include the reserved address less than all the addresses of the memory chip. 2 4. The method according to item 21 of the patent application scope, wherein when the signal processing element is separated from the memory chip, the signal processing element performs a data processing function. 25. The method of claim 24, wherein when the signal processing element has access to the memory chip, the processing element writes the data it processes to the memory chip. 26. The method of claim 21, wherein the signal processing element includes a cache memory for storing data received from the central processing unit. 2 7. The method according to item 21 of the patent application scope, wherein the memory bus control element includes a program plan from the central processing unit to write the selected program to the signal processing element. 2 8. The method according to item 21 of the patent application scope, wherein the signal processing element is a digital signal processor. 第17頁 480404 六、申請專利範圍 2 9.如申請專利範圍第2 2項之方法,其中該信號處理元 件執行光譜分析以決定該記憶體中的熱門部位。 3 〇 ·如申請專利範圍第2 1項之方法,其中該信號處理元 件執行從快速傅立葉轉換、資料壓縮、和有限脈衝回應濾 波器的群體中所選擇出的至少一運作。 3 1 ·如申請專利範圍第1項之記憶體模組,進一步特徵在 於該記憶體匯流排控制器中的一缓衝區,供在該信號處理 元件擷取之前,暫時儲存資料、位址、和時間資訊。 3 2 ·如申請專利範圍第1 1項之電腦系統,進一步特徵在 於該記憶體匯流排控制器中的一緩衝區,供在該信號處理 元件擷取之前,暫時儲存資料、位址、和時間資訊。 3 3 ·如申請專利範圍第2 1項之方法,進一步特徵在於該 記憶體匯流排控制器中的一緩衝區,供在該信號處理元件 操取之前’暫時儲存貧料、位址、和時間資訊。Page 17 480404 VI. Patent Application Range 2 9. The method according to item 22 of the patent application range, wherein the signal processing element performs a spectral analysis to determine the hot spots in the memory. 30. The method of claim 21, wherein the signal processing element performs at least one operation selected from the group of fast Fourier transform, data compression, and finite impulse response filters. 3 1 · If the memory module of the first patent application scope is further characterized by a buffer in the memory bus controller for temporarily storing data, address, And time information. 3 2 · The computer system according to item 11 of the patent application scope is further characterized by a buffer in the memory bus controller for temporarily storing data, address, and time before the signal processing component is retrieved. Information. 3 3 · The method according to item 21 of the scope of patent application, further characterized by a buffer in the memory bus controller, for 'temporarily storing lean materials, addresses, and time before the signal processing element operates. Information. 第18頁Page 18
TW089115139A 1999-08-31 2000-07-28 Memory card with signal processing element TW480404B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/386,543 US6446163B1 (en) 1999-01-04 1999-08-31 Memory card with signal processing element

Publications (1)

Publication Number Publication Date
TW480404B true TW480404B (en) 2002-03-21

Family

ID=23526038

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089115139A TW480404B (en) 1999-08-31 2000-07-28 Memory card with signal processing element

Country Status (2)

Country Link
KR (1) KR100368085B1 (en)
TW (1) TW480404B (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5193170A (en) * 1990-10-26 1993-03-09 International Business Machines Corporation Methods and apparatus for maintaining cache integrity whenever a cpu write to rom operation is performed with rom mapped to ram
TW386192B (en) * 1997-04-14 2000-04-01 Ibm Method and system for speculatively sourcing cache memory data within a data-processing system

Also Published As

Publication number Publication date
KR20010050094A (en) 2001-06-15
KR100368085B1 (en) 2003-01-15

Similar Documents

Publication Publication Date Title
CA2245106A1 (en) Method and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus access
US5913044A (en) Method and system for simultaneous variable-width bus access in a multiprocessor system
CN108139994B (en) Memory access method and memory controller
KR20050005553A (en) Memory hub with internal cache and/or memory access prediction
US7082491B2 (en) Memory device having different burst order addressing for read and write operations
US7814257B2 (en) Data transfer apparatus and data transfer method
JP2005501300A (en) Array and method for accessing data in a virtual memory array
JP2001043180A (en) Microprocessor and storage device therefor
US6446169B1 (en) SRAM with tag and data arrays for private external microprocessor bus
US6446163B1 (en) Memory card with signal processing element
US20010016922A1 (en) Emulator and method of emulation for testing a system
TW480404B (en) Memory card with signal processing element
US7451248B2 (en) Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations
EP0969513A2 (en) Embedded enhanced DRAM with integrated logic circuit, and associated method
EP0803820A2 (en) An integrated digital processing device and method for examining the operation thereof
US5809534A (en) Performing a write cycle to memory in a multi-processor system
US7200706B2 (en) Semiconductor integrated circuit
KR920010446A (en) Method and apparatus for fast page mode selection
JP3419392B2 (en) Memory access monitoring device, memory access monitoring method, and recording medium recording memory access monitoring program
TW200535623A (en) Expansible time-division bus structure of enhanced type
JPH01251250A (en) Shared cache memory
US6141735A (en) Performing a memory access cycle in a multi-processor computer system
JPH06274415A (en) Shared memory system
KR100268178B1 (en) A caching unit on the pci bus
JPS58213371A (en) Data processing system

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees