TWI283553B - Thermal enhanced low profile package structure and method for fabricating the same - Google Patents

Thermal enhanced low profile package structure and method for fabricating the same Download PDF

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Publication number
TWI283553B
TWI283553B TW094112784A TW94112784A TWI283553B TW I283553 B TWI283553 B TW I283553B TW 094112784 A TW094112784 A TW 094112784A TW 94112784 A TW94112784 A TW 94112784A TW I283553 B TWI283553 B TW I283553B
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Taiwan
Prior art keywords
electronic
dielectric material
material layer
electronic component
layer
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TW094112784A
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English (en)
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TW200638814A (en
Inventor
En-Boa Wu
Shou-Lung Chen
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Ind Tech Res Inst
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Priority to TW094112784A priority Critical patent/TWI283553B/zh
Priority to US11/301,903 priority patent/US7511365B2/en
Publication of TW200638814A publication Critical patent/TW200638814A/zh
Application granted granted Critical
Publication of TWI283553B publication Critical patent/TWI283553B/zh
Priority to US12/388,191 priority patent/US7754530B2/en

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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

1283553 九、發明說明： 【發明所屬之技術領域】 本發明侧於_種_化電子縣，制是_—種 熱增益效果之薄型化電子構裝結構及其形成方法。 【先前技術】 電子構裝驗之改良·電子產t肋發脑言是相當重 要的；隨著電子元件產品的小型似及輕薄化等需求 裝技術亦必須不斷地轉崎’哺合電子元件產品的， =進-步發揮其電力傳送、訊號傳送、散熱以及保護^等 電子元件產品的小型化需求亦代表著必須提高電子 的内連接(interconnect)電路之密度，以於一較小的 ^達到同料訊號處理量。目前6有許多文獻相 ^ 方法，舉例而吕，在美國專利第6,242,282號中 種高密度晶片齡結構_成方法；請參閱第卩 法所形成的構裝結構之側視圖 方 佈線124之内連接層12，並將該電路晶 12上之該通道122，接著利用一祕尽^玄内連接層 18於該電路晶片1G上，而形成—完整日J-構襄材料 在美國專利第5,567,657^^^4=1 k出一種具有可撓性内連接層之雙側 亦刀別 i其=兩;== =在嶋㈣峨===== 此外，本案申請人亦於中華民國93年11月19日提出「薄 5 1283553 =化電子構裝結構及其製作方法」之台灣專 93135698號申請案），其係利用一有機基板製 對>1合的方式，而於整體基板形成時即同時完成電子二= 線與構裝，簡化了習知構裝技術中如打線接合 以及覆晶接合技術之相關製程；藉其所形成之i子 減了構裝結構之整體體積，並使得職在傳遞^ = =轉換而產纖強度逸失之現象，因此能夠 然而，上述之各種高密度與薄型化構裝的相關技術僅 了關=構裝結射錢密度無積之絲；崎著電子元 電流密度的提昇以及元件贿的減少，更需要重視 結構内部散制題，才能避免訊號在電路晶片與構^構之間 ，遞時因所產生的熱量無法散失而影響了該電子元件“體二 能。 本案發明動機即由此而產生；申請人鑑於時 需，乃經悉心試驗與研究，並一本鎮而不捨之精線二 出本案「熱增益型薄型化電谓裝」。本發明係 前案-_化電子構裝賴及其製作方法_為基礎= -步發展之新穎技術，所職之電子構裝 發明所提供之f子構裝結構所具有的餘效果_優於上 知技術所軸者，13而麟進—步提昇該電子 構 關之電子藉雜能。 【發明内容】
本發明之第-_姐提供―種電子猶結構 裝結構包含-第-介電材冊，其具有—第— I 表面;-第二介電材料層，其具有一第二上表面與:g下: 1283553 面卜金屬層，其係部分位於該第一下表面與 間，至少-電子元件，係位於該第一下表面與該金屬層^之 ΐϊίΠ一介電材料層與該第二介電材料層進行▲合而固 i as)，其係貫穿該第—介電材料層而連接 至該電子兀件，以及一佈線層，其係位於部分之該 上，其中該第二介電材料層上更具有複數之凹槽，且^ 之位置係對應至該等電子元件之位置。 寻糟 之f二構想在於提供""種電子構裝結構，該電子構 ^構包3-第-介電材料層，其具有—第—上表面與第一下 表面，-第二介電材料層，其具有一第二上表面與一第二下表 面；一導線架(leadframe-likecarrier)，其係位於該^一下^面: 該第二上表面之間，其中該導線架上具有複 ； (channel)，而該等溝槽係將該導線架分隔為複數之導線載體； 至^-電子元件’係位於該第—下表面與該導線架之間，其位 ，係對應㈣等倾之位置，且藉崎該第—介電材料層^該 ^介電材料層進行壓合而固定於其中；複數通道(Vias)， 貫穿該第-介電材料層而連接至該電子元件；以及一佈厂 其係位於部分之該第一上表面上。 、曰 根據上述構想，其中該金屬層更包含一導線架 (leadframe-likecarrier) ’該導線架上具有複數之溝槽(ch_卜、 藉此而將該導線架分隔為複數之導線載體。 歸Ϊϋΐί，其中該第—介f材料層與該第二介電材料 層係由一介電材料所構成。 根據上述構想，其中該第一介電材料層係包含一 ^C^?\C〇ated C〇Pper-foi1)^^' - ABF(Ajinomoto Build-up Film)基板與一可撓式基板其中之一。 介電想’其中該第二介電材料層之麵與該第-根據上述構想，其中該電子元件係為-主動式電子元件與 7 1283553 一被動式電子元件其中之一。 其中構丨〖彳:該奸難結構包含減之該€子元件， ί 1=11係選自於主動式電子元件、被動式電子元件 電阻中ΐ，離式被動元件係Μ ，其中，在該佈線層上更包含複數錫球_)。 該導線架之該導i載::該電子元件更藉由-金屬線而固設於 子元===槽K該導線紐上更具有-凹槽，而該電 發構想挪提供—種電子構財法，其包含的 ⑼於 70件上，以覆蓋該第一介電材料層與 一 明治結構?壓她_構，‘==固 ?亥，道；以及形成佈線圖形_eming)於該三明治結構 上，以進而於該三明治結構上進行佈線。 根據上述構想’其巾該方法更包含—步驟：分別形成複數 8 !283553 之凹槽於該等導線載體上。 、根據上述構想，其中該方法係利用一衝壓方式^pUnching) 或钱刻方式(etching)而將該等凹槽形成於該等導線載體上。 根據上述構想，其中該電子元件係位於該等凹槽中。 根據上述構想，其中該方法係利用一增層(Build_up)製程而 將該第二介電材料層形成於該電子元件上。 根據上述構想，其中該方法係利用一紫外線(uv)雷射製 程、二氧化碳(C〇2)氣體雷射製程與一化學蝕刻製程i中之一而 形成該等通道。 〃
根據上述構想，其中該方法更包含一步驟：對該三明治結 構進行一綠漆(Solder Mask)覆蓋處理。 根據上述構想，其中該方法更包含一步驟：對該三明治結 構進行一植球製程(Ball Mounting)。 根據上述構想，其中該方法更包含一步驟：切割該三明治 結構，而形成所需要之一電子構裝元件。 /〇 、根據上述構想，其中該方法係以一導電性材料填充該等通 道0 根據上述構想，其巾該第_介電材料層與該第二介電 層係包含_ RCC基板、-避基板與一可撓式基中之一。 本案得藉由下列圖示及詳細說明，俾得一更深入之了解： 【實施方式】 請參閱第二圖⑻至⑻，其說明了本發明之熱增益型薄型化 電子構裝之製作方法。首先將魏行齡之電？元件2 提供之一導線架(leadframe-like carrier)22上，盆中令雷；二放 20係一晶片（die);如第二圖⑻之俯視圖所示/在^線70 亡係具有複數之溝槽221，該等溝槽221係將該導線架、22分 =复，之導線賴22〇，子元件2〇即置於該等導線載體 9 1283553 26於十供第一介電材料層24與一第二介電材料層 與該該導線架22之外侧’藉此該電子元件2〇 層26 #而2 ί該第一介電材料層24與該第二介電材料 材料所ίΪ科3與該第二介電材料層26係由基板用之介電 向所示)秦成’並接著對該三明治結構2進行壓合(如圖中箭頭方 之該Ϊ第著移除經壓合之三明治結構2中部分 凹样而使該介電材料層26上具有複數之 “元0係得以暴露於該等凹槽261，以 成複壓、合之二明治結構中該第—介電材料層24上形 ，一般而言’無論是紫外線_雷射、C〇2 i綠學侧对，均可肋舰料道形成；
Pi;chi:、”、rf 一ί，利用UV雷射能夠形成更精細之間距(fme ’因而在此例中在不傷害下方結構之前提下，以uv 該ί通道為較佳選擇。該等通道係貫穿該三明治結 €材料層24而連接至該電子元件2G，並以- (d)所^料填充該等通道’而形成複數之傳導通道28，如第二圖 j替導通道28形成之後，對已形成有傳導通道^之 丨電材料層24表面進行佈線®^^Patteming)，而形成 -佈線層21，以利於進—步在該三明治結構2上== (wiring)並形成線跡(trace)，如第二圖⑹所示。 、' =至此，以本發明方法所形成之電子構裝結構已初步形 健上舰子黯結渐具有之内部賴、以及避免 =子構裝結構在後續製程中受職程條件(如高溫)之影響， ”方法亦可配合-習知之綠漆(solder Mask)覆蓋處士程 序、係分別於該第-介電材料層24與該第二介電材料層％ 1283553 =覆蓋-_層23、25 ’以提供該電子構裝結構一完整之保 遷，如第二圖(f)所示。 • 而為維持所形成的該電子構裝結構之線距(pitch)，在本發 姐^方法中，同樣包含了一植球製程(baUm〇Unting)，以將複數 上球27形成於該電子構裝結構中已預先配置好之錫球位置 ，如第二圖(g)所示；接著，依需要而以切割裝置1對已完成 . ^裳之上述該電子構裝結構進行切割程序 (isolatmg/singulating) ’以形成所需之單一電子構裝結構2〇〇， - 如第二圖(h)所示。 在本發明之方法中，該電子元件2〇係以置放方式形成於該 導線載體220上，而無須進行與該導線載體22〇間之接合 (ponding)程序；然於一較佳實施例中，為了避免該電子元件2〇 党到周圍環境擾動而移位，亦可進一步配合其他接合方式而對 該導線載體220與置放於其上之該電子元件2〇進行接合，例如 以打線接合方式(Wire Bonding)而將該電子元件20以金屬線連 接至该導線載體220上，並進而將引線延續至整體電子構裝結 構外部，以利於與其他電子元件間之連接。 此外，本發明之構裝方式亦適用於多種基板用之介電材 料’例如·背膠銅箔(RCC，Resin Coated Copper_foil)基板、 • ABF(Ajinomoto Build-up Film)基板、以及含有如聚醯乙胺 (?〇以《^(16，？1)、聚二甲基石夕烧(?0以出111她71811〇又31^，？〇]^18)、液 • 晶聚合物(Licluid Crystal Polymer，LCP)或聚對·酜酸乙二酯 (Polyethylene Terephthalate)等有機材料之可撓性基板，以形成 • 一軟性電子元件，將更拓展其應用層面。 請參閱第三圖，其係為根據本發明之第一較佳實施例之電 子構裝結構的剖面圖。該電子構裝結構3〇〇主要係用以構裝一 電子元件30，該電子元件30係預先設置於一導線架32上；該 導線架32係由複數之溝槽321與其所分隔而成之複數導線載體 320所形成，且該電子元件3〇係位於該等導線載體32〇上。該 11 1283553 電子構裝結構3GG係藉由對—介電材料層3植該 行壓合，而將該電子元件30固定於其中使電子構^ ，300能夠連接於-外部電路或電子裝置(圖^ ίϋΐ傳導通道38，該等傳導通道38係貫穿該介電材料^ 34而連接至位於該電子構裝結構·内部之該電子元件3〇，丄 亥等傳導通道38與該介電材料層34之外侧表面上且有佈 :31與複數錫球37,以利f路之連接與該等傳導通道38間^ ;此外’在料料収％與齡騎· 34之部 二外侧表面上亦覆有-阻銲層33 ’以保護該電子構裝 ^ ===線路’使其免贼料界械、科物或後續高 娃壯ΐ參閱細® ’係為根據本發日月之第二較佳㈣例之電子 ί装二f的剖面圖；其與第—實施例(如第三圖所示)不同的 件3G與該導線架32係藉由對-第-介電材料層 4 一一第二介電材料層36之壓合而固定於 34與該第二介電材料層36之間。此外，該第f介電^ ίΐίίί除而更具有複數之凹槽361，該導線載體32(^藉 :而=於，請，以利元件散熱之用，達成熱增益= 田=為避免外界水氣或污染物對該電子構震結構細中 之—侧產生不良影響，因而於該側上亦同 構裝本發明之第三較佳實施例之電子 ,前__ 第41= 分520係突出於該第f介電材料層36與該阻銲層 量直接‘4?二『二子广件3〇在運作時所產生的熱 12 1283553 請參閱第六圖⑻_(c) ’係為根據本發明之第四較佳實施例 之剖面圖;在該電子構二 兀件60係預先設置於一金屬層62上 屬層62間之壓合溶接，該電子 、糸因而固疋於八中。魏子構裝結構_更具 通道68a係連接至該電子元件60，而 同樣的， 外，傳f 6861與該等錫球67，以利電路之連接。此 1 68b與該介電材料層64之部分外側 元株盥二ί有T,知層6产’以保護該電子構裝結構600内部之 之干f。’使〃免於謂外界械、污染物或後續高溫處理 67峨職谓結構 ί=Λ二，一系統或準系統用之基板⑽上咖 直以以、 砝μ a 金屬仵呵度熱傳導性，因而可將該電子構裝 發明各項實施例僅為舉例說明本發明之用，然本 與結構’而提供較習知者更佳的構裝結構尺I 此外’清參閱第七圖與第七圖⑻至(c)，在本發明中，為避 1283553 免將電子元件70放置在金屬層或是導線架之導線載體72時， 會受外界干擾而偏離其位置，可利用衝壓(pUnching)或是钱刻處 理(etching/half etching)等方式於該金屬層或該導線載體72上先 形成對應之凹槽725，而將該電子元件70放置於該凹槽725 中；這樣的設計不但可以避免電子元件70受干擾而移位7亦可 減少所形成之電子構裝結構的整體高度，進而縮減其整體體積 並提昇其性能。
更甚者，如第七圖(c)所示，可利用打線接合的方式而直接 以金屬線724連接該電子元件70與該導線載體72，除了提高 該電子元件70的固定程度之外，亦可直接延伸該金屬線 至该電子構裝結構700整體之外部而成為一輸入/輸出導線 (Lead 1/0)726，以利於與其他電子元件間之連接。 在本發明中，所使用的構裝材料係一介電材料所形成之介 電材料層，其係藉由壓合方式而將欲構裝之電子元件構裝於其 中，以發揮其電力傳送、訊號傳送、散熱以及保護電路等^能 而除了上述之介電材料層之外，亦可使用背膠銅箔(RCC，Resin
Coated Copper-foil)基板、ABF(Ajinomoto Build_up Film)基板， 以及其他含有如聚醯乙胺(Polyjnide，PI)、聚二甲基梦烧 (Polydimethylsiloxane，PDMS)、液晶聚合物(Liquid trysw Polymer，LCP)或聚對-酞酸乙二酯(p〇iyethyiene Terephthalate)等 有機材料之可撓性基板。 此外，適用於本發明之電子元件種類亦相當廣泛，除了常 見之晶片（die)外，習用之其他電子元件如主動式電子元件與被 動式電子元件等，亦可單獨或共同組合而構裝於本發明之電子 構裝結構6中。舉例而言，常用的主動式元件更包含了半導體 (Semiconductor)、電晶體(Transistor)與積體電路(IC)等；而被動 式電子元件則包括如：電容器、電阻器與電感等分離式(Discrete) 被動元件，以及由電容材料、電感材料或是電阻材料所形成之 内埋式(Build-in)被動元件等。 1283553 相較於目前業界中所重視之球柵陣列（BGA，Ball Grid Array)構裝技術而言，在利用本發明所形成的電子構裝結構 中，因不需核心層(corelayer)，且其所需要的構裝尺寸(PKGsize) 較小，因而本發明之電子構裝結構可具有較小的體積；此外， 更由於本發明係關於電子元件與兩介電材料層間之直接壓合， 因此所形成的電子構裝結構具有較小的輸入/輸出距離長度，可 呈現較佳的性能與應用性。 另一方面，本發明係搭配了金屬層與導線架的設計而形成 一熱增益型電子構裝結構，由於金屬層與導線架的優良熱傳導 性巧，因而本發明所構裝之電子元件在執行操作時產生的熱量 可藉由該金屬層與導線架而直接導出該電子構裝結構，以達到 ，越的散熱效果；且本發明之電子構裝結構係以一簡單易於施 行的方式形成，適合於目前常用的多種基板用之介電材料，具 ^產業上之可利用性。因此本發明實為一新穎、進步且具產業 實用性之發明，深具發展價值。 本，發明得由熟悉技藝之人任施匠思而為諸般修飾，然不脫 如附申請範圍所欲保護者。 【圖式簡單說明】 Ϊ - 係為利用習知技術所形成之一構裝結構剖面圖； 的吾係為根據本發明之第一較佳實施例之電子構裝結構 的咅f面四圖圖;’係為根據本發明之第二較佳實施例之電子構裝結構 的^面^’4根據本發明之第三較佳實補之€子構裝結構 ()(e) ’係為根據本發明之第四較佳實施例之電子構 15 1283553 裝結構的剖面圖；以及 第七圖與第七圖(a)至(c)，係說明本發明之電子構裝結構中 之金屬層與導線架之剖面圖。
【主要元件符號說明】 1 構裝結構 10 電路晶片 12 内連接層 14 晶片概塾 16 黏接層 18 構裝材料 122 通道 124 金屬佈線 20 電子元件 22 導線架 220 導線載體 221 溝槽 24 第一介電材料層 26 第二介電材料層 261 凹槽 28 傳導通道 21 佈線層 23 阻焊層 25 阻鲜層 27 錫球 200 電子構裝結構 30 電子元件 31 佈線層 32 導線架 320 導線載體 321 溝槽 33 阻焊層 34 介電材料層 35 阻焊層 36 介電材料層 37 錫球 38 傳導通道 300 電子構裝結構 52 金屬層 520 增厚部分 60 電子元件 61 佈線層 62 金屬層 63 阻銲層 64 介電材料層 650 基板 67 錫球 68a 傳導通道 68b 傳導通道 600 電子構裝結構 700 電子構裝結構 70 電子元件 1283553 72 導線載體 724 725 凹槽 726 金屬線 導線
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Claims (1)

1283553 十、申請專利範圍： 1· 一種電子構裝結構，包含·· 1-介電材料層，其具有—第— 面；-红介電材料層，其具有_第二上表面與第_第下二表下面表 之^金屬層，其係部分位於該第一下表面與該第二上表面 電^第—介電材料層而連接至該 2線ί，其係位於部分之該第—上表面上， 娣==電材料層上更具有複數之凹槽，且兮等凹 槽之位置係對應至該等電子元件之位置。w僧且射凹 2Hf利範ιΐ第1項之結構，其中該金屬層更包含-導線 木（leadframe-like carrier)，該導線牟 、、策 (ch麵1)，藉此_緣線架分隔^之導之溝槽 3·如申請專利範圍第2項之結構，其體' 應於該等載體之位置。 μ電子疋件之位置係對 4. ^申請專利範圍第2項之結構，其中該電子 屬線而固設於該導線架之該導線载體上 ^ “ 5. 如申請專利翻第2項之結構，其中卿 凹槽’而該電子元件係位於該凹槽中。等深載體上更具有一 6·如申請專利範圍第1項之結構，其中 RCC(Resin Coated CoPPer-foil)^ f Build-up Film)基板與一可撓式基板复中之一 Jmomo 〇 1283553 8· 專f侧第1項之結構，射該電子元件係為一主動 式電子70件與一被動式電子元件1中之一。 9. 圍第1項之結構，’包含魏之該電子元件，其 1ί 自於主動式電子元件、被動式電子元件 m專，，8項之結構’其巾該絲式電子元件係 範圍第8項之結構，其中該被動式d元件更包 3刀離式被動元件與一内埋式被動元件1中之一。 Γ二專利範圍第11項之結構，其中該分離式被動元件係 為一電谷為、一電阻器與一電感其中之一。 圍第11項之結構，其巾軸埋錄動元件係 為一電谷材料、一電感材料與一電阻材料1中之一。 1似㈣+，錢'麵上更包含 B· —種電子構裝結構，包含： 一介電材料層； 鲁 一導線架(leadframe-like carrier)，其且有藉動之、、盖燐 (^rnnel) ’而該等溝槽係將該導線架分隔為複數之導線^ 門，^r署’係位於該介電材料層與該導線架之 :料=== 而載二且胸 複數通道(Vias)’其係貫穿該介電材料層而連接至該電子 凡1干，以及 上 16. _ -佈線層，其係位於部分之該介電材料層之—外侧表面 種電子構裝方法，其包含的步驟為： (a)提供一第一介電材料層； 1283553 (b) 提供一導線架(Leadframe-like Carrier)於該第一介電材 料層上，其中該導線架上具有複數之溝槽，而該 槽係將該導線架分隔為複數之導線載體； (c) 提供一電子元件於該等導線載體上； (Φ提供-第二介電材料層於該電子元件上，以覆蓋 一介電材料層與該電子元件，_成一三明治結構； (e)壓合該三明治結構，以使該電子元件固定於其中） (0形成複數通道(Vias)於該壓合之三明治結構上^亥等通 道，貫穿該三_結構中之該第二介電材料層而連接 至該電子元件； (g)填充該等通道；以及 ¢)形成佈線圖形(patterning)於該三明治結構上，以進而 於該三明治結構上進行佈線。 專利範圍第16項之方法，其於步卿)中，更包含一 分別形成複數之凹槽於該等導線載體上。 3範圍第17項之方法，其於步驟(bl)中，係利用- 輪絲麵帽等凹槽形 利範圍第18項之方法，其中該電子元件係位於該 專^範圍第16項之方法，其於步师)中，係利用一 ϋ(。uid-up)製程而將該第二介電材料層形成於該電子元 21 ΐΠίιΐΐ圍第16項之方法，其於步驟附，係利用一 射製程、二氧化碳(cc>2)㈣雷㈣程與一化 .ic範圍第16項之方法’其於步_後，更包含-"、Μ二明治結構進行一綠漆(SolderMask)覆蓋處理。 23·如申凊專利範固第16 步驟··對該三明、么钍、方法，其於步驟(h)後，更包含一 24·如申請專利範固g、f6行一植球製程(Ball Mounting)。 步驟：切割該三明、之方法，其於步驟00後，更包含一 25·如申請專利範圍第而形成所需要之-電子構裝元件。 電性材料填充該等通之方法，其於步驟(g)中，係以一導 二1 之方法，其中該第-介電材料層與 撓式基板其中之2包含—腦基板、—_基板與一可
21
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