TWI331386B - Substrate process for embedded component - Google Patents

Substrate process for embedded component Download PDF

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Publication number
TWI331386B
TWI331386B TW096108330A TW96108330A TWI331386B TW I331386 B TWI331386 B TW I331386B TW 096108330 A TW096108330 A TW 096108330A TW 96108330 A TW96108330 A TW 96108330A TW I331386 B TWI331386 B TW I331386B
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Taiwan
Prior art keywords
dielectric layer
embedded component
electronic component
substrate
contacts
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TW096108330A
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English (en)
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TW200837909A (en
Inventor
Chueh An Hsieh
Li Cheng Tai
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Advanced Semiconductor Eng
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Priority to TW096108330A priority Critical patent/TWI331386B/zh
Priority to US11/972,633 priority patent/US7727818B2/en
Publication of TW200837909A publication Critical patent/TW200837909A/zh
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Publication of TWI331386B publication Critical patent/TWI331386B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73267—Layer and HDI connectors
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    • H01L2224/82047—Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
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    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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    • H05K2201/0108—Transparent
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
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    • H05K2203/01—Tools for processing; Objects used during processing
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    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
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    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0067—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto an inorganic, non-metallic substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

1331386 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種基板製程，特別係有關於一種内 埋電子元件之基板製程。 【先前技術】 如第1圖所示’習知内埋元件之基板製程之流程圖依 序包含有「提供一載台」步驟丨、「設置至少—電子元件於 該載台」步驟2、「形成一第一介電層於該載台」步驟3、 「没置一載板於該第一介電層」步驟4、「移除該載台」步 驟5、「翻轉該載板」步驟6、「清除殘留之黏膠」步驟7、 形成一第二介電層於該第一介電層」步驟8、「以微影蚀 刻法形成複數個開口」步驟9、「形成一重分配線路層於該 第二介電層」步驟1〇。首先，請參閱第1及2A圖，在步 驟1中’係提供一載台1丨〇，該載台110之一表面1^係 塗覆有一黏膠層112,接著，請參閱第1及2B圖，在步驟 2中’設置複數個電子元件21〇於該載台11〇，每—電子 70件210係具有一主動面211、一背面212及複數個接點 213’該主動面211係朝向該載台11〇之該表面m，該些 接點213係形成於該主動面211上，之後，請參閱第 2c圖，在步驟3中，形成一第一介電層22〇於該載台 該第一介電層220係覆蓋該些電子元件210，利用一整平 步驟使該第一介電層22〇顯露出該些電子元件21〇之該些 背面212 ’接著，請參閱第1及2D圖，在步驟4中，設 置一載板230於該第—介電層220，該載板230係以一膠 6 1331386 本發明之主要目的係在於提供一種内埋元件之基板 氣心，首先，提供一模具，該模具之一表面係形成有複數 個犬起部，接著，形成一第一介電層於該表面並覆蓋該些 突起部，之後，設置至少一電子元件於該第一介電層，該 電子元件之一主動面係朝向該第一介電層，該電子元件之 複數個接點係形成於該主動面上且該些接點係對應於該 些大起部’接著’形成一第二介電層於該第一介電層，之 後，设置一載板於該電子元件上並進行一微壓印步驟，以 使該第一介電層形成有複數個開口，並且該些開口係對應 該電子元件之該些接點，最後，移除該模具，以形成内埋 凡件之基板，其係具有簡化製程之功效且由於該内埋元件 之基板製程係藉由微壓印步驟以形成開口，可避免殘留之 姓刻液污染。 依本發明之一種内埋元件之基板製程，首先，提供一 杈具，該模具係具有一表面及複數個突起部，該些突起部 係形成於該表面上，接著， 覆盍該些突起部，之後，言3 ’形成一第一介電層於該表面並
些開口係對應該電子元 進行一微壓印步驟，其係藉由該模具 一介電層形成有複數個開口，並且該 元件之該些接點，最後，移除該模具。 8

Claims (1)

  1. 案號96108330 年月日 修正 十、申請專利範圍： 1、 /種内埋元件之基板製程’其係包含： 提供一模具’該模具係具有一表面及複數個突起部， 該些突起部係形成於該表面上； 形成一第一介電層於該表面並覆蓋該些突起部； 設置至少一電子元件於該第一介電層，該電子元件係 具有一主動面、一背面及複數個接點，該主動面係朝 向該第一介電層’該些接點係形成於該主動面上，其 中該些接點係對應於該些突起部； 形成一第二介電層於該第一介電層；以及 設置一載板於該電子元件之該背面上。 2、 如申請專利範圍第1項所述之内埋元件之基板製程， 其中該第二介電層係覆蓋該電子元件。 3、 如申請專利範圍第2項所述之内埋元件之基板製程， 其另包含有：利用一整平步驟使該第二介電層顯露出 該電子元件之該背面，使得該載板得以貼設於該背 面。 4如申凊專利！已圍第3項所述之内埋元件之基板製程， 其中該第二介電廣與該電子元件之該背面係共平面。 5如申5月專利|巳圍第j項所述之内埋元件之基板製程， 其中該第一介電層係為半固化態。 如申5月專利範圍第1項所述之内埋元件之基板製程， 其另包含有：進行-微壓印步驟，其係藉由該模具之 該些突起部使該第-介電層形成有複數個開口 ’該些 案號96108330 年月日 修正 開口係對應該電子元件之該些接點。 7如申請專利範圍第6項所述之内埋元件之基板製程， 其中在該微壓印步驟中，係以紫外光固化該第一介電 層。 如申β專利範圍第6項所述之内埋元件之基板製程， 其另包含有：移除該模具以顯露出該些開口。 如申β專利範圍第8項所述之内埋元件之基板製程， 其中該些開口係顯露該些接點。 如申明專利範圍第丨項所述之内埋元件之基板製程， 其另包含有：形成一重分配線路層於該第一介電層 上’ 4重分配線路層係具有複數個重分配墊，該些重 刀配墊係電性連接至該電子元件之該些接點。 如申凊專利範圍第1項所述之内埋元件之基板製程， 其中該載板係選自於矽基板或玻璃基板。 如申清專利範圍第1項所述之内埋元件之基板製程， 其中該模具係為一透明材質。 如申明專利範圍第1項所述之内埋元件之基板製程， 其中該載板係以一膠帶貼設於該電子元件之該背面。 1 4、一種内埋元件之基板製程，其係包含： 提ί、模具，該模具係具有一表面及複數個突起部， 該些突起部係形成於該表面上； 形成一第一介電層於該表面並覆蓋該些突起部； 設置至少一電子元件於該第一介電層，該電子元件係 具有-主動面、一背面及複數個接點，該主動面係朝 15 15 > 16、 17、 18 > 19、 20、 21 > 案號96108330 年月日 修正 向省第；|電層，該些接點係形成於該主動面上，其 中該些接點係對應於該些突起部； 設置-載板於該電子元件之該背面上； 進行微® Ep步驟，其係藉由該模具之該&突起部在 δ玄第-介電層上形成複數個開口，該些開口係對應該 電子元件之該些接點；以及 移除該模具以顯露出該些開口。 申β專利範圍第丨4項所述之内埋元件之基板製程， 其中該第一介電層係為半固化態。 如申4專利範圍第14項所述之内埋元件之基板製程， 其中該些開口係顯露該些接點。 如申請專利範圍第14項所述之内埋元件之基板製程， 其中在該微壓印步驟中，係以紫外光固化該第一介電 層。 如申明專利範圍第14項所述之内埋元件之基板製程， 其另包3有.形成—重分配線路層於該第一介電層 上，忒重分配線路層係具有複數個重分配墊，該些重 分配墊係電性連接至該電子元件之該些接點。 如申凊專利範圍第丨4項所述之内埋元件之基板製程， 其中該载板係選自於矽基板或玻璃基板。 如申喷專利範圍第丨4項所述之内埋元件之基板製程， 其中該模具係為一透明材質。 如申明專利範圍第i 4項所述之内埋元件之基板製程， 其中該載板係以一膠帶貼設於該電子元件之該背面。 22133.1386 23、 % 24、 25、 26 ' 27、 案號96108330 年月曰 修正 、一種内埋元件之封裝製程，其係包含： 提供杈具，該模具係具有一表面及複數個突起部， 該些突起部係形成於該表面上； 形成一第—介電層於該表面並覆蓋該些突起部； :置至少-電子元件於該第-介電層，該電子元件係 具有一主動面、一背面及複數個接點，該主動面係朝 向該第一介電層，該些接點係形成於該主動面上，其 中该些接點係對應於該些突起部； 、 形成一第二介電層於砝第一介電層； "又置一載板於該電子元件之該背面上；以及 進行一微壓印步驟，其係藉由該模具之該些突起部在 及第一介電層上形成複數個開口，該些開口係對應該 電子元件之該些接點。 如申請專利範圍第22項所述之内埋元件之封裝製程， 其中該第二介電層係覆蓋該電子元件。 如申請專利範圍第23項所述之内埋元件之封裝製程， 其另包含有：利用一整平步驟使該第二介電層顯露出 該電子元件之該背面，使得該載板得以貼設於該背 面0 如申請專利範圍第24項所述之内埋元件之封裝製程， 其中該第二介電層與該電子元件之該背面係共平面。 如申請專利範圍第22項所述之内埋元件之封裝製程， 其中該第一介電層係為半固化態。 如申請專利範圍第22項所述之内埋元件之封裝製程， 17 28' 28' 案號 96108330 年月日 修正 係以紫外光固化該第一介f 29、 30、 31 > 32、 33 ' 34、 35 ' 其中在該微壓印步驟中 層。 如申π專利範圍第22項所述之内埋元件之封裝製程， 其另包含有·移除該模具以顯露出該些開口。 如申"月專利$&圍第29項所述之内埋元件之封褒製程， 其中該些開口係顯露該些接點。 申明專利範圍第22項所述之内埋元件之封裝製程， 其另包含有：形成一重分配線路層於該第一介電層 上，該重分配線路層係具有複數個重分配墊，該些^ 分配墊係電性連接至該電子元件之該些接點。— 申明專利範圍第2 2項所述之内埋元件之封裝掣程， 其中該载板係選自於矽基板或玻璃基板。、、， 如申明專利範圍第22項所述之内埋元件之封裝製程， 其中該模具係為—透明材質。 如申π專利範圍第22項所述之内埋元件之封裝製程， 其中該載板係以一膠帶貼設於該電子元件之該背面。 如申請專利範圍第22項所述之内埋元件之封裝製程， 其另包含有：進行一移除該載板之步驟。 如申請專利範圍第22項所述之内埋元件之封裝製程， 其另包含有：進行一切割步驟。
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