TWI393223B - 半導體封裝結構及其製造方法 - Google Patents

半導體封裝結構及其製造方法 Download PDF

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TWI393223B
TWI393223B TW098106892A TW98106892A TWI393223B TW I393223 B TWI393223 B TW I393223B TW 098106892 A TW098106892 A TW 098106892A TW 98106892 A TW98106892 A TW 98106892A TW I393223 B TWI393223 B TW I393223B
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heat sink
layer
sealing material
wafers
wafer
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Min Lung Huang
Chih Yuan Cheng
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Advanced Semiconductor Eng
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    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Description

半導體封裝結構及其製造方法
本發明是有關於一種半導體封裝結構及其製造方法，且特別是有關於一種具有散熱片之半導體封裝結構及其製造方法。
近年來電子裝置蓬勃的應用於日常生活中，業界無不致力發展微型且多功能之電子產品，以符合市場需求。晶圓級封裝件(Wafer Level Package,WLP)係目前電子產品之半導體元件常用之封裝結構。
隨著產品應用的尺寸越來越小、功能越趨繁多，為了使晶片的工作效能發揮極致，對於晶片在運作過程中所產生的熱能，必須提供有效的散熱途徑，以保護其內部線路，防止晶片因過熱而影響其運作效能或受損等問題的發生。
本發明係有關於一種半導體封裝結構及其製造方法，直接利用封膠層之固化製程將散熱片固定於晶片上。
根據本發明之一方面，提出一種半導體封裝結構，包括：一晶片、一散熱片(heatspeader)、一封膠層(molding compound)、一重新佈線層、以及數個銲球。封膠層包覆晶片且固定散熱片於晶片上。晶片具有一主動表面，重新佈線層係設置於晶片之主動表面。數個銲球係設置於重新佈線層上。
根據本發明之另一方面，提出一種半導體封裝結構之製造方法，包括下列步驟：提供具有一黏貼層之一載具(carrier)；配置數個晶片於黏貼層上；置放一封膠材料於黏貼層上，使得封膠材料包覆數個晶片；置放一散熱片於數個晶片上；固化封膠材料為一封膠層，以使封膠層固定散熱片於晶片上；移除載具及黏貼層，以暴露出數個晶片之主動表面；形成一重新佈線層(redistribution layer,RDL)於數個晶片之主動表面；配置數個銲球於重新佈線層上；以及依據數個晶片的位置，切割重新佈線層、封膠層及散熱片，以形成數個封裝件。
為讓本發明之上述內容能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：
 第一實施例
請參照第1A圖，其繪示依照本發明一第一實施例之一半導體封裝結構之示意圖。第1A圖之半導體封裝結構包括：一晶片210、一散熱片(heatspeader)230、一封膠層(molding compound)220、一重新佈線層240、數個銲球250以及數個銲墊260。封膠層220包覆晶片210且固定散熱片230於晶片210上。晶片210具有一主動表面210a及一背面210b，重新佈線層240係設置於晶片210之主動表面210a，而散熱片230係固定於晶片210之背面210b。數個銲球係250設置於重新佈線層240上。數個銲墊260係設置於晶片210之主動表面210a。
散熱片230具有一散熱面230a及一接合面230b，接合面230b係與散熱面230a相對。如第1A圖所示，接合面230b係為一粗糙表面，以增加接合面230b與封膠層220間之附著力，使散熱片230、封膠層220及晶片210緊密接合。散熱片230之接合面230b係面向晶片210之背面210b，且接合面230b之面積係大於背面210b之面積。在本實施例中，散熱片230之散熱面230a係外露於空氣中，一方面可提高散熱之效能，另一方面亦有助於後續之油墨印刷或塗佈(coating)製程。
第2A~2L圖繪示依照本發明第一實施例之半導體封裝結構之製造方法的示意圖。首先，在第2A圖中，提供具有一黏貼層205之一載具(carrier)200。黏貼層205之兩表面皆具有黏性，其中一表面係黏貼於載具200。
接著，於第2B圖中，將數個晶片210配置於黏貼層205上。由於黏貼層205之另一表面亦具有黏性，數個晶片210係直接貼附於黏貼層205之另一表面。
如第2C圖所示，置放一封膠材料220m於黏貼層205上，使得封膠材料220m包覆數個晶片210。此置放封膠材料220m之步驟係較佳地以點膠方式進行。
第2C圖及第2D圖係繪示將散熱片230固定於封裝結構中之具體作法，主要係置放一散熱片230於數個晶片210上，並固化封膠材料220m為一封膠層，以使封膠層220固定散熱片230於晶片210上。此固化製程可分為第一固化階段及第二固化階段。
第一固化階段係先對封膠材料200進行初步加熱，以使封膠材料220m呈現半固化狀態。當加熱封膠材料220m至半固化時，再將散熱片230置放於數個晶片210上。在此置放散熱片230之步驟中，本方法更包括：提供一模具235，且對準模具235與載具200，使得模具235覆蓋封膠材料200m及散熱片230。同時，下壓模具235，以使散熱片230之接合面230b佈滿封膠材料200m，且部分封膠材料200m回填至散熱片230之散熱面230a。而後進行脫膜，以使模具235脫離。
第二固化階段係繼續加熱封膠材料220m，以完全固化封膠材料220m為封膠層220。封膠材料220m一旦固化形成了封膠層，便可將散熱片230穩固地固定於晶片210上。如第2E圖所示，封膠層220係位於散熱片230之接合面230b的下方，而散熱片之散熱面230a所殘留之已固化的封膠材料220f則係製程中回填至散熱面230a的封膠材料220m。
接著，在第2F圖中，本實施例之製造方法更包括：利用研磨設備270研磨殘留於散熱面230a之封膠材料220f。經過研磨製程之後，散熱面230a得以外露於空氣中，如第2G圖所示。而後，依序移除載具200及黏貼層205，以暴露出數個晶片210之主動表面210a，如第2H圖所示。
再者，於第21圖中，將整個結構上下翻轉，以利於第2J圖形成一重新佈線層240於數個晶片210之主動表面210a。接著，在第2K圖中，配置數個銲球250於重新佈線層240上。
最後，在第2L圖中，依據數個晶片210的位置，以切割治具280切割重新佈線層240、封膠層220及散熱片230，以形成數個封裝件P1。
第二實施例
本實施例相較於第一實施例，主要差異在於封膠體與散熱片間之空間關係及省略研磨製程。
請參照第1B圖，其繪示依照本發明一第二實施例之一半導體封裝結構之示意圖。第1B圖之半導體封裝結構包括：一晶片310、一散熱片330、一封膠層320、一重新佈線層340、數個銲球350以及數個銲墊360。封膠層320包覆晶片310且固定散熱片330於晶片310上。封膠層320包括第一封膠層320a及第二封膠層320b，分別位於散熱片330之接合面330b及散熱面330a。晶片310具有一主動表面310a及一背面310b，重新佈線層340係設置於晶片310之主動表面310a，而散熱片330係固定於晶片310之背面310b。數個銲球係350設置於重新佈線層340上。數個銲墊360係設置於晶片310之主動表面310a。
散熱片330具有一散熱面330a及一接合面330b，接合面330b係與散熱面330a相對。如第1B圖所示，接合面330b係為一粗糙表面，以增加接合面330b與第一封膠層320a間之附著力，使散熱片330、第一封膠層320a及晶片310緊密接合。此外，散熱片330之散熱面330a亦同樣可為一粗糙表面，以增加散熱面330a與第二封膠層320b間之附著力，使散熱片330及第二封膠層320b緊密接合。散熱片330之接合面330b係面向晶片310之背面310b，且接合面330b之面積係大於背面310b之面積。相較於第一實施例，本實施例之散熱片330之散熱面330a尚覆蓋一第二封膠層320b，不但可增加封膠層320固定散熱片330之力量，更可省略後續之油墨印刷或塗佈(coating)製程，而直接用雷射對第二封膠層320b進行切刻製程。
第3A~3L圖繪示依照本發明第一實施例之半導體封裝結構之製造方法的示意圖。首先，在第3A圖中，提供具有一黏貼層305之一載具300。黏貼層305之兩表面皆具有黏性，其中一表面係黏貼於載具300。
接著，於第3B圖中，將數個晶片310配置於黏貼層305上。由於黏貼層305之另一表面亦具有黏性，數個晶片310係直接貼附於黏貼層305之另一表面。
如第3C圖所示，置放一封膠材料320m於黏貼層305上，使得封膠材料320m包覆數個晶片310。此置放封膠材料320m之步驟係較佳地以點膠方式進行。
第3C圖及第3D圖係繪示將散熱片330固定於封裝結構中之具體作法，主要係置放一散熱片330於數個晶片310上，並固化封膠材料320m為一封膠層，以使封膠層320固定散熱片330於晶片310上。此固化製程可分為第一固化階段及第二固化階段。
第一固化階段係先對封膠材料300進行初步加熱，以使封膠材料320m呈現半固化狀態。當加熱封膠材料320m至半固化時，再將散熱片330置放於數個晶片310上。在此置放散熱片330之步驟中，本方法更包括：提供一模具335，且對準模具335與載具300，使得模具335覆蓋封膠材料300m及散熱片330。同時，下壓模具335，以使散熱片330之接合面330b佈滿封膠材料300m，且部分封膠材料300m回填至散熱片330之散熱面330a。而後進行脫膜，以使模具335脫離。
第二固化階段係繼續加熱封膠材料320m，以完全固化封膠材料320m為封膠層320。封膠材料320m一旦固化形成了封膠層320，便可將散熱片330穩固地固定於晶片310上。如第3E圖所示，封膠層320包括位於散熱片330之接合面330b下方之第一封膠層320a，以及位於散熱片之散熱面330a上之第二封膠層320b。第二封膠層320b係由製程中回填至散熱面330a的封膠材料320m所形成。
相較於第一實施例，本實施例係保留於製程中回填至散熱面330a的封膠材料320m所形成之第二封膠層320b，而省略研磨製程。因此，散熱片330之散熱面330a及接合面330b皆覆蓋有已固化之封膠材料，而能增加固定散熱片330之力量。
而後，依序於第3E圖移除載具300且於第3F圖移除黏貼層305，以暴露出數個晶片310之主動表面310a，如第3G圖所示。
再者，於第3H圖中，將整個結構上下翻轉，以利於第3I圖形成一重新佈線層340於數個晶片310之主動表面310a。接著，在第3J圖中，配置數個銲球350於重新佈線層340上。
最後，在第3K圖中，依據數個晶片310的位置，以切割治具380切割重新佈線層340、第一封膠層320a、散熱片330及第二封膠層320b，以形成數個封裝件P2。
本發明上述實施例所揭露之半導體封裝結構及其製造方法，係直接利用封膠層之固化製程將散熱片固定於晶片上，使得散熱片與晶片之間不需另以散熱膠黏合，可減少一道黏合製程，降低製造成本。再者，散熱片所具有之粗糙表面可增加該表面與該封膠層間之附著力，有助於後續之切割製程。此外，直接以封膠層來固定散熱片的作法，亦可因減少散熱膠的厚度而使整個封裝件具有較薄的厚度，能提高產品競爭力。
綜上所述，雖然本發明已以一較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
200、300．．．載具
205、305．．．黏貼層
210、310．．．晶片
210a、310a．．．主動表面
210b、310b．．．背面
220、320．．．封膠層
220m、320m．．．封膠材料
220f．．．已固化之封膠材料
230、330．．．散熱片
230a、330a．．．散熱面
230b、330b．．．接合面
240、340．．．重新佈線層
250、350．．．銲球
260、360．．．銲墊
270．．．研磨設備
280、380．．．切割治具
320a．．．第一封膠層
320b．．．第二封膠層
第1A圖繪示依照本發明一第一實施例之一半導體封裝結構之示意圖。
第1B圖繪示依照本發明一第二實施例之一半導體封裝結構之示意圖。
第2A~2L圖繪示依照本發明第一實施例之半導體封裝結構之製造方法的示意圖。
第3A~3K圖繪示依照本發明第二實施例之半導體封裝結構之製造方法的示意圖。
210．．．晶片
210a．．．主動表面
210b．．．背面
220．．．封膠層
230．．．散熱片
230a．．．散熱面
230b．．．接合面
240．．．重新佈線層
250．．．銲球
260．．．銲墊

Claims (8)

  1. 一種半導體封裝結構之製造方法，包括下列步驟：提供具有一黏貼層之一載具(carrier)；配置複數個晶片於該黏貼層上，其中每一該些晶片具有一主動表面及一背面，該些主動表面貼附於該黏貼層上；置放一封膠材料於該黏貼層上，使得該封膠材料包覆該些晶片；置放一散熱片於該些晶片之該背面上；固化該封膠材料為一封膠層，以使該封膠層固定該散熱片於該晶片上；移除該載具及該黏貼層，以暴露出該些晶片之該些主動表面；形成一重新佈線層於該些晶片之該些主動表面；配置複數個銲球於該重新佈線層上；以及依據該些晶片的位置，切割該重新佈線層、該封膠層及該散熱片，以形成複數個封裝件。
  2. 如申請專利範圍第1項所述之製造方法，其中該固化步驟包括：加熱該封膠材料，以半固化該封膠材料；以及繼續加熱該封膠材料，以完全固化該封膠材料為該封膠層。
  3. 如申請專利範圍第2項所述之製造方法，其中當加熱該封膠材料至半固化時，將該散熱片置放於該些晶片上。
  4. 如申請專利範圍第2項所述之製造方法，其中當加熱該封膠材料至完全固化為該封膠層時，該封膠層將該散熱片穩固地固定於該晶片上。
  5. 如申請專利範圍第1項所述之製造方法，其中在置放該散熱片之步驟中，該方法更包括：提供一模具；對準該模具與該載具，使得該模具覆蓋該封膠材料及該散熱片；下壓該模具，以使該散熱片之一接合面佈滿該封膠材料，且該封膠材料回填至該散熱片之一散熱面；以及進行脫膜以使該模具脫離。
  6. 如申請專利範圍第5項所述之製造方法，其中該方法更包括：研磨殘留於該散熱面之該封膠材料，以使該散熱面外露於空氣中。
  7. 如申請專利範圍第1項所述之製造方法，其中置放該封膠材料之該步驟係以點膠方式進行。
  8. 如申請專利範圍第1項所述之製造方法，更包括：配置複數個銲墊於該些晶片之主動表面。
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Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8258624B2 (en) 2007-08-10 2012-09-04 Intel Mobile Communications GmbH Method for fabricating a semiconductor and semiconductor package
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
TWI456715B (zh) * 2009-06-19 2014-10-11 Advanced Semiconductor Eng 晶片封裝結構及其製造方法
TWI466259B (zh) * 2009-07-21 2014-12-21 Advanced Semiconductor Eng 半導體封裝件、其製造方法及重佈晶片封膠體的製造方法
TWI405306B (zh) 2009-07-23 2013-08-11 Advanced Semiconductor Eng 半導體封裝件、其製造方法及重佈晶片封膠體
US20110084372A1 (en) 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
US8378466B2 (en) 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8372689B2 (en) 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
US8320134B2 (en) 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
KR20130123682A (ko) * 2012-05-03 2013-11-13 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US20130337614A1 (en) * 2012-06-14 2013-12-19 Infineon Technologies Ag Methods for manufacturing a chip package, a method for manufacturing a wafer level package, and a compression apparatus
JP6154917B2 (ja) * 2013-02-28 2017-06-28 ヒューレット−パッカード デベロップメント カンパニー エル．ピー．Ｈｅｗｌｅｔｔ‐Ｐａｃｋａｒｄ Ｄｅｖｅｌｏｐｍｅｎｔ Ｃｏｍｐａｎｙ， Ｌ．Ｐ． 成形された流体流れ構造
JP6068684B2 (ja) 2013-02-28 2017-01-25 ヒューレット−パッカード デベロップメント カンパニー エル．ピー．Ｈｅｗｌｅｔｔ‐Ｐａｃｋａｒｄ Ｄｅｖｅｌｏｐｍｅｎｔ Ｃｏｍｐａｎｙ， Ｌ．Ｐ． 流体流れ構造の成形
US10821729B2 (en) 2013-02-28 2020-11-03 Hewlett-Packard Development Company, L.P. Transfer molded fluid flow structure
KR102005466B1 (ko) 2013-02-28 2019-07-30 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. 프린트 바
US9724920B2 (en) 2013-03-20 2017-08-08 Hewlett-Packard Development Company, L.P. Molded die slivers with exposed front and back surfaces
US9230878B2 (en) 2013-04-12 2016-01-05 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Integrated circuit package for heat dissipation
US9768038B2 (en) * 2013-12-23 2017-09-19 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of making embedded wafer level chip scale packages
CN105934345B (zh) 2014-01-28 2017-06-13 惠普发展公司，有限责任合伙企业 柔性载体
KR20150135611A (ko) * 2014-05-22 2015-12-03 에스케이하이닉스 주식회사 멀티 칩 패키지 및 제조 방법
US10600753B2 (en) * 2015-08-28 2020-03-24 Texas Instruments Incorporated Flip chip backside mechanical die grounding techniques
DE102016105243A1 (de) * 2016-03-21 2017-09-21 Infineon Technologies Ag Räumlich Selektives Aufrauen von Verkapselungsmasse, um eine Haftung mit einer Funktionsstruktur zu Fördern
US10529593B2 (en) * 2018-04-27 2020-01-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package comprising molding compound having extended portion and manufacturing method of semiconductor package
CN111668098A (zh) * 2019-03-08 2020-09-15 矽磐微电子(重庆)有限公司 半导体封装方法
CN111312670B (zh) * 2020-02-26 2022-04-01 南通智通达微电子物联网有限公司 一种散热封装方法
TW202143401A (zh) * 2020-05-08 2021-11-16 力成科技股份有限公司 半導體封裝方法及其結構

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040012099A1 (en) * 2002-02-26 2004-01-22 Toshinori Nakayama Semiconductor device and manufacturing method for the same, circuit board, and electronic device
TW200612533A (en) * 2004-10-08 2006-04-16 Advanced Semiconductor Eng Flip chip quad flat non-leaded package structure and manufacturing method thereof
TWI264125B (en) * 2005-07-05 2006-10-11 Advanced Semiconductor Eng Package of die with heat sink and method of making the same
US20060231944A1 (en) * 2005-04-15 2006-10-19 Siliconware Precision Industries Co., Ltd. Thermally enhanced semiconductor package and fabrication method thereof
TW200905847A (en) * 2007-07-30 2009-02-01 Advanced Semiconductor Eng Chip package and chip packaging process thereof
TW200908279A (en) * 2007-08-07 2009-02-16 Advanced Semiconductor Eng Package having a self-aligned die and the method for making the same, and a stacked package and the method for making the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI253155B (en) * 2003-05-28 2006-04-11 Siliconware Precision Industries Co Ltd Thermally enhanced semiconductor package and fabrication method thereof
US20060065387A1 (en) * 2004-09-28 2006-03-30 General Electric Company Electronic assemblies and methods of making the same
TWI246757B (en) * 2004-10-27 2006-01-01 Siliconware Precision Industries Co Ltd Semiconductor package with heat sink and fabrication method thereof
US7371676B2 (en) * 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040012099A1 (en) * 2002-02-26 2004-01-22 Toshinori Nakayama Semiconductor device and manufacturing method for the same, circuit board, and electronic device
TW200612533A (en) * 2004-10-08 2006-04-16 Advanced Semiconductor Eng Flip chip quad flat non-leaded package structure and manufacturing method thereof
US20060231944A1 (en) * 2005-04-15 2006-10-19 Siliconware Precision Industries Co., Ltd. Thermally enhanced semiconductor package and fabrication method thereof
TWI264125B (en) * 2005-07-05 2006-10-11 Advanced Semiconductor Eng Package of die with heat sink and method of making the same
TW200905847A (en) * 2007-07-30 2009-02-01 Advanced Semiconductor Eng Chip package and chip packaging process thereof
TW200908279A (en) * 2007-08-07 2009-02-16 Advanced Semiconductor Eng Package having a self-aligned die and the method for making the same, and a stacked package and the method for making the same

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