US4161663A - High voltage CMOS level shifter - Google Patents

High voltage CMOS level shifter Download PDF

Info

Publication number
US4161663A
US4161663A US05/885,248 US88524878A US4161663A US 4161663 A US4161663 A US 4161663A US 88524878 A US88524878 A US 88524878A US 4161663 A US4161663 A US 4161663A
Authority
US
United States
Prior art keywords
voltage
level shifter
transistor devices
source
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US05/885,248
Inventor
Miguel A. Martinez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Boeing North American Inc
Original Assignee
Rockwell International Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rockwell International Corp filed Critical Rockwell International Corp
Priority to US05/885,248 priority Critical patent/US4161663A/en
Priority to GB7905191A priority patent/GB2016234B/en
Priority to JP54025020A priority patent/JPS5915216B2/en
Priority to DE2909388A priority patent/DE2909388C3/en
Application granted granted Critical
Publication of US4161663A publication Critical patent/US4161663A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger

Definitions

  • This invention relates to a high voltage level shifter circuit comprised of CMOS transistor devices.
  • CMOS voltage level shifter circuits are relatively unreliable for high voltage applications.
  • CMOS transistor devices e.g. n-channel FETs
  • the diode junction of certain CMOS transistor devices become back biased so as to consequently cause transistor breakdown and failure when relatively low input voltages, typically in the order of 15 volts, are exceeded.
  • the output voltage swing of the prior art level shifter circuits is undesirably limited.
  • CMOS voltage level shifter is disclosed that is suitable for high voltage applications.
  • the present level shifter is comprised of first and second p-channel FETs and first and second pairs of series connected n-channel FETs.
  • First conduction path electrodes of each of the p-channel FETs are respectively connected to first and second level shifter input terminals.
  • the gate electrodes of each of the p-channel FETs are connected together at a first source of supply voltage.
  • Second conduction path electrodes of each of the p-channel FETs are respectively connected to first and second level shifter output terminals.
  • the first and second pairs of series connected n-channel FETs are connected between a second source of supply voltage and a respective one of the first and second level shifter output terminals.
  • the gate electrodes of the first pair of series connected n-channel FETs are connected together and to the second level shifter output terminal.
  • the gate electrodes of the second pair of series connected n-channel FETs are connected together and to the first level shifter output terminal.
  • the present voltage level shifter is relatively unsusceptible to low voltage transistor breakdown, and, therefore, an extended, wide output voltage swing can be achieved.
  • FIG. 2 is a schematic circuit of the presently disclosed high voltage CMOS level shifter.
  • FIG. 1 illustrates one example of the schematic circuit for a prior art CMOS voltage level shifter 1.
  • the prior art voltage level shifter 1 includes first and second input terminals 2 and 4.
  • Input terminal 2 is adapted to receive a first input signal, designated V in .
  • Input terminal 4 is adapted to receive a second input signal, designated V in , the signal level of which is inverted with respect to that of the first input signal V in .
  • the conduction path of a first p-channel field effect transistor (FET) Q 1 is connected between a source of relatively positive supply voltage, designated V DD , and an electrical junction 6.
  • the second level shifter input terminal 4 is connected to the control or gate electrode of FET Q 1 .
  • FET field effect transistor
  • the conduction path of a second p-channel field effect transistor (FET) Q 2 is connected between the source of supply voltage V DD and an electrical junction 8.
  • the first level shifter input terminal 2 is connected to the gate electrode of FET Q 2 .
  • the electrical junctions 6 and 8 provide first and second level shifter output signals, designated V out and V out , respectively.
  • the conduction path of a first n-channel FET Q 3 is connected between the electrical junction 6 and a source of relatively negative supply voltage, designated V S .
  • the conduction path of a second n-channel FET Q 4 is connected between the electrical junction 8 and the source of supply voltage V S .
  • the gate electrodes of FETs Q 3 and Q 4 are cross-connected relative to one another. That is, the gate electrode of FET Q 3 is connected to the electrical junction 8, and the gate electrode of FET Q 4 is connected to the electrical junction 6.
  • the electrical junction 8 is driven towards the signal level of the source of positive supply voltage V DD via the conduction path of FET Q 2 .
  • FET Q 3 is rendered conductive, inasmuch as the gate electrode thereof is connected to the electrical junction 8.
  • the electrical junction 6 is, thereby, driven towards the source of negative supply voltage V S via the conduction path of FET Q 3 .
  • FET Q 4 is rendered non-conductive, inasmuch as the gate electrode thereof is connected to the electrical junction 6.
  • the level shifter output signal V out that is applied to the electrical junction 6 achieves the full V S voltage level via conduction path of FET Q 3 .
  • the level shifter output signal V out that is applied to the electrical junction 8 achieves the full V DD voltage level via the conduction path of FET Q 2 .
  • each of two field effect transistors absorbs the full output voltage swing (i.e. from V S to V DD ). More particularly, in the example described above, each of the FETs Q 1 and Q 4 absorbs the full output voltage swing across the respective source-to-drain conduction path thereof.
  • relatively low input voltage signals typically in the order of 15 volts
  • field effect transistor devices e.g. n-channel FETs Q 3 and Q 4
  • the range of the output voltage swing that can be achieved by utilization of the prior art voltage level shifters is undesirably limited.
  • FIG. 2 illustrates the schematic circuit for an improved high voltage CMOS level shifter 20.
  • the improved CMOS level shifter 20 includes first and second input terminals 22 and 24.
  • Input terminal 22 is adapted to receive a first input signal, designated V in .
  • Input terminal 24 is adapted to receive a second input signal, designated V in , the signal level of which is inverted with respect to that of the first input signal V in .
  • the conduction path of a first p-channel field effect transistor (FET) Q 5 is connected between the first level shifter input terminal 22 and an electrical junction 26.
  • the conduction path of a second p-channel field effect transistor (FET) is connected between the second level shifter input terminal 24 and an electrical junction 28.
  • the control or gate electrodes of FETs Q 5 and Q 6 are connected together and to a source of relatively positive supply voltage, such as ground.
  • the electrical junctions 26 and 28 provide first and second level shifter output signals, designated V out and V out , respectively.
  • the conduction paths of a first pair of n-channel FETs Q 7 and Q 8 are connected in electrical series between the electrical junction 26 and an electrical junction 30.
  • the electrical junction 30 is connected to a source of relatively negative supply voltage (typically -15 volts d.c.), designated V S .
  • the conduction paths of a second pair of n-channel FETs Q 9 and Q 10 are connected in electrical series between the electrical junctions 28 and 30.
  • the control or gate electrodes of FETs Q 7 and Q 8 and FETs Q 9 and Q 10 are cross-connected relative to one another. That is, the gate electrodes of each of the FETs Q 7 and Q 8 are connected together and to the electrical junction 28. The gate electrodes of each of the FETs Q 9 and Q 10 are connected together and to the electrical junction 26.
  • CMOS voltage level shifter 20 The operation of the presently disclosed CMOS voltage level shifter 20 is described as follows.
  • a relatively low signal level e.g. ground
  • p-channel FET Q 5 is cutoff, due to the lack of sufficient threshold voltage applied to the gate-to-source junction thereof.
  • FET Q 5 is, thereby, rendered non-conductive.
  • V DD typically +6 volts d.c.
  • the electrical junction 28 is driven towards the V DD level of the V in input voltage signal via the conduction path of FET Q 6 .
  • the voltage of the electrical junction 28 approximates the V DD voltage level, each of the p-channel FETs Q 7 and Q 8 are rendered conductive, inasmuch as the gate electrodes thereof are connected together to receive the positive voltage of electrical junction 28.
  • the electrical junction 26, is, thereby, driven towards the source of supply voltage V S via the series connected conduction paths of FETs Q 7 and Q 8 .
  • the n-channel FETs Q 9 and Q 10 are rendered non-conductive, inasmuch as the gate electrodes of the FETs Q 9 and Q 10 are connected together to receive the negative voltage of the electrical junction 26. Therefore, the level shifter output signal V out that is applied to the electrical junction 28 achieves the full V DD voltage level via the conduction path of FET Q 6 . Moreover, the level shifter output signal V out that is applied to the electrical junction 26 achieves the full voltage level of the source of supply voltage V S via the conduction paths of FETs Q 7 and Q 8 .
  • the operation of the present voltage level shifter 20 is similar to that described above.
  • the level shifter output signal V out that is applied to the electrical junction 28 achieves the full V S supply voltage via the conduction paths of FETs Q 9 and Q 10 .
  • the level shifter output signal V out that is applied to the electrical junction 26 achieves the full V DD voltage level via the conduction path of FET Q 5 .
  • the input voltage signals V in and V in which have a voltage swing of approximately 6 volts between ground and V DD , are level shifted to output voltage signals V out and V out , which accordingly have a corresponding voltage swing of approximately 21 volts between V S and V DD .
  • no single field effect transistor absorbs the full output voltage swing (i.e. from V S to V DD ) across the respective conduction path thereof.
  • the presently disclosed level shifter 20 is both reliable and relatively unsusceptible to low voltage transistor breakdown. What is more, the wide range output voltage swing of the present level detector is maximized.
  • the presently disclosed level shifter 20 is suitable for high voltage applications (e.g. typically in the order of 25-30 volts).

Landscapes

  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)

Abstract

A reliable voltage level shifter circuit implemented with complementary metal oxide semiconductor field effect transistor (MOSFET) devices, suitable for high voltage applications. The disclosed circuit is relatively unsusceptible to low voltage transistor breakdown, whereby a wide range output voltage swing is achieved.

Description

The invention herein described was made in the course of or under a contract or subcontract thereunder with the Department of the Air Force.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a high voltage level shifter circuit comprised of CMOS transistor devices.
2. Statement of the Prior Art
Conventional CMOS voltage level shifter circuits are relatively unreliable for high voltage applications. As a result of the prior art level shifter circuit implementation and deficiencies in device processing, the diode junction of certain CMOS transistor devices (e.g. n-channel FETs) become back biased so as to consequently cause transistor breakdown and failure when relatively low input voltages, typically in the order of 15 volts, are exceeded. Hence, due to the high susceptibility for breakdown of the component transistor devices, the output voltage swing of the prior art level shifter circuits is undesirably limited.
Examples of conventional voltage level shifter circuits are disclosed in the following U.S. Patents:
U.s. pat No. 3,942,043--Mar. 2, 1976
U.s. pat. No. 4,039,862--Aug. 2, 1977
However, none of the prior art level shifter patents shows a circuit comprising first and second p-channel field effect transistors interconnected with first and second pairs of series connected n-channel field effect transistors, as disclosed and claimed in the instant patent application, to prevent low voltage transistor breakdown and to thereby extend the range of the level shifter output voltage swing.
SUMMARY OF THE INVENTION
Briefly, and in general terms, a reliable CMOS voltage level shifter is disclosed that is suitable for high voltage applications. The present level shifter is comprised of first and second p-channel FETs and first and second pairs of series connected n-channel FETs. First conduction path electrodes of each of the p-channel FETs are respectively connected to first and second level shifter input terminals. The gate electrodes of each of the p-channel FETs are connected together at a first source of supply voltage. Second conduction path electrodes of each of the p-channel FETs are respectively connected to first and second level shifter output terminals. The first and second pairs of series connected n-channel FETs are connected between a second source of supply voltage and a respective one of the first and second level shifter output terminals. The gate electrodes of the first pair of series connected n-channel FETs are connected together and to the second level shifter output terminal. The gate electrodes of the second pair of series connected n-channel FETs are connected together and to the first level shifter output terminal. The present voltage level shifter is relatively unsusceptible to low voltage transistor breakdown, and, therefore, an extended, wide output voltage swing can be achieved.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic circuit of a prior art CMOS voltage level shifter.
FIG. 2 is a schematic circuit of the presently disclosed high voltage CMOS level shifter.
DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 illustrates one example of the schematic circuit for a prior art CMOS voltage level shifter 1. The prior art voltage level shifter 1 includes first and second input terminals 2 and 4. Input terminal 2 is adapted to receive a first input signal, designated Vin. Input terminal 4 is adapted to receive a second input signal, designated Vin, the signal level of which is inverted with respect to that of the first input signal Vin. The conduction path of a first p-channel field effect transistor (FET) Q1 is connected between a source of relatively positive supply voltage, designated VDD, and an electrical junction 6. The second level shifter input terminal 4 is connected to the control or gate electrode of FET Q1. The conduction path of a second p-channel field effect transistor (FET) Q2 is connected between the source of supply voltage VDD and an electrical junction 8. The first level shifter input terminal 2 is connected to the gate electrode of FET Q2. The electrical junctions 6 and 8 provide first and second level shifter output signals, designated Vout and Vout, respectively. The conduction path of a first n-channel FET Q3 is connected between the electrical junction 6 and a source of relatively negative supply voltage, designated VS. The conduction path of a second n-channel FET Q4 is connected between the electrical junction 8 and the source of supply voltage VS. The gate electrodes of FETs Q3 and Q4 are cross-connected relative to one another. That is, the gate electrode of FET Q3 is connected to the electrical junction 8, and the gate electrode of FET Q4 is connected to the electrical junction 6.
The operation of the prior art voltage level shifter is briefly described as follows. By way of example, when an input voltage signal Vin having a relatively high signal level (e.g. VDD) is applied to the second input terminal 4, FET Q1 is cutoff, due to the lack of sufficient threshold voltage applied to the gate-to-source junction thereof. FET Q1 is, thereby, rendered non-conductive. Inasmuch as the input voltage signal Vin that is applied to the first input terminal 2 has a relatively low signal level (e.g. ground), sufficient threshold voltage is applied to the gate-to-source junction of FET Q2, and FET Q2 is, thereby, rendered conductive. As a result, the electrical junction 8 is driven towards the signal level of the source of positive supply voltage VDD via the conduction path of FET Q2. As the voltage of the electrical junction 8 approximates the VDD voltage level, FET Q3 is rendered conductive, inasmuch as the gate electrode thereof is connected to the electrical junction 8. The electrical junction 6 is, thereby, driven towards the source of negative supply voltage VS via the conduction path of FET Q3. As the voltage at the electrical junction 6 approximates that of the source of supply voltage VS, FET Q4 is rendered non-conductive, inasmuch as the gate electrode thereof is connected to the electrical junction 6. Therefore, the level shifter output signal Vout that is applied to the electrical junction 6 achieves the full VS voltage level via conduction path of FET Q3. The level shifter output signal Vout that is applied to the electrical junction 8 achieves the full VDD voltage level via the conduction path of FET Q2.
As a consequence of the circuit configuration for the prior art voltage level shifter 1 of FIG. 1, each of two field effect transistors absorbs the full output voltage swing (i.e. from VS to VDD). More particularly, in the example described above, each of the FETs Q1 and Q4 absorbs the full output voltage swing across the respective source-to-drain conduction path thereof. Thus, relatively low input voltage signals (typically in the order of 15 volts) are known to cause drain breakdowns in certain field effect transistor devices (e.g. n-channel FETs Q3 and Q4) which comprise the prior art voltage level shifters. As a result of the high susceptibility to breakdown, the range of the output voltage swing that can be achieved by utilization of the prior art voltage level shifters is undesirably limited.
In accordance with the present invention, FIG. 2 illustrates the schematic circuit for an improved high voltage CMOS level shifter 20. The improved CMOS level shifter 20 includes first and second input terminals 22 and 24. Input terminal 22 is adapted to receive a first input signal, designated Vin. Input terminal 24 is adapted to receive a second input signal, designated Vin, the signal level of which is inverted with respect to that of the first input signal Vin. The conduction path of a first p-channel field effect transistor (FET) Q5 is connected between the first level shifter input terminal 22 and an electrical junction 26. The conduction path of a second p-channel field effect transistor (FET) is connected between the second level shifter input terminal 24 and an electrical junction 28. The control or gate electrodes of FETs Q5 and Q6 are connected together and to a source of relatively positive supply voltage, such as ground. The electrical junctions 26 and 28 provide first and second level shifter output signals, designated Vout and Vout, respectively. The conduction paths of a first pair of n-channel FETs Q7 and Q8 are connected in electrical series between the electrical junction 26 and an electrical junction 30. The electrical junction 30 is connected to a source of relatively negative supply voltage (typically -15 volts d.c.), designated VS. The conduction paths of a second pair of n-channel FETs Q9 and Q10 are connected in electrical series between the electrical junctions 28 and 30. The control or gate electrodes of FETs Q7 and Q8 and FETs Q9 and Q10 are cross-connected relative to one another. That is, the gate electrodes of each of the FETs Q7 and Q8 are connected together and to the electrical junction 28. The gate electrodes of each of the FETs Q9 and Q10 are connected together and to the electrical junction 26.
The operation of the presently disclosed CMOS voltage level shifter 20 is described as follows. When an input voltage signal Vin having a relatively low signal level (e.g. ground) is applied to the first input terminal 22, p-channel FET Q5 is cutoff, due to the lack of sufficient threshold voltage applied to the gate-to-source junction thereof. FET Q5 is, thereby, rendered non-conductive. Inasmuch as the input voltage signal Vin that is applied to the second input terminal 24 has a relatively high signal level, such as VDD (typically +6 volts d.c.), sufficient threshold voltage is applied to the gate-to-source junction of p-channel FET Q6, and FET Q6 is thereby rendered conductive. As a result, the electrical junction 28 is driven towards the VDD level of the Vin input voltage signal via the conduction path of FET Q6. As the voltage of the electrical junction 28 approximates the VDD voltage level, each of the p-channel FETs Q7 and Q8 are rendered conductive, inasmuch as the gate electrodes thereof are connected together to receive the positive voltage of electrical junction 28. The electrical junction 26, is, thereby, driven towards the source of supply voltage VS via the series connected conduction paths of FETs Q7 and Q8. As the voltage at the electrical junction 26 approximates that of the source of supply voltage VS, the n-channel FETs Q9 and Q10 are rendered non-conductive, inasmuch as the gate electrodes of the FETs Q9 and Q10 are connected together to receive the negative voltage of the electrical junction 26. Therefore, the level shifter output signal Vout that is applied to the electrical junction 28 achieves the full VDD voltage level via the conduction path of FET Q6. Moreover, the level shifter output signal Vout that is applied to the electrical junction 26 achieves the full voltage level of the source of supply voltage VS via the conduction paths of FETs Q7 and Q8.
Should the input voltage signals Vin and Vin that are applied to the level shifter input terminals 22 and 24 otherwise have relatively high and low signal levels, respectively, the operation of the present voltage level shifter 20 is similar to that described above. However, the level shifter output signal Vout that is applied to the electrical junction 28 achieves the full VS supply voltage via the conduction paths of FETs Q9 and Q10. Moreover, the level shifter output signal Vout that is applied to the electrical junction 26 achieves the full VDD voltage level via the conduction path of FET Q5.
Thus, by virtue of the presently disclosed voltage level shifter 20, the input voltage signals Vin and Vin, which have a voltage swing of approximately 6 volts between ground and VDD, are level shifted to output voltage signals Vout and Vout, which accordingly have a corresponding voltage swing of approximately 21 volts between VS and VDD. As an advantageous result of the circuit configuration of the presently disclosed CMOS voltage level shifter 20, no single field effect transistor absorbs the full output voltage swing (i.e. from VS to VDD) across the respective conduction path thereof. Hence, unlike the prior art level shifters, such as that illustrated in FIG. 1, the presently disclosed level shifter 20 is both reliable and relatively unsusceptible to low voltage transistor breakdown. What is more, the wide range output voltage swing of the present level detector is maximized. Thus, the presently disclosed level shifter 20 is suitable for high voltage applications (e.g. typically in the order of 25-30 volts).
It will be apprent that while a preferred embodiment of the invention has been shown and described, various modifications and changes may be made without departing from the true spirit and scope of the invention.

Claims (5)

Having thus set forth a preferred embodiment of the present invention, what is claimed is:
1. A voltage level shifter comprising:
first and second sources of supply voltage,
first and second transistor devices having respective conduction paths and control electrodes,
first and second pairs of series connected transistor devices having respective conduction paths and control electrodes,
first and second input terminals to receive respective input voltage signals, and
first and second output terminals to provide output voltage signals having a wide output voltage swing,
said first transistor device connected between said first input terminal and said first output terminal,
said second transistor device connected between said second input terminal and said second output terminal,
the respective control electrodes of said first and second transistor devices connected together and to said first source of supply voltage,
said first pair of series connected transistor devices connected between said first output terminal and said second source of supply voltage,
said second pair of series connected transistor devices connected between said second output terminal and said second source of supply voltage,
the respective control electrodes of each of the first pair of transistor devices connected together and to said second output terminal,
the respective control electrodes of each of the second pair of transistor devices connected together and to said first output terminal.
2. The voltage level shifter recited in claim 1, wherein each of said first and second transistor devices is of a first conductivity type and each of said first and second pairs of series connected transistor devices is of a second conductivity type.
3. The voltage level shifter recited in claim 2, wherein each of said first and second transistor devices and each of said first and second pairs of series connected transistor devices is a field effect transistor.
4. The voltage level shifter recited in claim 1, wherein each of said first and second transistor devices is a p-channel field effect transistor, and each of said first and second pairs of series connected transistor devices is an n-channel field effect transistor.
5. The voltage level shifter recited in claim 1, wherein said first source of supply voltage is positive relative to said second source of supply voltage.
US05/885,248 1978-03-10 1978-03-10 High voltage CMOS level shifter Expired - Lifetime US4161663A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US05/885,248 US4161663A (en) 1978-03-10 1978-03-10 High voltage CMOS level shifter
GB7905191A GB2016234B (en) 1978-03-10 1979-02-14 Voltage level shifter
JP54025020A JPS5915216B2 (en) 1978-03-10 1979-03-03 voltage level shifter
DE2909388A DE2909388C3 (en) 1978-03-10 1979-03-09 Voltage level shifting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/885,248 US4161663A (en) 1978-03-10 1978-03-10 High voltage CMOS level shifter

Publications (1)

Publication Number Publication Date
US4161663A true US4161663A (en) 1979-07-17

Family

ID=25386482

Family Applications (1)

Application Number Title Priority Date Filing Date
US05/885,248 Expired - Lifetime US4161663A (en) 1978-03-10 1978-03-10 High voltage CMOS level shifter

Country Status (4)

Country Link
US (1) US4161663A (en)
JP (1) JPS5915216B2 (en)
DE (1) DE2909388C3 (en)
GB (1) GB2016234B (en)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4318015A (en) * 1979-06-29 1982-03-02 Rca Corporation Level shift circuit
US4486670A (en) * 1982-01-19 1984-12-04 Intersil, Inc. Monolithic CMOS low power digital level shifter
US4490629A (en) * 1982-05-10 1984-12-25 American Microsystems, Inc. High voltage circuits in low voltage CMOS process
US4568844A (en) * 1983-02-17 1986-02-04 At&T Bell Laboratories Field effect transistor inverter-level shifter circuitry
US4864159A (en) * 1987-08-26 1989-09-05 U.S. Philips Corporation ECL to CMOS transition amplifier
US5243236A (en) * 1991-12-31 1993-09-07 Intel Corporation High voltage CMOS switch with protection against diffusion to well reverse junction breakdown
EP0600734A1 (en) * 1992-12-04 1994-06-08 Nec Corporation Level shifter
US5343094A (en) * 1993-01-13 1994-08-30 National Semiconductor Corporation Low noise logic amplifier with nondifferential to differential conversion
US5406141A (en) * 1992-07-06 1995-04-11 Sgs-Thomson Microelectronics, S.A. High voltage CMOS switching circuit
US5471149A (en) * 1993-09-27 1995-11-28 Sony Corporation High-speed large output amplitude voltage level shifting circuit
US5493244A (en) * 1994-01-13 1996-02-20 Atmel Corporation Breakdown protection circuit using high voltage detection
US6300796B1 (en) 1999-02-19 2001-10-09 Zilog, Inc. High voltage PMOS level shifter
US6580291B1 (en) 2000-12-18 2003-06-17 Cypress Semiconductor Corp. High voltage output buffer using low voltage transistors
US20070052297A1 (en) * 2003-07-28 2007-03-08 Hajime Nagai Voltage converter apparatus
US20070063758A1 (en) * 2005-09-22 2007-03-22 Honeywell International Inc. Voltage divider and method for minimizing higher than rated voltages
US20080079708A1 (en) * 2006-10-03 2008-04-03 Abhishek Bandyopadhyay Low voltage driver for high voltage LCD
US20080238522A1 (en) * 2007-03-31 2008-10-02 Thorp Tyler J Method for incorporating transistor snap-back protection in a level shifter circuit
US20080238523A1 (en) * 2007-03-31 2008-10-02 Thorp Tyler J Level shifter circuit incorporating transistor snap-back protection

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59214316A (en) * 1983-05-20 1984-12-04 Nec Corp Hysteresis circuit
JPH0419503Y2 (en) * 1984-10-31 1992-05-01
JPH0777346B2 (en) * 1988-12-28 1995-08-16 株式会社東芝 Logic level conversion circuit
JP2975122B2 (en) * 1990-12-26 1999-11-10 富士通株式会社 Level conversion circuit
JPH06204850A (en) * 1993-01-07 1994-07-22 Oki Electric Ind Co Ltd Level shifter circuit

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3550097A (en) * 1969-08-25 1970-12-22 Shell Oil Co Dc memory array
US3900746A (en) * 1974-05-03 1975-08-19 Ibm Voltage level conversion circuit
US3916430A (en) * 1973-03-14 1975-10-28 Rca Corp System for eliminating substrate bias effect in field effect transistor circuits
US3942043A (en) * 1973-01-02 1976-03-02 Fairchild Camera And Instrument Corporation Electronic watch
US4023050A (en) * 1976-05-10 1977-05-10 Gte Laboratories Incorporated Logic level converter
US4039862A (en) * 1976-01-19 1977-08-02 Rca Corporation Level shift circuit
US4045691A (en) * 1975-09-22 1977-08-30 Kabushiki Kaisha Daini Seikosha Level shift circuit
US4077031A (en) * 1976-08-23 1978-02-28 Texas Instruments Incorporated High speed address buffer for semiconductor memory
US4132904A (en) * 1977-07-28 1979-01-02 Hughes Aircraft Company Volatile/non-volatile logic latch circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2603704C3 (en) * 1976-01-31 1981-06-25 Deutsche Itt Industries Gmbh, 7800 Freiburg Monolithically integrated clock pulse shaper

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3550097A (en) * 1969-08-25 1970-12-22 Shell Oil Co Dc memory array
US3942043A (en) * 1973-01-02 1976-03-02 Fairchild Camera And Instrument Corporation Electronic watch
US3916430A (en) * 1973-03-14 1975-10-28 Rca Corp System for eliminating substrate bias effect in field effect transistor circuits
US3900746A (en) * 1974-05-03 1975-08-19 Ibm Voltage level conversion circuit
US4045691A (en) * 1975-09-22 1977-08-30 Kabushiki Kaisha Daini Seikosha Level shift circuit
US4039862A (en) * 1976-01-19 1977-08-02 Rca Corporation Level shift circuit
US4023050A (en) * 1976-05-10 1977-05-10 Gte Laboratories Incorporated Logic level converter
US4077031A (en) * 1976-08-23 1978-02-28 Texas Instruments Incorporated High speed address buffer for semiconductor memory
US4132904A (en) * 1977-07-28 1979-01-02 Hughes Aircraft Company Volatile/non-volatile logic latch circuit

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4318015A (en) * 1979-06-29 1982-03-02 Rca Corporation Level shift circuit
US4486670A (en) * 1982-01-19 1984-12-04 Intersil, Inc. Monolithic CMOS low power digital level shifter
US4490629A (en) * 1982-05-10 1984-12-25 American Microsystems, Inc. High voltage circuits in low voltage CMOS process
US4568844A (en) * 1983-02-17 1986-02-04 At&T Bell Laboratories Field effect transistor inverter-level shifter circuitry
US4864159A (en) * 1987-08-26 1989-09-05 U.S. Philips Corporation ECL to CMOS transition amplifier
US5243236A (en) * 1991-12-31 1993-09-07 Intel Corporation High voltage CMOS switch with protection against diffusion to well reverse junction breakdown
US5406141A (en) * 1992-07-06 1995-04-11 Sgs-Thomson Microelectronics, S.A. High voltage CMOS switching circuit
EP0600734A1 (en) * 1992-12-04 1994-06-08 Nec Corporation Level shifter
US5387828A (en) * 1992-12-04 1995-02-07 Nec Corporation High-speed level shifter with simple circuit arrangement
US5343094A (en) * 1993-01-13 1994-08-30 National Semiconductor Corporation Low noise logic amplifier with nondifferential to differential conversion
US5471149A (en) * 1993-09-27 1995-11-28 Sony Corporation High-speed large output amplitude voltage level shifting circuit
US5493244A (en) * 1994-01-13 1996-02-20 Atmel Corporation Breakdown protection circuit using high voltage detection
US6300796B1 (en) 1999-02-19 2001-10-09 Zilog, Inc. High voltage PMOS level shifter
US6580291B1 (en) 2000-12-18 2003-06-17 Cypress Semiconductor Corp. High voltage output buffer using low voltage transistors
US20070052297A1 (en) * 2003-07-28 2007-03-08 Hajime Nagai Voltage converter apparatus
US7545172B2 (en) * 2003-07-28 2009-06-09 Tpo Hong Kong Holding Limited Voltage converter apparatus
US20070063758A1 (en) * 2005-09-22 2007-03-22 Honeywell International Inc. Voltage divider and method for minimizing higher than rated voltages
US20080079708A1 (en) * 2006-10-03 2008-04-03 Abhishek Bandyopadhyay Low voltage driver for high voltage LCD
US8456463B2 (en) 2006-10-03 2013-06-04 Analog Devices, Inc. Low voltage driver for high voltage LCD
US20080238522A1 (en) * 2007-03-31 2008-10-02 Thorp Tyler J Method for incorporating transistor snap-back protection in a level shifter circuit
US20080238523A1 (en) * 2007-03-31 2008-10-02 Thorp Tyler J Level shifter circuit incorporating transistor snap-back protection
US7696805B2 (en) 2007-03-31 2010-04-13 Sandisk 3D Llc Level shifter circuit incorporating transistor snap-back protection
US7696804B2 (en) 2007-03-31 2010-04-13 Sandisk 3D Llc Method for incorporating transistor snap-back protection in a level shifter circuit

Also Published As

Publication number Publication date
DE2909388C3 (en) 1983-06-16
GB2016234B (en) 1982-04-28
GB2016234A (en) 1979-09-19
JPS5915216B2 (en) 1984-04-07
JPS54124964A (en) 1979-09-28
DE2909388A1 (en) 1979-09-13
DE2909388B2 (en) 1981-04-09

Similar Documents

Publication Publication Date Title
US4161663A (en) High voltage CMOS level shifter
KR930003557B1 (en) Transmission gate
US3675144A (en) Transmission gate and biasing circuits
KR910005604B1 (en) Interface circuit
US4947064A (en) Semiconductor device having a time delay function
US4039869A (en) Protection circuit
US3995172A (en) Enhancement-and depletion-type field effect transistors connected in parallel
US3551693A (en) Clock logic circuits
US4037114A (en) Tri-state logic circuit
US4453090A (en) MOS Field-effect capacitor
US4443715A (en) Driver circuit
JPS6471217A (en) Output buffer circuit
JPH024011A (en) Analog switch circuit
US4001606A (en) Electrical circuit
US4694430A (en) Logic controlled switch to alternate voltage sources
GB2198005A (en) Series-connected fet voltage equalisation
US4490632A (en) Noninverting amplifier circuit for one propagation delay complex logic gates
US4185209A (en) CMOS boolean logic circuit
US4945262A (en) Voltage limiter apparatus with inherent level shifting employing MOSFETs
US4232270A (en) High gain differential amplifier with positive feedback
KR900012440A (en) Analog signal input circuit
US4256974A (en) Metal oxide semiconductor (MOS) input circuit with hysteresis
US3970950A (en) High common mode rejection differential amplifier utilizing enhancement depletion field effect transistors
US4641046A (en) NOR gate with logical low output clamp
US4206418A (en) Circuit for limiting voltage differential in differential amplifiers