CN1295755C

CN1295755C - Method for forming grooved grid structure

Info

Publication number: CN1295755C
Application number: CNB2003101081915A
Authority: CN
Inventors: 许允埈
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2003-10-27
Filing date: 2003-10-27
Publication date: 2007-01-17
Anticipated expiration: 2023-10-27
Also published as: CN1612297A

Abstract

The present invention provides a method for forming a grooved gate structure. Firstly, a first conductive layer is formed on a semiconductor base with a first oxidizing layer; a part of the first conductive layer and a part of the first oxidizing layer are removed to form a first gate structure; a first gap wall is formed on the side wall of the first gate structure, and a second oxidizing layer is formed on the semiconductor base; another second conductive layer is formed on the surface of the second oxidizing layer, and the first gate structure and the second conductive layer above the first gate structure are then removed to form a second gate structure; a second gap wall is subsequently formed on the side wall of the second gate structure to complete the manufacturing process of the grooved gate structure. The method of the present invention can reduce the capacitance of the extending zone of the gate and a source electrode or a drain electrode, reduce the difficulty of the manufacturing process, and increase the control of the manufacturing process.

Description

A kind of method that forms notched gate structure

Technical field

The present invention relates to a kind of manufacture method of grid structure, particularly about the method for a kind of manufacturing groove grids (notched gate) structure.

Background technology

With regard to integrated circuit (IC) technology, dwindle the IC dimensions and be an important topic for a long time, the IC size of devices is more and more little, on limited area, design on the device faces the electric capacity that must reduce on the device, with the operating rate of boost device; In addition, owing to reduce the IC chip area higher manufacturing output can be arranged, so still continue to reduce the IC size.

In metal oxide semiconductor field effect transistor (MOSFET), when device dimensions shrink during to dozens of nanometer (nm), the parasitic capacitance of grid and source/drain extension area (extension) (parasitic capacitance) just becomes fairly obvious, has also therefore limited operating rate and the electrical quality of MOSFET; Then the someone proposes tool groove grids (notchedgate) structure, to reduce the generation of grid and source/drain extension area parasitic capacitance.But it is to utilize isotropic etching (isotropic etching) that existing formation has the method for groove grids profile, because when carrying out isotropic etching technology, because of the etch-rate of either direction all identical, therefore wayward required groove structure and size, thereby limited the lifting of semiconductor device yield and output.

Therefore, the conventional semiconductor manufacture craft is in that to face the device integrated level more and more high, under the more and more little situation of processing procedure live width, desire utilizes notched gate structure to reduce electric capacity between grid and source/drain extension area, to be difficult to control etched result in the manufacturing process, more can further influence the stability of device, will make that less semiconductor device is difficult to make, and reduce the rate of finished products and the electrical quality of device.

At above-mentioned shortcoming, at the disclosed application number of China Intellectual Property Office is that 99814159.3 patent documentation discloses a kind of transistor with groove grids, the present invention proposes a kind of method of different with it formation notched gate structure, effectively to overcome the shortcoming that is present in the prior art.

Summary of the invention

The purpose of this invention is to provide a kind of method that forms notched gate structure, it helps to increase the susceptibility of dopant ion and the form of silicon base at the implantation step that forms lightly doped drain (LDD).

Another object of the present invention provides a kind of method that forms notched gate structure, and it can reduce micro loading effect (microloading effect), to improve the repeatability of wafer to wafer (wafer to wafer) stability.

A further object of the present invention provides a kind of method that forms notched gate structure, and it can reduce the resistance value of automatic aligning metal silicide (salicide), and reduces the control difficulty in the manufacturing process and increase manufacturing process stability.

In order to solve the problems of the technologies described above, technical scheme of the present invention is: a kind of method that forms notched gate structure comprises: at first, provide the semiconductor-based end with first oxide layer, and form one first conductive layer on first oxide layer; Remove part first conductive layer and first oxide layer and form some first grid structures; Sidewall in the first grid structure forms first clearance wall, forms one second oxide layer again on the semiconductor-based end; Other has one second conductive layer to be formed at the described second oxide layer surface, removes second conductive layer of described first grid structure and top thereof then, to form a second grid structure; Then the sidewall in the second grid structure forms second clearance wall, to finish the manufacturing process of notched gate structure; Described second grid structure has short base and long top margin.

The present invention forms the method for notched gate structure, can be widely used in the semiconductor fabrication, on the semiconductor-based end, utilize two-period form to form grid structure and clearance wall structure, form at last final notched gate structure again, this notched gate structure can reduce the parasitic capacitance between polysilicon layer and source/drain extension area, and can reduce the resistance value of automatic aligning metal silicide (salicide), and reduce the control difficulty in the manufacturing process and increase manufacturing process stability, make it under the situation of device dimensions shrink, still can keep Devices Characteristics, promote the rate of finished products of product.

Description of drawings

Fig. 1 to Fig. 7 is respectively each step structure cutaway view that the present invention forms notched gate structure.

The figure number explanation:

The 10 semiconductor-based ends

12 first dielectric layers

14 first conductive layers

16 patterning photoresist layers

18 second dielectric layers

20 first clearance walls

22 the 3rd dielectric layers

24 second conductive layers

26 notched gate structure

28 second clearance walls

Embodiment

Below in conjunction with accompanying drawing the present invention is further described.

Fig. 1 to Fig. 7 is that preferred embodiment of the present invention is at each step structure cutaway view of making notched gate structure, as shown in the figure, manufacture method of the present invention includes the following step: at first, semiconductor substrate 10 is provided, be generally silicon base, as shown in Figure 1, utilize chemical vapour deposition technique to form one first dielectric layer 12 and one first conductive layer 14 in regular turn on surface, the semiconductor-based ends 10; This first conductive layer 14 is generally a polysilicon layer, and whether its thickness and can be selected will mix between 100 to 200 dusts (); First dielectric layer 12 is generally the silicon oxide layer that forms a silicon base surface, and its thickness is about 100 dusts.Wherein, be formed with suitable isolation structure or doped region (not shown) in the semiconductor-based end 10, as field oxide, shallow slot isolation structure or impure well etc., defining active area, and the existing production of integrated circuits technology of these structure utilizations is finished.

As shown in Figure 2, on first conductive layer 14, form a patterning photoresist layer 16, and be mask with this patterning photoresist layer 16, described first conductive layer 14 of part and first dielectric layer 12 are removed in etching, to form the temporary transient grid structure of being made up of remaining first conductive layer 14 and first dielectric layer 12.Wherein, the distance between this two adjacent temporary transient grid structure is represented with " L1 ".

Then, as shown in Figure 3, utilize chemical vapour deposition technique to form one second dielectric layer 18 again on a semiconductor-based end 10, silicon oxide layer for example is to cover described temporary transient grid structure top.Utilize etching technique again, remove second dielectric layer 18 of part, only stay part second dielectric layer 18 that is positioned at described temporary transient grid structure both sides, so that be formed with first clearance wall 20 as shown in Figure 4 in temporary transient grid structure 18 both sides, the distance that described two adjacent first clearance walls are 20 is represented with " L2 ".

As shown in Figure 5, other has one the 3rd dielectric layer 22 to form, silicon oxide layer for example, and it is covered in the surface of the semiconductor-based end 10, temporary transient grid structure and first clearance wall 20; And then form another second conductive layer 24 in the 3rd dielectric layer 22 surface depositions, polysilicon layer for example.

As shown in Figure 6, utilize photolithography techniques, described second conductive layer 24 of part and the 3rd dielectric layer 22 are removed in etching, and described some temporary transient grid structures, and then on the semiconductor-based end 10, form a notched gate structure 26, this notched gate structure 26 is made up of conductive layer 24, the 3rd dielectric layer 22 and first clearance wall 20, and between the adjacent two temporary transient grid structures of having removed.Specifically, the base of notched gate structure 26 contacted with the semiconductor-based end 10, and its length is with " L3 " expression, and the length on this contact base top margin L1 relatively is short.

Then, the pre-doping (pre-doping) that forms lightly doped drain (LDD) in the semiconductor-based end 10 is to utilize ion implantation to finish (not shown), and this implantation step that forms LDD helps to increase the susceptibility of heteroion and the form of silicon base.In addition, wafer can increase along with the minimizing of micro loading effect (microloading effect) the repeatability of wafer (wafer to wafer) stability.

As shown in Figure 7, utilize deposition and etching technique, form second clearance wall 28 respectively at the sidewall of notched gate structure 26.With this notched gate structure 26 and second clearance wall 28 is mask, and follow-up ion implantation step is carried out in semiconductor substrate 10, so that form source electrode and drain region (not shown) in the semiconductor-based end 10.At last, after the semiconductor device of finishing whole notched gate structure 26, can continue follow-up semiconductor fabrication process, as form automatic aligning metal silicide (salicide), to finish follow-up semiconductor structure.

Therefore, the present invention forms the method for notched gate structure, can be widely used in the semiconductor fabrication process, on the semiconductor-based end, utilize two-period form to form grid structure and clearance wall structure, form at last final notched gate structure again, this notched gate structure can reduce the parasitic capacitance between polysilicon layer and source/drain extension area, and can reduce the resistance value of automatic aligning metal silicide (salicide), and reduce the control difficulty in the manufacturing process and increase manufacturing process stability, make it under the situation of device dimensions shrink, still can keep Devices Characteristics, promote the rate of finished products of product.

Above-described embodiment only is used to illustrate technological thought of the present invention and characteristics, its purpose makes those skilled in the art can understand content of the present invention and is implementing according to this, therefore can not only limit claim of the present invention with present embodiment, be all equal variation or modifications of doing according to disclosed spirit, still drop in the claim of the present invention.

Claims

1, a kind of method that forms notched gate structure is characterized in that, comprising:

A semiconductor-based end, be provided, form one first oxide layer on it;

On described first oxide layer, form one first conductive layer;

Remove described first oxide layer of part and described first conductive layer, to form several first grid structures;

Sidewall in described some first grid structures forms first clearance wall respectively;

On the described semiconductor-based end, form one second oxide layer;

On described second oxide layer, form one second conductive layer;

Remove described some first grid structures and top described second conductive layer thereof, to form a second grid structure, described second grid structure is made up of described second conductive layer, described second oxide layer and described some first clearance walls;

And form one second clearance wall on the sidewall of this second grid structure.

2, a kind of method that forms notched gate structure according to claim 1 is characterized in that, described second grid structure is between the described two adjacent first grid structures of having removed.

3, a kind of method that forms notched gate structure according to claim 1 and 2 is characterized in that, the base of described second conductive layer of described second grid structure is less than top margin.

4, a kind of method that forms notched gate structure according to claim 1 and 2 is characterized in that, before the step that forms described second clearance wall, injects some first ions in the described semiconductor-based end, to form several lightly doped drains.

5, a kind of method that forms notched gate structure according to claim 1 and 2 is characterized in that, before the step that forms described second clearance wall, injects some second ions in the described semiconductor-based end, to form several source electrodes and drain region.

6, a kind of method that forms notched gate structure according to claim 1 and 2 is characterized in that, described first conductive layer is a polysilicon layer.

7, a kind of method that forms notched gate structure according to claim 1 and 2 is characterized in that, described second conductive layer is a polysilicon layer.

8, a kind of method that forms notched gate structure according to claim 1 is characterized in that, the step that forms described several first grid structures comprises the following steps:

On described first conductive layer, form a patterning photoresist layer;

With described patterning photoresist layer is mask, this conductive layer of etching and described first oxide layer; And

Remove described patterning photoresist layer.

9, a kind of method that forms notched gate structure according to claim 2 is characterized in that, the described semiconductor-based end is a silicon base.

10, a kind of method that forms notched gate structure according to claim 2 is characterized in that, described first clearance wall is made up of silica.

11, a kind of method that forms notched gate structure according to claim 2 is characterized in that, described second clearance wall is made up of silica.