CN1648751A - Liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

The present invention discloses a liquid crystal display device, wherein a scanning line generated by a transparent conductive layer and a metal layer lamination layer and a pixel electrode are formed at the same time, and a process of forming an opening part on a gate insulating layer and a process of striping a semiconductor layer are rationalized by introducing a halftone image exposure technology.

Description

Liquid crystal display device and manufacturing method thereof

technical field

The present invention relates to a liquid crystal display device having a color image display function, and more particularly, to an active type liquid crystal display device.

Background technique

In recent years, due to advances in microfabrication technology, liquid crystal material technology, and high-density packaging technology, liquid crystal display devices with a diagonal of 5 to 50 cm have been widely used in television images or various image displays by commercial standards. In addition, RGB colored layers are formed in advance on one of the two glass circuit boards that make up the liquid crystal panel, enabling color display to be easily realized. In particular, the built-in switch component in each pixel, that is, the active liquid crystal panel, can not only reduce low-order distortion, but also speed up the response speed and ensure high image contrast.

The above-mentioned liquid crystal display device (liquid crystal panel) generally has 200-1200 scanning lines and 300-1600 signal lines arranged in a matrix. Recently, in order to support the expansion of display capacity, large-screen and high-definition are being simultaneously pursued.

Fig. 7 shows the assembly state of the liquid crystal panel, adopts conductive adhesive, will provide the semiconductor integrated circuit chip 3 of drive signal, connect to the transparent insulating circuit board that constitutes one side of liquid crystal panel 1, for example on the glass circuit board 2 The COG (Chip-On-Glass) method of the formed scan line electrode terminal group 5 is based on a polyimide film resin film, using an appropriate adhesive containing a conductive medium, and copper with metal or solder plating. The TCP film 4 of the foil terminal is pressure-welded to the electrode terminal group 6 of the signal line, and an assembly method such as a fixed TCP (Tape-Carrier-Package) is used to provide an electrical signal to the image display unit. For the sake of explanation, the above-mentioned two assembly methods are shown in diagrams at the same time, but in fact, either method can be appropriately selected.

The wiring lines 7, 8 between the electrode terminals 5, 6, which are located approximately in the center of the liquid crystal panel 1 and connect the pixels, scanning lines, and signal lines in the display portion, need not be made of the same conductive material as the electrode terminal groups 5, 6. 9 is a transparent conductive opposite electrode commonly used in all liquid crystal cells, and an opposite glass circuit board or color filter of another sheet of transparent insulating circuit board on its opposite surface.

FIG. 8 shows an active liquid crystal display device in which an insulated gate type thin film transistor 10 is arranged according to each pixel, as an equivalent circuit diagram of a switch component, 11 (7 in FIG. 7 ) is a scanning line, 12 (7 in FIG. 7 ) 8) is a signal line, and 13 is a liquid crystal cell, and the liquid crystal cell 13 is used as an electrical capacitance component. Components drawn in solid lines will be formed on one glass circuit board 2 constituting the liquid crystal panel, and opposing electrodes 14 common to all liquid crystal cells 13 drawn in dotted lines will be formed on the opposite main plane of the other glass circuit board 9 form. When the OFF resistance of the insulated gate type thin film transistor 10 or the resistance of the liquid crystal cell 13 becomes low, or when the gray scale of the displayed image is emphasized, an auxiliary storage capacitor 15 can be applied side by side to the liquid crystal cell 13, etc., in the circuit Ingenuity is applied to expand the time constant of the liquid crystal cell 13 as a load, and 16 is a storage capacitor formed by the common bus of the storage capacitor 15 .

Fig. 9 shows the sectional view of the important parts of the image display part of the liquid crystal display device. The two glass circuit boards 2 and 9 constituting the liquid crystal panel 1 are formed on resinous fibers, hollow particles or color filters 9, spaced in a columnar shape. Spacers such as objects (not shown in the figure) are formed after maintaining a predetermined distance of several μm. Around the glass circuit board 9, a sealing material and a sealing material (not shown in any diagram) made of organic resin are used to seal it. The gap (Gap) forms a closed space, and the liquid crystal 17 is filled in the closed space.

When realizing color display, use any one or both of dyes or pigments called colored layer 18, and wrap an organic film with a thickness of about 1 to 2 μm in the closed space of the glass circuit board 9, and it will have a color display function. , the glass circuit board 9 at this time is the so-called color filter (Color Filter, CF for short). According to the properties of the liquid crystal material 17, the liquid crystal panel 1 can function as an electro-optical component after the polarizer 19 is pasted on either the upper surface of the glass circuit board 9 or the lower surface of the glass circuit board 2, or both surfaces. At present, most of the liquid crystal panels on the market use TN (Twist Nematic) liquid crystal materials, usually requiring two polarizers 19 . Although not shown in the figure, the transmissive liquid crystal panel is equipped with a back light source as a light source, and illuminates white light from below.

On the two glass circuit boards 2 and 9 to which the liquid crystal 17 is connected, a polyimide film-based resin film 20 with a thickness of about 0.1 μm is formed, which is an orientation film that determines the direction of the liquid crystal molecules. 21 is a drain (wiring) connecting the drain of the insulated gate thin film transistor 10 and the transparent conductive pixel electrode 22 , and is usually formed simultaneously with the signal line (source line) 12 . Located between the signal line 12 and the drain 21 is a semiconductor layer 23 , details will be described later. On the boundary of the colored layer 18 that is in contact with the color filter 9, a Cr film layer 24 with a thickness of about 0.1 μm is formed, which is a light-shielding component for preventing external light sources from irradiating the semiconductor layer 23, the scanning line 11, and the signal line 12. , which is the so-called black matrix frame (Black Matrix referred to as BM), which is a common technology at present.

The structure of an insulated gate type thin film transistor as a switching element and a related manufacturing method will be described below. At present, there are two types of insulated gate thin film transistors widely used, one of which is called the etch stop layer type, which will be explained in detail with the prior art. Fig. 10 is a plan view of a unit pixel of an active circuit board (semiconductor device for a display device) constituting a liquid crystal panel in the prior art, and a cross-sectional view on lines AA', BB' and CC' of Fig. 10(e) As shown in Fig. 11, the manufacturing process thereof will be briefly described below.

First, as shown in Figure 10(a) and Figure 11(a), a glass circuit board 2 with a thickness of about 0.5 to 1.1 mm is used as an insulating circuit with excellent heat resistance, chemical resistance and transparency. For example, on one main plane of the CORNING company/trade name 1737, use a vacuum film-forming device such as SPT (sputtering), coat the first metal layer with a film thickness of about 0.1-0.3 μm, and select The scan line 11 and the storage capacitor line 16 that also serve as the gate 11A are formed. After a comprehensive inspection of the material of the scanning line, it will be selected with heat resistance, chemical resistance, fluorine acid resistance and electrical conductivity. Generally, Cr, Ta, MoW alloy and other metals or alloys with excellent heat resistance are used.

In order to reduce the resistance value of the scanning line, it is reasonable to use AL (aluminum) as the material of the scanning line in order to reduce the resistance value of the LCD panel, but the heat resistance of the single AL is not good, so the above-mentioned heat-resistant metal Cr, Ta, Mo are either stacked with silicide, or an oxide layer (AL2O3) is applied on the surface of AL by anodic oxidation, which are generally used technologies at present. That is, the scanning line 11 is composed of more than one metal layer.

Secondly, on the overall glass circuit board 2, using a PCVD (plasma) device, for example, with a film thickness of about 0.3-0.05-0.1 μm, sequentially coat the first SiNx (silica gel suffocation) layer 30 that constitutes the gate insulating layer, And almost free of impurities, the first amorphous silica gel (A-Si) layer 31 is formed by the channel of the insulated gate type thin film transistor, and the second SiNx layer 32 and three kinds of thin film layers are formed by the insulating layer of the protection channel, such as As shown in FIG. 10(b) and FIG. 11(b), the width of the second SiNx layer on the gate 11A is selectively kept narrower than that of the gate 11A through microfabrication technology, so as to serve as a protective insulating layer (etch stop layer or channel protection layer) 32D, and expose the first amorphous silica gel layer 31 .

Next, use the same PCVD device to coat impurities such as the second amorphous silica gel layer 33 containing phosphorus with a film thickness of about 0.05 μm, as shown in Figure 10(c) and Figure 11(c), and use a vacuum such as SPT The film forming device is sequentially coated with a heat-resistant metal layer with a film thickness of about 0.1 μm, such as Ti, Cr, Mo and other film layers 34, and a low-resistance wiring layer, an AL film layer 35 with a film thickness of about 0.3 μm, and a thin film The thickness is about 0.1 μm, and the Ti thin film layer 36 as the intermediate conductive layer, through micro-fabrication technology, these three thin film layers 34A, 35A and 36A belonging to the source/drain wiring material, are laminated to selectively form an insulated gate The drain 21 of the thin film transistor and the signal line 12 as the source. Use the photosensitive resin pattern used to form the source/drain wiring as a mask plate, etch the Ti thin film layer 36, the Al thin film layer 35, and the Ti thin film layer 34 in sequence, and remove the gap between the source/drain electrodes 12 and 21. The second amorphous silica gel layer 33 is exposed to the protective insulating layer 32D. At the same time, the first amorphous silica gel layer 31 is also removed in other regions to expose the gate insulating layer 30, and the above selective pattern can be formed. In this way, under the second SiNx layer 32D where the channel protection layer exists, the second amorphous silica gel layer 33 will automatically finish etching, and this manufacturing method is called an etching stop layer type.

The source/drain electrodes 12 , 21 planarly overlap a part (several μm) of the protective insulating layer 32D in order to avoid structural deviation of the insulated gate type thin film transistor. This overlap will generate electrical effects with parasitic capacity. Although the smaller the better, it still needs to be determined according to the adjustment accuracy of the exposure machine, the accuracy of the mask board, the expansion coefficient of the glass circuit board, and the temperature of the glass circuit board during exposure. Practical The value of sex is about 2 μm.

After removing the above photosensitive resin pattern, on the overall glass circuit board 2, the gate insulating layer as a transparent insulating layer is also covered with a SiNx layer with a film thickness of about 0.3 μm as a passivation insulating layer 37 by using a PCVD device, as shown in the figure 10(d) and the passivation insulating layer 37 shown in FIG. 11(d), on the drain electrode 21 and in the area outside the image display portion, the area where the electrode terminals of the scanning line 11 and the signal line 12 are formed, will be formed separately. Openings 62, 63, 64, after removing the passivation insulating layer 37 and gate insulating layer 30 in the opening 63, part of the scanning line is exposed in the opening 63, and at the same time, the passivation in the opening 62, 64 is removed. The insulating layer 37 exposes part of the drain electrode 21 and part of the signal line. Similarly, openings 65 are formed on the storage capacitor lines 16 (electrode patterns bundled in parallel), exposing part of the storage capacitor lines 16 .

Finally, use a vacuum film-forming device such as SPT to coat a transparent conductive layer with a film thickness of about 0.1-0.2 μm, such as ITO (Indium-Tin-Oxide) or IZO (Indium-Zine-Oxide), as shown in Figure 10 ( e) As shown in FIG. 11( e ), pixel electrodes 22 are selectively formed on the passivation insulating layer 37 containing openings 62 after microfabrication technology, that is, the active circuit board 2 is completed. The part of the scanning line 11 exposed in the opening 63 is used as the electrode terminal 5, and the part of the signal line 12 exposed in the opening 64 can also be used as the electrode terminal 6. Electrode terminals 5A, 6A made of ITO are selectively formed on the passivation insulating layer 37, and a transparent conductive short-circuit line 40 connecting the electrode terminals 5A, 6A is usually formed at the same time. The reason is that, although not shown in the figure, the electrode terminals 5A, 6A and the short-circuit line 40 form long and thin strips and become high resistance, so it can be used as a high resistance for static electricity countermeasures. Similarly, although no number is assigned, the inclusion of the opening 65 forms an electrode terminal for the storage capacitor line 16 .

When the wiring resistance of the signal line 12 does not cause a problem, the low-resistance wiring layer 35 made of AL is not necessarily required. 12 and 21 can be simplified into a single layer. In this way, the most important thing is to use the heat-resistant metal layer for the source/drain wiring, and to ensure the electrical connection with the second amorphous silicon layer. Regarding the heat resistance of the insulated gate type thin film transistor, The prior art is described in detail in JP-A-7-74368. In addition, in FIG. 10(c), the storage capacitor line 16 and the drain electrode 21 pass through the gate insulating layer 30, and the storage capacitor 15 is formed by the plane overlapping region 50 (towards the downward oblique line), and details will be omitted here. illustrate.

Patent Document 1 JP-A-7-74368

Although the above description of the detailed processing process of 5 photomasks is omitted, due to the rationalization of the striping process of the semiconductor layer and the deletion of the contact point formation process, about 7 to 8 photomasks were originally required, and because of the dry etching technology The introduction, now reduced to 5 wafers, is expected to significantly reduce processing costs. In order to reduce the production cost of liquid crystal display devices, firstly, the processing cost of the active circuit board must be reduced, and secondly, the component cost must be reduced in the panel assembly process and module assembly process, which is also a well-known development goal. The method to reduce the processing cost includes shortening the process of cutting, developing low-cost processing or replacing the processing. The following is to make an active circuit board with 4 photomask boards, that is, use 4 photomask boards to process to reduce the cost. The prior art of the process is described. The 4-piece photomask processing is to delete the photo-etching process after introducing the halftone image exposure technology. Figure 12 is a unit pixel plan view of the active circuit board supporting the 4-piece photomask processing. Sectional views on lines A-A', BB' and CC'. As mentioned above, there are two types of insulated gate type thin film transistors generally used, and channel-etched type insulated gate type thin film transistors are used here.

First, as with the treatment of five photomasks, on one main plane of the glass circuit board 2, use a vacuum film forming device such as SPT to coat the first metal layer with a film thickness of about 0.1-0.3 μm, as shown in Figure 12(a) As shown in FIG. 13( a ), after microfabrication technology, the scanning line 11 and the storage capacitor line 16 serving as the gate 11A are selectively formed.

Next, on the whole glass circuit board 2, using a PCVD device, for example, with a film thickness of about 0.3-0.2-0.05 μm, the SiNx layer 30 that constitutes the gate insulating layer is sequentially covered, and it contains almost no impurities. The first amorphous silica gel layer 31 composed of channels of TFTs, the second amorphous silica gel layer 33 containing impurities and composed of source/drain electrodes of insulated gate TFTs, and three thin film layers. Next, using a vacuum film-forming device such as SPT, for example, use the Ti film layer 34 as a heat-resistant metal layer with a film thickness of about 0.1 μm, use the AL film layer 35 as a low-resistance wiring layer with a film thickness of about 0.3 μm, and use the Ti film layer 34 as a low-resistance wiring layer with a film thickness of about 0.3 μm. Layer 36 is an intermediate conductive layer with a film thickness of about 0.1 μm, which covers the source/drain wiring materials in sequence. After microfabrication technology, the drain 21 of the insulated gate type thin film transistor and the source electrode 21 are selectively formed. When forming such a selective pattern, the signal line 12 is formed through the halftone image exposure technique, as shown in Figure 12(b) and Figure 13(b), for example, the channel formation region 80B between the source/drain electrodes Line portion) film thickness is 1.5 μm, and rationally formed photosensitive resin patterns 80A, 80B are thinner than the film thickness (3 μm) of source/drain wiring formation regions 80A (12), 80A (21), This is the biggest feature of the 4-piece mask board.

In this case, when manufacturing circuit boards for liquid crystal display devices, the photosensitive resin patterns 80A and 80B usually use a general positive photoresist photosensitive resin, and the source/drain wiring formation region 80A is black, that is, a Cr film is formed. The channel area 80B is gray, such as the Cr pattern of Line And Space with a width of about 0.5-1 μm, and the other areas are white, that is, a mask plate with Cr film removed can be used. In the gray area, because the resolution of the exposure machine is not enough, it is impossible to analyze the fine line and space (Line And Space), and the light source from the display can penetrate about half of the mask plate to irradiate light, matching the characteristics of the remaining film of the positive photoresist photosensitive resin , as shown in FIG. 13(b), photosensitive resin patterns 80A, 80B having cross-sectional shapes can be obtained.

With above-mentioned photosensitive resin pattern 80A, 80B as photomask plate, as shown in Figure 13 (b), etch Ti thin film layer 36, Al thin film layer 35, Ti thin film layer 34, the second amorphous silica gel layer 33 and the first After an amorphous silica gel layer 31 is exposed and the gate insulating layer 30 is exposed, as shown in Figure 12(c) and Figure 13(c), in the ashing mode such as oxygen plasma, when the photosensitive resin pattern 80A, 80B If the thickness of the film is reduced by more than 1.5 μm, the photosensitive resin pattern 80B will disappear and the channel area will be exposed. At the same time, only 80C (12) and 80C (21) can be directly left in the source/drain wiring formation area. Then use the photosensitive resin pattern 80C (12) and 80C (21) with reduced film thickness as the mask plate, etch the Ti thin film layer, Al thin film layer, Ti The thin film layer, the second amorphous silica gel layer 33A, and the first amorphous silica gel layer 31A are etched after leaving the first amorphous silica gel layer 31A at about 0.05-0.1 μm. After the metal layer is etched, the first amorphous silica gel layer 31A remains about 0.05-0.1 μm for etching to form the source/drain wiring. The insulated gate type thin film transistor obtained by this manufacturing method is generally called a channel. Etching type. In the above-mentioned oxygen plasma treatment, it is better to strengthen the anisotropy, so as to effectively suppress the variation of the pattern size, and the reason will be described later.

After removing the photosensitive resin patterns 80C(12) and 80C(21), the process is the same as that of the five photomask boards, as shown in Figure 12(d) and Figure 13(d), on the integral glass circuit board 2, wrap Cover the second SiNx layer with a transparent insulating layer film thickness of about 0.3 μm, as a passivation insulating layer 37, on the drain electrode 21, on the scanning line 11 in the area outside the image display part, and the electrode terminal area formed by the signal line 12 , forming openings 62, 63, 64 respectively, after removing the passivation insulating layer 37 in the opening 63 to connect with the gate insulating layer 30, a part of the scanning line is exposed in the opening 63, and at the same time, removing the opening 62, 64 The passivation insulating layer 37 exposes part of the drain electrode 21 in the opening 62 and part of the signal line in the opening 64 . After the opening 65 is formed on the storage capacitor line 16 , a part of the storage capacitor line 16 is exposed.

Finally, use a vacuum film-forming device such as SPT to cover a transparent conductive layer with a film thickness of about 0.1-0.2 μm, such as ITO or IZO, as shown in Figure 12(e) and Figure 13(e), after fine processing technology After selectively forming the transparent conductive pixel electrodes 22 including the openings 62 on the passivation insulating layer 37 , the active circuit board 2 is completed. Regarding the electrode terminals, transparent conductive electrode terminals 5A and 6A made of ITO are selectively formed on the passivation insulating layer 37 including the openings 63 and 64 at this stage.

In this kind of 5-piece photomask processing and 4-piece photomask processing, the formation process of the scanning line 11 at the contact point of the drain electrode 21 is also carried out at the same time. Therefore, the thickness of the insulating layer in the openings 62, 63 and There are different types. Compared with the gate insulating layer 30, the film-forming temperature of the passivation insulating layer 37 is not only low but also of poor quality. When using fluorine-fluorine acid etching solution for etching, the etching speeds differ by several 1000/min, several 100/min or even One digit, plus the cross-sectional shape of the opening 62 on the drain 21, the pore diameter cannot be controlled due to excessive etching, so dry etching with fluorine-based gas is used.

Even if dry etching is used, the opening 62 on the drain 21 only has the passivation insulating layer 37, so compared with the opening 63 on the scanning line 11, it is difficult to avoid excessive etching. The intermediate conductive layer 36A) is reduced in film thickness due to etching gas. In addition, when the photosensitive resin pattern is removed after etching, it is first treated with oxygen plasma ashing to remove the fluorinated surface polymer, and the surface of the photosensitive resin pattern is deleted by about 0.1-0.3 μm, and then organic stripping is used Liquid, such as Tokyo Ohka’s stripping liquid 106, etc., is treated with a chemical solution. Although this is a common treatment method, when the thickness of the middle conductive layer 36A is reduced and the underlying aluminum layer 35A is exposed, after oxygen After the plasma ashing treatment, Al 2 O 3 , which is an insulator, is formed on the surface of the aluminum layer 35A, and a good resistive contact point with the pixel electrode 22 cannot be obtained. Therefore, in order to reduce the film thickness of the intermediate conductive layer 36A and not be affected, the film thickness is firstly set at 0.2 μm, so as to avoid the above-mentioned problems. Alternatively, when the openings 62-65 are formed, the aluminum layer 35A may be removed to expose the Ti thin film layer 34A of the underlying heat-resistant metal layer, and then avoidance measures such as forming the pixel electrode 22 may be taken. This has the advantage that the intermediate conductive layer 36A is not required in the first place.

However, if the in-plane thickness of the film is not uniform, the countermeasures in the preceding paragraph may not be effective. In addition, the same is true if the in-plane uniformity of the etching rate is poor. Although the latter countermeasure does not require the intermediate conductive layer 36A, when the removal process of the aluminum layer 35A is added, or the cross-section control of the opening 62 is insufficient, the pixel electrode 22 is likely to be segmented.

The channel formation process applied to the 4-sheet photomask process is to selectively remove the source/drain wiring material between the source/drain wiring 12 and 21 and the semiconductor layer containing impurities, so it is also serious The process of affecting the ON characteristics of insulated gate thin film transistors to determine the channel length (the current mass product is 4 to 6 μm). The change of this channel length will also greatly change the ON current value of the insulated gate type thin film transistor. Although strict manufacturing management is usually required, the channel length, that is, the pattern size of the halftone image exposure area, will affect the exposure ( The intensity of the light source and the graphic accuracy of the mask plate, especially the line and space size (Line And Space size), the coating thickness of the photosensitive resin, the imaging treatment of the photosensitive resin, and the reduction of the photosensitive resin film on the etching process, etc. Coupled with the combination of the in-plane equality of the above-mentioned quantities, it may not be possible to achieve high yield and stable production, so stricter manufacturing management is required than in the past, but from the current situation, it has not yet reached a high level. Especially 6μm Below the channel length, due to the reduction of the film thickness of the photoresist pattern, the pattern size tends to be seriously affected.

In view of the related status quo, the present invention can not only avoid the lack of contact point formation in the past 5-piece photomask processing or 4-piece photomask processing, but also achieve deletion by using the halftone image exposure technology with a large manufacturing volume. Goals of the manufacturing process. In addition, to realize the low price of liquid crystal panels, in line with the increase in demand, further actively pursue the reduction of the number of manufacturing processes, simplify other main manufacturing processes, or introduce low-cost technologies, so that the value of the present invention will be even greater. promote.

First, the present invention applies the rationalized formation process of the pixel electrode disclosed in the prior art Japanese Patent Application No. Hei 5-268726 to the present invention, and further achieves the purpose of reducing the manufacturing process. Secondly, the halftone image exposure technology is applied to the forming process of the semiconductor layer and the contact point forming process for the scanning line, which is easy to manage the pattern accuracy, and further realizes the purpose of reducing the manufacturing process. Based on the purpose of applying a passivation function to the source/drain wiring of an insulated gate type thin film transistor, the photosensitive organic insulating layer disclosed in the prior art Japanese Patent Application Laid-Open No. 2-275925 adopts the method of forming the source/drain Wiring photosensitive resin, or according to the content disclosed in JP-A-2-216129, on the surface of the source/drain wiring made of aluminum, the anodic oxidation technology that fuses and forms an insulating layer to realize the rationalization of processing with hypothermia. Next, in order to further cut out the process, the halftone image exposure technique is also applied to the anodic oxide layer formation of the source/drain wiring, and the protective layer formation process of the electrode terminal is rationalized.

Patent Document 1 JP-A-5-268726

Patent Document 2 Japanese Unexamined Patent Publication No. 2-275925

Patent Document 3 Japanese Unexamined Patent Publication No. 2-216129

Contents of the invention

According to one aspect of the present invention, there is provided a liquid crystal display device, which has at least an insulated gate type thin film transistor, a scan line as the gate of the above insulated gate type thin film transistor, and a source wiring The unit pixel composed of the signal line and the pixel electrode connected to the drain wiring includes a first transparent insulating circuit board in which the unit pixels are arranged in a two-dimensional matrix, and the first transparent insulating circuit board opposite to the above-mentioned Liquid crystals are filled between the second transparent insulating circuit board or the color filter, and the feature is: at least on one main plane of the first transparent insulating circuit board, the first metal layer of the transparent conductive layer is laminated to form a scanning line, And form a transparent conductive pixel electrode, the same transparent conductive signal line electrode terminal as the area outside the image display part, on the gate, through the plasma protection layer and the gate insulating layer, the second impurity-free The semiconductor layer is formed into stripes. On the above-mentioned first semiconductor layer, a protective insulating layer narrower than the gate is formed. On the above-mentioned pixel electrode, on the electrode terminal of the signal line, and in the area outside the image display part, belong to the scanning area. The plasma protection layer and the gate insulating layer on the scanning line electrode terminals of the scanning line will form openings, and the pixel electrodes, the electrode terminals of the scanning lines and the electrode terminals of the signal lines are exposed in each opening. On a part and on the first semiconductor layer, a pair of second semiconductor layers containing impurities are formed by the source/drain of the insulated gate type thin film transistor, on the gate insulating layer, on the second semiconductor layer and on the part of the signal line On the electrode terminal, the source (signal line) wiring is composed of more than one layer of heat-resistant metal layer, and also on the gate insulating layer, on the second semiconductor layer, and on some pixel electrodes in the above-mentioned opening. The drain wiring is characterized in that a photosensitive organic insulating layer is formed on the above-mentioned source/drain wiring.

With this structure, since the transparent conductive pixel electrodes are formed at the same time as the scanning lines, they are formed on the glass circuit board. In addition, since the insulated gate thin film transistor is an etch stop layer type, after the protective insulating layer is formed on the channel, a photosensitive organic insulating layer will be formed on the source/drain wiring, and the active circuit board will be given a passivation function. After that, a TN type liquid crystal display device with transparent conductive electrode terminals can be obtained.

According to another aspect of the present invention, a liquid crystal display device is provided, which is also characterized in that: at least on one main plane of the first transparent insulating circuit board, the first metal layer of the transparent conductive layer is laminated to form a scanning line, and the first metal layer is formed The transparent conductive pixel electrode (the same as the area outside the image display part, the transparent conductive signal line electrode terminal), on the gate, passes through the plasma protective layer and the gate insulating layer, and is made of the first impurity-free The semiconductor layer is formed into stripes. On the above-mentioned first semiconductor layer, a protective insulating layer narrower than the gate is formed. Openings will be formed on the plasma protection layer on the electrode terminals of the signal line and on the electrode terminals of the signal line, and on the gate insulating layer, and the transparent conductive pixel electrodes and part of the transparent conductive scanning lines (or scanning lines) will be exposed in each opening. It is the electrode terminal of the scanning line and the electrode terminal of the signal line), on the part of the above-mentioned protective insulating layer and on the first semiconductor layer, a pair of second electrodes containing impurities are formed by the source/drain of the insulated gate type thin film transistor. On the semiconductor layer, on the gate insulating layer and on the second semiconductor layer (and on some signal line electrode terminals), the source (signal line) wiring is composed of more than one layer of heat-resistant metal layer, and on the gate On the insulating layer, on the first semiconductor layer, and on part of the pixel electrodes in the above-mentioned openings, also including a part of the drain wiring and the scanning line, an electrode terminal (or a transparent conductive scanning line electrode terminal) of the scanning line is formed. A signal line electrode terminal (or a transparent conductive signal line electrode terminal) formed with a part of the signal line is characterized in that a photosensitive organic insulating layer is formed on the signal line except for the electrode terminal of the above signal line.

With this structure, since the transparent conductive pixel electrodes are formed simultaneously with the scanning lines, they are formed on the glass circuit board. In addition, since the insulated gate thin film transistor is an etch stop layer type, after the protective insulating layer is formed on the channel, a photosensitive organic insulating layer will be formed on the signal line, and the active circuit board will be given a minimum passivation function, that is, A TN-type liquid crystal display device can be obtained, and the electrode terminals can be either transparent conductive or metallic.

According to another aspect of the present invention, a liquid crystal display device is provided, which is also characterized in that: at least on one main plane of the first transparent insulating circuit board, a scanning line formed by laminating the transparent conductive layer and the first metal layer is formed, And the transparent conductive pixel electrode (the same as the area outside the image display part, which is a transparent conductive signal line electrode terminal), on the gate, through the plasma protection layer and the gate insulating layer, made of impurity-free The first semiconductor layer is formed in a stripe shape, and on the first semiconductor layer, a protective insulating layer narrower than the gate is formed. The plasma protective layer on the electrode terminals of the scanning lines and the electrode terminals of the signal lines) will form openings with the gate insulating layer, and the transparent conductive pixel electrodes and part of the transparent conductive scanning lines (or scanning lines) are exposed in each opening. is the electrode terminal of the scanning line and the electrode terminal of the signal line), on a part of the above-mentioned protective insulating layer and on the first semiconductor layer, a pair of second impurity-containing electrodes is formed by the source/drain of the insulated gate type thin film transistor. On the semiconductor layer, on the gate insulating layer and the second semiconductor layer (and on some signal line electrode terminals), the source (signal line) is composed of more than one heat-resistant metal layer and a metal layer that can be anodized Wiring, and on the gate insulating layer, on the first semiconductor layer and on part of the pixel electrodes in the above-mentioned opening, also including a part of the drain wiring and the above-mentioned scanning line, forming the electrode terminal (or transparent) of the scanning line Conductive scanning line electrode terminals) and signal line electrode terminals (or transparent conductive signal line electrode terminals) composed of part of the signal line are characterized in that, except for the above electrode terminals, the source/drain wiring An anodized layer is formed on the surface.

With this structure, the transparent conductive pixel electrodes are formed simultaneously with the scanning lines, so they are formed on the glass circuit board. In addition, since the insulated gate thin film transistor is an etch stop layer type, when the protective insulating layer is formed on the channel, at least on the surface of the signal line, an insulating anodized layer of tantalum pentoxide (Ta2O5) or tantalum oxide will be formed. aluminum (Al2O3), a TN-type liquid crystal display device with a passivation function can be obtained. Although the electrode terminals can be either transparent conductive or metallic, the metallic electrode terminals have less restrictions on handling.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, which is characterized in that: by means of halftone image exposure technology, the process of using a photomask to form scanning lines and pixel electrodes, and the process of forming a protective insulating layer process, and with the help of half-tone image exposure technology, use a photomask plate to process the electrode terminals of the scanning line and the electrode terminals of the signal line to form contact points with the pixel electrodes to form a process with the semiconductor layer on the gate, and use photosensitive organic insulating layer to form source/drain wiring.

With this structure, one photomask can be used to process the forming process of the scanning line and the forming process of the pixel electrode, so as to achieve the purpose of reducing the number of photo-etching processes. Therefore, a photomask plate is used to process the contact point and the semiconductor layer to achieve the purpose of reducing the number of photo-etching processes, and the photosensitive organic insulating layer used in the formation of the source/drain wiring can be directly retained instead of It is necessary to form a passivation insulating layer. In addition to reducing the manufacturing process, four photomasks can also be used to manufacture a TN-type liquid crystal display device with transparent conductive electrode terminals.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, which is characterized in that by means of halftone image exposure technology, the process of using a photomask to form scanning lines and pixel electrodes, and the process of forming a protective insulating layer , and with the help of halftone image exposure technology, use a mask plate to process the electrode terminals of the scanning lines and the electrode terminals of the signal lines to form contact points with the pixel electrodes, so as to form a process with the semiconductor layer on the gate, and at the same time use halftone Image exposure technology, the process of using a photosensitive organic insulating layer to form source/drain wiring, and only retaining the photosensitive organic insulating layer on the signal line.

With this structure, one photomask can be used to process the forming process of the scanning line and the forming process of the pixel electrode, so as to achieve the purpose of reducing the number of photo-etching processes. Therefore, a photomask plate is used to process the contact point and the semiconductor layer to achieve the purpose of reducing the number of photo-etching processes. When the source/drain wiring is formed, the half-tone image exposure technology is used. On the signal line, only selective The photosensitive organic insulating layer is kept, and the formation of the passivation insulating layer is no longer required. In addition to reducing the manufacturing process, only four photomask plates can be used to manufacture the TN type liquid crystal display device.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, which is characterized in that by means of halftone image exposure technology, the process of using a photomask to form scanning lines and pixel electrodes, and the process of forming a protective insulating layer , and with the help of halftone image exposure technology, use a mask plate to process the electrode terminals of the scanning lines and the electrode terminals of the signal lines to form contact points with the pixel electrodes to form a process with the semiconductor layer on the gate, while using a halftone image Exposure technology, a process in which source/drain wiring is formed and only the source/drain wiring is anodized.

With this structure, one photomask can be used to process the forming process of the scanning line and the forming process of the pixel electrode, so as to achieve the purpose of reducing the number of photo-etching processes. Therefore, a photomask is used to process the contact point and the semiconductor layer to achieve the purpose of reducing the number of photo-etching processes. When the source/drain wiring is formed, the half-tone image exposure technology is used to form the source/drain wiring. The anodic oxidation layer is selectively formed on the line, so that the formation of a passivation insulating layer is no longer required. In addition to reducing the manufacturing process, only four photomasks can be used to manufacture a TN-type liquid crystal display device.

As mentioned above, the present invention is mainly aimed at the insulated gate type thin film transistor using the etching stop layer type, and takes the rationalization technology of processing the scanning line and the pixel electrode with a photomask as the core, and proposes various active circuit boards according to this structure. scheme. In the liquid crystal display device described in the present invention, since the channel of the insulated gate type thin film transistor is provided with a protective insulating layer, the electrode terminals formed except for the image display part have only the source/drain wiring or only the signal line. A photosensitive organic insulating layer will be selectively formed on it to have a passivation function. Therefore, no special heating process is required, and the insulated gate type TFT with the amorphous silica gel layer as the semiconductor layer does not need to have high heat resistance. That is to say, the additional effect of avoiding damage to electrical properties can be achieved by forming passivation.

In a part of the liquid crystal display device described in the present invention, a protective insulating layer is also provided on the channel of the insulated gate type thin film transistor, and the source/drain wiring formed by the source/drain wiring material that can be anodized is formed. Anodizing can have a passivation function, and it does not need to have too high heat resistance. In addition, when the source/drain wiring is anodized, the introduction of halftone image exposure technology can selectively protect the electrode terminals of the scanning line or signal line, and can obtain the effect of preventing the increase in the number of photo-etching processes.

In addition, after the halftone image exposure technology is introduced, the striping process of the semiconductor layer and the forming process of the opening to the gate insulating layer can be processed on the same mask plate. In addition to eliminating the process, it can also reduce the number of photo-etching processes. . The liquid crystal display device can be manufactured by using four photomask plates and according to a manufacturing method different from the past, which greatly contributes to reducing the cost of the liquid crystal display device. Furthermore, the above-mentioned process does not require high graphics accuracy, so it will not have a great impact on the yield rate or quality, and it is easy to control production management.

According to the above description, the essentials of the present invention can be clearly understood, and the key point is that when forming scanning lines and pixel electrodes, by means of half-tone image exposure technology, between the transparent conductive layer and the metal thin film layer for scanning lines, the simulation of stacking There is an opening on the pixel electrode, and the film thickness of the region where the semiconductor layer is formed on the gate will form a photosensitive resin pattern thicker than other regions, using the photosensitive resin pattern as a mask plate to expose the pixel electrode in the opening, and Reduce the film thickness of the above-mentioned photosensitive resin pattern and expose the semiconductor layer, use the photosensitive resin pattern showing the film thickness as a mask plate, and form a semiconductor layer on the grid, that is, one piece of photomask plate can handle the formation of the semiconductor layer and the contact point, except Other structures, including liquid crystal display devices with completely different materials or film thicknesses such as scanning lines, signal lines, pixel electrodes, and gate insulating layers, or differences in their manufacturing methods, are not difficult to understand. In addition, the scope of the present invention can be more determined that the semiconductor layer of the insulated gate type thin film transistor is not limited to amorphous silica gel.

Description of drawings

Fig. 1 is the plan view according to the active circuit board of embodiment 1 of the present invention;

2 is a sectional view of the manufacturing process of the active circuit board according to Embodiment 1 of the present invention;

3 is a plan view of an active circuit board according to Embodiment 2 of the present invention;

4 is a cross-sectional view of the manufacturing process of the active circuit board according to Embodiment 2 of the present invention;

5 is a plan view of an active circuit board according to Embodiment 3 of the present invention;

6 is a cross-sectional view of the manufacturing process of the active circuit board according to Embodiment 3 of the present invention;

Fig. 7 is a perspective view illustrating an assembled state of a liquid crystal panel;

8 is an equivalent circuit diagram of a liquid crystal panel;

9 is a cross-sectional view of a liquid crystal panel in the prior art;

Fig. 10 is the plan view of active circuit board of prior art;

Fig. 11 is a sectional view of the manufacturing process of the active circuit board of the prior art;

Figure 12 is a plan view of the active circuit board after rationalization; and

Fig. 13 is a cross-sectional view of the manufacturing process of the active circuit board after rationalization.

Symbol Description

1: LCD panel

2: Active circuit board (glass circuit board)

3: Semiconductor integrated circuit chip

4: TCP film

5: A part of the metallic scanning line or an electrode terminal

5A: A part of a transparent conductive scanning line or an electrode terminal

6: A part of a metallic signal line or an electrode terminal

6A: A part of a transparent conductive signal line or an electrode terminal

9: Color filter (opposite glass circuit board)

10: Insulated gate thin film transistor

11: scan line

11A: Gate wiring, gate

12: Signal line (source wiring, source)

16: storage capacitor line

17: LCD

19: polarizer

20: Orientation film

21: Drain (drain wiring, drain)

22: Transparent conductive pixel electrode

30: Gate insulating layer

31: (first) amorphous silica gel layer free of impurities

32D: Protective insulating layer (etch stop layer, channel protective insulating layer)

33: (second) amorphous silica gel layer containing impurities

34: (can be anodized) heat-resistant metal layer

35: (can be anodized) low resistance metal layer (AL)

36: middle conductive layer

37: passivation insulating layer

50, 52: storage capacitor formation area

62: opening (on the drain)

63, 63A: openings (on part of scanning lines or electrode terminals of scanning lines)

64, 64A: Opening (on part of the signal line or on the electrode terminal of the signal line)

65: opening (on the counter electrode)

68: Anodized layer (titanium oxide, TiO2)

69: Anodized layer (aluminum oxide, Al2O3)

71: Plasma Shield

72: accumulation electrode

74: opening (on the pixel electrode)

82A, 82B, 87A, 87B:

(formed by halftone image exposure) photosensitive resin pattern

85: Photosensitive organic insulating layer graphics

86A, 86B: photosensitive organic insulating layer patterns (formed by halftone image exposure)

91: transparent conductive layer

92: first metal layer

Detailed ways

Embodiments of the present invention will be described below with reference to FIGS. 1 to 6 . FIG. 1 shows a plan view of a semiconductor device (active circuit board) for a display device according to Embodiment 1 of the present invention, and FIG. 2 shows the AA' line, BB' line, and CC' line of FIG. 1(e) A cutaway view of the manufacturing process in-line. Similarly, FIG. 3 and FIG. 4 of Embodiment 2, and FIG. 5 and FIG. 6 of Embodiment 3 represent the plan view of the active circuit board and the cross-sectional view of the manufacturing process, respectively. The same reference numerals are assigned to the same parts as those in the prior art, and detailed explanations are omitted.

Example 1

Embodiment 1, firstly, on a main plane of the glass circuit board 2, adopt a vacuum film-forming device such as SPT to cover a transparent conductive layer 91 with a film thickness of about 0.1-0.2 μm, such as ITO), and a film with a thickness of about 0.1 μm. The first metal layer 92 is 0.1-0.3 μm, such as Cr, Ta, MoW alloy, etc. Due to the low resistance of the scanning line, in order to avoid the battery reaction caused by ITO and alkaline developer or photoresist stripper, the heat-resistant metal layer can also be laminated aluminum or aluminum alloy containing Nd.

Next, as shown in FIG. 1(A) and FIG. 2(A), the first metal layer 92 and the transparent conductive layer 91 are sequentially etched through microfabrication technology to expose the glass circuit board 2, and the transparent conductive layer 91A is selectively formed. Laminated with the first metal layer 92A to form the scanning line 11 of the gate 11A and the dummy electrode terminal 94 of the scanning line, and the dummy pixel electrode 93 formed by laminating the transparent conductive layer 91B and the first metal layer 92B, and the transparent conductive layer 91C and the dummy electrode terminal 94 of the scanning line. The dummy electrode terminal 95 of the signal line formed by stacking the first metal layer 92C. Through the gate insulating layer, the insulation withstand voltage of the scanning line and the signal line is increased. In order to improve the yield rate, the above electrodes are preferably dry-etched to suppress the taper of the cross-sectional shape.

Next, on the whole glass circuit board 2 , a transparent insulating layer such as TaOx or SiO2 is coated as a plasma protection layer 71 with a film thickness of about 0.1 μm. This plasma protection layer 71 will reduce the transparent conductive layer 91A exposed at both ends of the scanning line 11 through the subsequent PCVD device during the SiNx film formation of the gate insulating layer, thereby affecting the film quality of SiNx, so It is necessary to pass through the gate insulating layer to prevent the insulation withstand voltage between the scan line and the signal line from being lowered. For details, please refer to the prior example Japanese Patent Laid-Open No. 59-9962.

Patent Citation 4 JP-A-59-9962

After coating the plasma protection layer 71, use the PCVD device as in the prior art, for example, the first SiNx layer 30, which is composed of a gate insulating layer with a film thickness of about 0.2-0.05-0.1 μm, is almost free of impurities and The first amorphous silica gel layer 31 composed of the channel of the insulated gate type thin film transistor, the second SiNx layer 32 which protects the channel and constitutes an insulating layer, and three thin film layers. Here, since the gate insulating layer, the plasma protection layer 71 and the first SiNx layer 30 are stacked, the thickness of the first SiNx layer 30 is formed thinner than before, which has an excellent auxiliary effect.

Through microfabrication technology, as shown in FIG. 1(b) and FIG. 2(b), the second SiNx layer on the gate 11A, which is thinner than the gate 11A, is selectively reserved, and the first amorphous silica gel layer 31 is exposed as Protective insulating layer 32D.

Then, after using the PCVD device, the whole glass circuit board 2 is coated with impurities with a film thickness of about 0.05 μm, such as the phosphorus-containing second amorphous silica gel layer 33, and there are openings on the dummy pixel electrodes 93 respectively. 74, an opening 63A is provided on the dummy electrode terminal 94 of the scanning line outside the image display section, and an opening 64A is provided on the dummy electrode terminal 95 of the signal line. , assuming that the film thickness of the semiconductor layer forming region, that is, the region 82A on the gate 11A is 2 μm, which is 1 μm thicker than the other region 82B, and the photosensitive resin patterns 82A, 82B are formed by halftone image exposure technology. Next, use the photosensitive resin patterns 82A, 82B as a mask plate, as shown in Fig. 1(c) and Fig. 2(c), including the second amorphous silica gel layer 33 and the first amorphous silica gel layer in the opening. 31. The gate insulating layer 30 and the plasma protection layer 71 also etch the first metal layers 92A-92C sequentially to expose the electrode terminal 5A of the scanning line 11, the pixel electrode 22 and the electrode terminal 6A of the signal line respectively.

Then use an ashing method such as oxygen plasma to reduce the film thickness of the above-mentioned photosensitive resin patterns 82A and 82B by more than 1 μm. After the photosensitive resin patterns 82B disappear and expose the second amorphous silica gel layer 33B, the semiconductor layer can be formed. On the area, only the photosensitive resin pattern 82C of reduced film thickness remains. The photosensitive resin pattern 82C corresponds to the semiconductor layer forming region, and even if the size of the etch stop layer type IGTFT is changed, the electrical characteristics of the IGTFT will not be affected, and the handling and management are very simple. Furthermore, as shown in FIG. 1(d) and FIG. 2(d), the photosensitive resin pattern 82C is used as a mask plate to selectively etch the second amorphous silica gel layer 33B and the first amorphous silica gel layer 31B. Striped semiconductor layers 33A, 31A having a pattern width thicker than the gate 11A are formed on the gate 11A, and the gate insulating layer 30A is exposed. At this time, the transparent conductive scanning line electrode terminal 5A, the signal line electrode terminal 6A and the pixel electrode 22 exposed in the above-mentioned openings 63A, 64A, and 74 are exposed on the second and first amorphous silica gel layers. Among the etching gases of 33A and 31A, the fluorine-based etching gas does not reduce the film thickness of these transparent conductive layers, or adversely affect the resistance value and transparency, so the structural morphology is very good.

After removing the above-mentioned photosensitive resin pattern 82C, in the process of forming the source/drain wiring, use a vacuum film-forming device such as SPT to coat a heat-resistant metal layer with a film thickness of about 0.1 μm, such as a thin film layer 34 such as Ti and Ta. , and the AL film layer 35 of the low-resistance wiring layer with a film thickness of about 0.3 μm. Next, through microfabrication technology, use photosensitive organic insulating layer patterns 85(12) and 85(21) with a film thickness of about 1-2 μm to sequentially etch the source/drain wiring material composed of two layers of film, the second The amorphous silica gel layer 33A and the first amorphous silica gel layer 31A expose the gate insulating layer 30A and the protective insulating layer 32D, as shown in FIGS. A part of the pixel electrode 22 is selectively formed by laminating 34A and 35A to form the drain 21 of the insulated gate type thin film transistor, and a part of the electrode terminal 6A including the signal line and the signal line 12 also serving as the source. In this way, the transparent conductive electrode terminals 5A and 6A are exposed on the glass circuit board 2 after the source/drain wiring 12 and 21 are etched. In addition, in terms of the structure of the source/drain wiring 12, 21, Ta, Cr, MoW, etc. can be simplified to a single layer as long as the restriction on the resistance value is relaxed.

After pasting the color filter on the active circuit board 2 manufactured through the above steps, it becomes a liquid crystal panel, and the first embodiment of the present invention is also completed. According to Embodiment 1, since the photosensitive organic insulating layer pattern 85 will contact the liquid crystal, the photosensitive organic insulating layer is mainly composed of thermoplastic phenolic resin instead of general photosensitive resin. Not only is the purity high, but the main component contains acrylic resin or polyimide film resin. The most important thing is to use a photosensitive organic insulating layer with high heat resistance. In terms of structure, the material can be heated to make it flow and then cover the source. The side surfaces of the electrode/drain wiring 12, 21. At this time, the stability of the liquid crystal panel is bound to be greatly improved. Regarding the structure of the storage capacitor 15, as shown in FIG. 1(e), although it is illustrated in the figure that the storage electrode 72 containing a part of the pixel electrode 22 is formed simultaneously with the source/drain wiring 12, 21, and the scanning in the previous stage The line 11 is provided with a protruding part, and penetrates the plasma protection layer 71A and the gate insulating layer 30A, and is an example of a planar overlapping structure (the oblique line 52 toward the lower right), but it does not mean that the structure of the storage capacitor 15 will be limited accordingly. , it has been explained with the prior art that between the storage capacitor line 16 and the drain electrode 21 (pixel electrode 22) formed at the same time as the scanning line 11, it can also be formed through an insulating layer containing a gate insulating layer 30A, or It is to use other structures, and the detailed description is omitted here.

In terms of anti-static measures, as shown in Figure 1(e), a transparent conductive layer pattern 40 for anti-static measures is arranged on the periphery of the active circuit board 2, and the transparent conductive layer pattern 40 can be connected through the source/drain wiring. Connected to the transparent conductive electrode terminals 5A, 6A, although such prior art static electricity measures are well-intentioned, since the gate insulating layer 30 has already set the opening portion forming process, it is not necessary to implement other static electricity countermeasures. Difficulty, detailed description is omitted here.

According to Embodiment 1, although the electrode terminals of the scanning lines and the electrode terminals of the signal lines also have restrictions on the device structure of the transparent conductive layer, devices/processing can also be adopted to remove the relevant restrictions. The following will be described with Embodiment 2.

Example 2

Embodiment 2, as shown in FIG. 1(d) and FIG. 2(d), the photosensitive resin pattern 82C is used as a mask plate to selectively etch the second amorphous silica gel layer 33B and the first amorphous silica gel layer 31B, On the gate 11A, stripe-shaped semiconductor layers 33A, 31A having a pattern width wider than that of the gate 11A are formed, and the same manufacturing process as in the first embodiment is carried out until the gate insulating layer 30A is exposed. However, the electrode terminal 6A for the signal line is not necessary for the following reason.

After removing the above-mentioned photosensitive resin pattern 82C, during the formation of the source/drain wiring, use a vacuum film-forming device such as SPT to coat a heat-resistant metal layer with a film thickness of about 0.1 μm, such as a thin film layer 34 such as Ti and Ta. , and the AL film layer 35 of the low-resistance wiring layer with a film thickness of about 0.3 μm. Next, using photosensitive organic insulating layer patterns 86A and 86B through microfabrication techniques, the source/drain wiring material composed of two layers of films, the second amorphous silica gel layer 33A and the first amorphous silica gel layer are sequentially etched. layer 31A, and expose gate insulating layer 30A and protective insulating layer 32D, as shown in FIG. 3(e) and FIG. Form the drain 21 of the insulated gate type thin film transistor, and the signal line 12 as the source. When the source/drain wiring 12, 21 is formed, a part 5A of the exposed scanning line is also formed at the same time. The electrode terminal 5 of the line and the electrode terminal 6 constituted by a part of the signal line. In other words, as shown in Embodiment 1, it is not necessary to have the transparent conductive signal line electrode terminal 6A. At this time, assuming that the film thickness of 86A (12) on the signal line 12 is 3 μm, the most important feature of Embodiment 2 is that the photosensitive organic insulating layer patterns 86A and 86B formed in advance are smaller than those on the drain electrode 21 through the halftone image exposure technology. 86B ( 21 ), 86B ( 5 ) and 86B ( 6 ) on electrode terminals 5 and 6 , and 86B ( 72 ) on storage electrode 72 have a film thickness of 1.5 μm. The minimum size of 86B(5) and 86B(6) supporting electrode terminals 5 and 6 will increase to several 10 μm. Although it is not difficult to manage the size of the mask board when it is manufactured or completed, it is not difficult to match the size of the signal line 12. The minimum size of the region 86A ( 12 ) is 4-8 μm, which is relatively high in dimensional accuracy. Therefore, the graphics in the black area must be finer. However, as explained in previous examples, compared with the source/drain wiring formed after one exposure treatment and two etching treatments, the source/drain wiring of the present invention only needs one exposure treatment. And one etching process can be formed, there are few factors affecting the variation of pattern width, whether it is the size management of source/drain wiring, or the size management of channel length between source/drain wiring, the graphics The management of accuracy is simpler than the past halftone image exposure technology. Furthermore, compared with the channel etching type IGTFT, the ON current of the etch stop layer type IGTFT is determined by the size of the protective insulating layer 32D protecting the channel, not the source/drain electrode. Therefore, it can be understood that the handling and management will be easier.

After the source/drain wires 12 and 21 are formed, the photosensitive organic insulating layer patterns 86A and 86B are reduced by more than 1.5 μm in film thickness through an ashing method such as oxygen plasma, and after the photosensitive organic insulating layer pattern 86B disappears, as As shown in Fig. 3(f) and Fig. 4(f), while exposing the drain electrode 21, the electrode terminals 5, 6 and the accumulation electrode 72, on the signal line 12, although there is only the photosensitive organic insulating layer pattern 86C minus the film thickness (12) can be directly retained, but under the above-mentioned oxygen plasma treatment, once the pattern width of the photosensitive organic insulating layer pattern 86C (12) becomes thinner and exposes the top of the signal line 12, the stability will be reduced. Therefore, it is better to Only by strengthening the anisotropy can the change of the pattern size be effectively suppressed, specifically, the RIE (Reactive Ion Etching Plasama) method, the ICP (Inductive Coupled Plasama) method with a high-density ion source or the TCP (Transfer Coupled Plasama) method Oxygen plasma treatment is ideal. In addition, in terms of the structure of the source/drain wiring 12, 21, Ta, Cr, MoW, etc. can be simplified to a single layer as long as the restriction on the resistance value is relaxed.

After pasting the color filter on the active circuit board 2 manufactured in the above embodiment, it becomes a liquid crystal panel, and the second embodiment of the present invention is also completed. According to Embodiment 2, since the photosensitive organic insulating layer pattern 86C is in contact with the liquid crystal, the main component of the photosensitive organic insulating layer is thermoplastic phenolic resin instead of ordinary photosensitive resin. Not only is the purity high, but the most important thing is that the main component is Acrylic resin or polyimide film resin, photosensitive organic insulating layer with high heat resistance. The structure of the storage capacitor 15 is the same as that of the first embodiment. In addition, as shown in Figure 3 (f), connect a part 5A of the scanning line of transparent conductivity, and the pattern 6A of transparent conductivity formed under the signal line 12, and the short-circuit line 40 that is arranged on the periphery of the active circuit board 2 If the shape of the transparent conductive layer pattern is elongated and linear, high-resistance wiring can be used for electrostatic measures. In addition, electrostatic measures using other conductive parts can of course also be implemented.

According to Embodiment 2, the photosensitive organic insulating layer 86C (12) is only formed on the signal line 12. Like the storage electrode 72 and the pixel electrode 22, the drain electrode 21 maintains conductivity and is exposed at the same time. Even so, sufficient stability can be achieved. This is because the driving signal applied to the liquid crystal cell is basically an alternating current. During image inspection, the voltage of the opposite electrode 14 will be adjusted (adjusted to reduce flicker), so as to reduce the voltage of the opposite electrode 14 on the color filter 9. DC voltage component between the pixel electrode 22 (drain 21). Therefore, the basic principle on which it is based is that it is better to form an insulating layer in advance so as not to conduct only the DC component on the signal line 12 .

If the electrode terminals 5 and 6 with the same metallicity as the source/drain wiring material can be formed like this, the electrode terminal 6A of the signal line is no longer needed, because the signal line 12 is connected to the short-circuit line 40 for preventing static electricity. It is a necessary part in function. Similarly, the electrode terminal 5A of the scanning line 11 is no longer needed, because the metallic electrode terminal 5 is connected to the scanning line 11, which is a necessary part (contact point) in function, and of course it needs to be made of transparent conductive material. Layers constitute part of the scan line 5A.

In addition, there is no need to form the metallic electrode terminal 5 on the transparent conductive scanning line electrode terminal 5A, and the formation of the source/drain wiring including the portion of the electrode terminal 6A of the transparent conductive signal line 12 is changed. After the graphic design, as shown in Figure 3(g) and Figure 4(g), after changing to the electrode terminals 5 and 6 formed by the source/drain wiring material, the same as Embodiment 1 can be obtained, which is transparent and conductive The electrode terminals 5A, 6A constituted in layers, and the device structure in the image display portion remain unchanged.

As mentioned above, in Embodiment 1 and Embodiment 2 of the present invention, the organic insulating layer is only formed on the source/drain wiring and the signal line respectively. The thickness of the insulating layer is generally more than 1 μm, so when using the alignment film of the flat grinding cloth for alignment treatment, the difference will cause a non-alignment state, or may affect the gap accuracy of the liquid crystal cell. Therefore, in Embodiment 3, the organic insulating layer can be provided with different passivation techniques by adding the least number of processes.

Example 3

In Embodiment 3, as shown in FIG. 5(d) and FIG. 6(d), the manufacturing process is substantially the same as that of Embodiment 2 before the contact point formation process and the formation process of semiconductor layers 33A, 31A. After removing the photosensitive resin pattern 82C, in the process of forming the source/drain wiring, use a vacuum film-forming device such as SPT to sequentially coat a heat-resistant metal layer with a film thickness of about 0.1 μm that can be anodized, such as Ti, Ta The equal thin film layer 34, and the Al thin film layer 35 of the low-resistance wiring layer that can also be anodized with a film thickness of about 0.3 μm. Next, through microfabrication techniques, use photosensitive resin patterns 87A and 87B to sequentially etch the source/drain wiring material, the second amorphous silica gel layer 33A, and the first amorphous silica gel layer 31A. , and expose the gate insulating layer 30A and the protective insulating layer 32D, as shown in FIG. 5( e) and FIG. The drain 21 of the gate type thin film transistor, and the signal line 12 as the source wiring, and while forming the source/drain wiring 12, 21, including a part 5A that exposes the scanning line, also forms the scanning line The electrode terminal 5, and the electrode terminal 6 constituted by a part of the signal line. At this time, assuming that the film thickness (black area) of 87A(5) and 87A(6) on the electrode terminals 5 and 6 is 3 μm, the photosensitive resin patterns 87A and 87B formed by the halftone image exposure technology are smaller than the source/drain electrodes. The film thickness (midtone area) of 87B(12), 87B(21) and 87B(72) on wirings 12 and 21 and on storage electrode 72 is 1.5 μm, which is the most important feature of Example 2.

After the source/drain wiring 12, 21 is formed, the film thickness of the photosensitive resin pattern 87A, 87B is reduced by more than 1.5 μm through an ashing method such as oxygen plasma, and the photosensitive resin pattern 87B disappears, and the source/drain pattern is exposed. Along with the drain wiring 12, 21 and the storage electrode 72, on the electrode terminals 5, 6, only the photosensitive resin patterns 87C(5), 87C(6) minus the film thickness can be left directly. After the above-mentioned oxygen plasma treatment, even if the pattern width of the photosensitive resin pattern 87C becomes thinner, an anodic oxide layer will only be formed around the electrode terminals 5 and 6 with a larger pattern size, which will hardly affect the electrical properties and good products. Efficiency and quality, this is a feature that must be particularly emphasized. Next, use the photosensitive resin pattern 87C(5) and 87C(6) with reduced film thickness as the mask plate, and at the same time of irradiating light, as shown in Figure 5(f) and Figure 6(f), the source/drain configuration After the lines 12, 21 are anodized, while the oxide layers 68, 69 are formed, the second amorphous silica gel layer 33A and the first amorphous silica gel layer exposed on the lower side of the source/drain wiring 12, 21 After 31A is anodized, silicon oxide layers (SiO2) 66 and 67 (not shown in the figure) of the insulating layer will be formed.

Al is exposed above the source/drain wiring 12, 21, or the stack of Al and Ti is exposed on the side. Through anodic oxidation, Ti becomes semiconductor titanium oxide (TiO2) 68, and Al becomes an insulating layer. Aluminum oxide (AL2O3)69. Although the titanium oxide layer 68 is not an insulating layer, because the film thickness is very thin and the exposed area is small, so it will not cause passivation problems, but the heat-resistant metal film layer 34A is preferably Ta. However, unlike Ti and Ta, after adsorbing the surface oxide layer of the bottom layer, it lacks the function of easily forming a resistive contact point, and this feature must be paid special attention to.

The film thickness of each oxide layer of aluminum oxide 69 and titanium oxide 68 formed by anodic oxidation is about 0.1-0.2 μm, which is sufficient for the passivation of wiring, and it can reach more than 100V by using a chemical synthesis liquid such as ethylene glycol. the applied voltage. When the source/drain wiring 12, 21 is anodized, although it is not marked in the figure, it must be noted that all the signal lines 12 are formed in parallel or in series according to the electrical characteristics, and then in a certain stage of the subsequent manufacturing process, the direct connection must be removed. Otherwise, it will not only hinder the electrical inspection of the active circuit board 2, but even affect the actual operation of the liquid crystal display device. One of the removal methods is to use laser light to cause evaporation and dispersion, or to use a scribe to perform mechanical removal. These methods are very simple, and detailed descriptions are omitted here.

After finishing the anodic oxidation, remove the photosensitive resin pattern 87C (5), 87C (6) that reduces film thickness, as shown in Fig. 5 (g) and Fig. 6 (g), its side will expose the low resistance formed by the anodized layer. Electrode terminals 5, 6 made of thin film layers. The anodizing current passes through the high-resistance short-circuit line 40 for static electricity prevention, and flows to the side surface of the electrode terminal 5 of the scanning line. Compared with the electrode terminal 6 of the signal line, it is conceivable that the thickness of the insulating layer formed on the side becomes relatively thin. In addition, in terms of the structure of the source/drain wiring 12, 21, as long as the restriction on the resistance value is relaxed, it can be simplified to a single layer of Ta which can be anodized. After pasting the color filter on the active circuit board 2 manufactured in the above embodiment, it becomes a liquid crystal panel, and the third embodiment of the present invention is completed. The structure of the storage capacitor 15 is the same as that of the first and second embodiments.

According to Embodiment 3, when the source/drain wiring 12, 21, the second amorphous silica gel layer 33A, and the first amorphous silica gel layer 31A are anodized, the pixel electrode 22 electrically connected to the drain electrode 21 is also At the same time, it will be anodized. Although special attention must be paid when increasing the resistance value of the transparent conductive layer, there is no need to worry about the transparency of the transparent conductive layer being reduced. The current for anodic oxidation of the drain electrode 21, the pixel electrode 22 and the storage electrode 72 must also be supplied through the channel of the insulated gate type thin film transistor. Since the area of the pixel electrode 22 is relatively large, there must be a chemical synthesis current or a long time No matter how strong the external light is irradiated, it will affect the resistance of the channel part. Therefore, if it is necessary to form an anodic oxide layer 69 on the drain electrode 21 and the storage electrode 72 with the same film quality and film thickness as that on the signal line 12 (21), 69(72), it is difficult to support only prolonging the chemical synthesis time. However, even if the anodized layers 69 ( 21 ) and 69 ( 72 ) formed on the drain wiring 21 and the storage electrode 72 are not perfect, they will not affect the practicality and can achieve a more desirable stability. This is because the driving signal applied to the liquid crystal cell is basically an alternating current, and during image inspection, the voltage of the opposite electrode 14 can be adjusted (adjustment lightens flash), so as to reduce the contrast between the opposite electrode 14 and the pixel on the color filter 9. DC voltage component between electrodes 22 (drain 21). Therefore, it is preferable to form an insulating layer in advance so as not to conduct only a DC component on the signal line 12 .

As in Embodiment 1, it is not necessary to form metallic electrode terminals 5 on transparent conductive scanning line electrode terminals 5A, a part of electrode terminals 6A including transparent conductive signal lines 12, and change source/drain wiring 12, 21 Forming graphic design, as shown in Figure 5(h) and Figure 6(h), changing the electrode terminals 5 and 6 formed by the source/drain wiring materials can obtain the electrode terminals formed by the transparent conductive layer 5A, 6A. At this time, when forming source/drain wiring 12, 21, although the halftone image exposure technique is no longer necessary, special care must be taken when increasing the resistance value of electrode terminals 5A, 6A made of transparent conductive layers. In this case, even if the structure of the electrode terminals is changed, the structure of the device in the image display portion remains unchanged.

Claims (6)

1. A liquid crystal display device, on the main plane of a first transparent insulating substrate, at least has an insulated gate type thin film transistor, which can be used as the scanning line of the gate of the insulated gate type thin film transistor, and can be used as the source The signal line of the wiring and the unit pixel formed by the pixel electrode connected to the drain wiring are arranged in a two-dimensional matrix on the first transparent insulating substrate, and the liquid crystal is filled in the second transparent insulating substrate opposite to the first transparent insulating substrate or Between color filters, characterized by: On the main plane of the first transparent insulating circuit board, a scanning line composed of a transparent conductive layer and a first metal layer, a transparent conductive pixel electrode, and a transparent conductive layer of the signal line outside the image display area are formed. electrode terminal, forming an island-shaped first semiconductor layer without impurities through the plasma protection layer, and forming a gate insulating layer on the gate electrode, On the above-mentioned first semiconductor layer, a protective insulating layer narrower than the gate is formed, Openings are formed in the plasma protective layer and the gate insulating layer on the pixel electrodes, on the electrode terminals of the scanning lines, and on the electrode terminals of the signal lines, and the pixel electrodes are exposed in each opening. electrode terminals and electrode terminals of the signal line, On a part of the above-mentioned protective insulating layer and the first semiconductor layer, a pair of second semiconductor layers containing impurities is formed to form the source/drain of the insulated gate type thin film transistor, On the gate insulating layer, on the second semiconductor layer, and on a part of the signal line electrode terminal, a source (signal line) wiring composed of one or more second metal layers is formed. The second metal layer includes a heat-resistant metal layer, and a drain wiring is formed on the gate insulating layer, on the second semiconductor layer, and on a part of the pixel electrode inside the opening, and On the above-mentioned source and drain wirings, a photosensitive organic insulating layer is formed. 2. A liquid crystal display device, a structure of a liquid crystal display device, on the main plane of a first transparent insulating substrate, at least has an insulated gate type thin film transistor, which can be used as the gate of the insulated gate type thin film transistor The scanning line, which can be used as the signal line of the source wiring, and the unit pixel formed by the pixel electrode connected to the drain wiring are arranged in a two-dimensional matrix on the first transparent insulating substrate, and the liquid crystal is filled with the first transparent insulating substrate. Between the opposite second transparent insulating substrate or color filter, it is characterized in that: On the main plane of the first transparent insulating circuit board, scan lines, transparent conductive pixel electrodes, and signal lines outside the image display area are formed by stacking a transparent conductive layer and a first metal layer Transparent conductive electrode terminals, forming an island-shaped first semiconductor layer without impurities through a plasma protection layer, and forming a gate insulating layer on the gate electrode, On the above-mentioned first semiconductor layer, a protective insulating layer narrower than the gate is formed, On the above-mentioned pixel electrode, the plasma protective layer and the gate insulating layer on a part of the signal line outside the image display area (or on the electrode terminals of the scanning line and the signal line) form openings, and each opening is exposed. Transparent conductive pixel electrodes and transparent conductive parts of scanning lines (or electrode terminals of scanning lines and signal lines), On a part of the above-mentioned protective insulating layer and the first semiconductor layer, a pair of second semiconductor layers containing impurities is formed to form the source/drain of the insulated gate type thin film transistor, On the gate insulating layer and on the second semiconductor layer (and on a part of the signal line electrode terminal), a source (signal line) wiring composed of one or more second metal layers is formed. , the second metal layer includes a heat-resistant metal layer, a drain wiring is formed on the gate insulating layer, on the first semiconductor layer, and on a part of the pixel electrode within the opening, An electrode terminal of the scanning line (or a transparent electrode terminal of the scanning line) is formed on a part of the scanning line, and a signal line terminal (or a transparent conductive signal line electrode terminal) having a part of the signal line is formed, and A photosensitive organic insulating layer is formed on the signal line except on the electrode terminal of the above-mentioned signal line. 3. A structure of a liquid crystal display device. On the main plane of a first transparent insulating substrate, there are at least an insulated gate type thin film transistor, which can be used as a scanning line for the gate of the insulated gate type thin film transistor, and can be used as the gate of the insulated gate type thin film transistor. The unit pixels formed by the signal line of the source wiring and the pixel electrode connected to the drain wiring are arranged in a two-dimensional matrix on the first transparent insulating substrate, and the liquid crystal is filled in the second transparent insulating substrate opposite to the first transparent insulating substrate. Between substrates or color filters, characterized by: On the main plane of the first transparent insulating circuit board, a scan line, a transparent conductive pixel electrode, and a transparent conductive electrode terminal of a signal line formed by laminating a transparent conductive layer and a first metal layer are formed, forming an island-shaped first semiconductor layer without impurities through the plasma protection layer, and forming a gate insulating layer on the gate electrode, On the above-mentioned first semiconductor layer, a protective insulating layer narrower than the gate is formed, On the above-mentioned pixel electrode, on a part of the signal line outside the image display area (or on the electrode terminal of the scanning line and the signal line), the plasma protective layer and the gate insulating layer form openings, and each opening is exposed. Transparent conductive pixel electrodes and transparent conductive parts of scanning lines (or electrode terminals of scanning lines and signal lines), On a part of the above-mentioned protective insulating layer and the first semiconductor layer, a pair of second semiconductor layers containing impurities is formed to form the source/drain of the insulated gate type thin film transistor, On the gate insulating layer and on the second semiconductor layer (and on a part of the signal line electrode terminal), a source (signal line) wiring composed of one or more anodized metal layers is formed, The second metal layer includes a heat-resistant metal layer, and an anodized metal layer is formed on the gate insulating layer, on the first semiconductor layer, and on a part of the pixel electrode inside the opening. The drain wiring is formed to form an electrode terminal of the scanning line (or a transparent electrode terminal of the scanning line) on a part of the scanning line and a signal line terminal (or a transparent conductive signal line) to form a part of the signal line. electrode terminals), and In addition to the above-mentioned electrode terminals, an anodized layer is formed on the source-drain wiring. 4. A manufacturing method of a liquid crystal display device, on the main plane of a first transparent insulating substrate, forming at least a scanning line with an insulated gate type thin film transistor, which can be used as the gate of the insulated gate type thin film transistor, and can The signal line as the source wiring and the unit pixel formed by the pixel electrode connected to the drain wiring are arranged in a two-dimensional matrix on the first transparent insulating substrate, and the second transparent insulating substrate opposite to the first transparent insulating substrate is filled with liquid crystal. Between transparent insulating substrates or color filters, the manufacturing method includes steps: On the main plane of the first transparent insulating circuit board, scan lines, scan line-like electrode terminals, signal line-like electrode terminals, and pixel-like electrodes forming a part of the scan lines are all composed of a transparent conductive layer and a A first metal layer is stacked, coating a plasma protective layer, a gate insulating layer, a first amorphous silicon layer free of impurities and a protective insulating layer in sequence, exposing the first amorphous silicon layer while retaining the protective insulating layer narrower than the gate on the gate, coating the second amorphous silicon layer containing impurities, A photosensitive resin mold is formed, which has openings on electrode terminals such as the scanning line and the signal line outside an image display area, and the thickness of the photosensitive resin mold resin on the semiconductor layer formation region on the gate electrode is smaller than that of the other area thick, Using the photosensitive resin molding resin as a photomask, remove the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, the plasma protection layer and the first metal layer in the opening , and expose the transparent conductive electrode terminals of the scanning lines and signal lines, and the transparent conductive pixel electrodes, reducing the film thickness of the above-mentioned photosensitive resin, and exposing the second amorphous silicon layer, forming an island-shaped second amorphous silicon layer on the gate, and the first amorphous silicon layer wider than the gate, exposing the gate insulating layer, and After coating the second metal layer containing more than one layer and having a heat-resistant metal layer, the second metal layer, the second amorphous silicon layer and the first amorphous silicon layer are selectively removed by microfabrication technology, A source wire (signal wire) including a second metal layer is formed, the source wire overlaps a part of the protective insulating layer and a part of the signal wire electrode terminal, and has a photosensitive organic insulating layer on the surface, and a second metal layer is formed The drain wire of the layer, the drain wire overlaps a part of the above-mentioned protective insulating layer and a part of the pixel electrode, and has a photosensitive organic insulating layer on the surface. 5. A method for manufacturing a liquid crystal display device, forming at least a scanning line with an insulated gate type thin film transistor on the main plane of a first transparent insulating substrate, which can be used as the gate of the insulated gate type thin film transistor, and can The signal line as the source wiring and the unit pixel formed by the pixel electrode connected to the drain wiring are arranged in a two-dimensional matrix on the first transparent insulating substrate, and the second transparent insulating substrate opposite to the first transparent insulating substrate is filled with liquid crystal. Between transparent insulating substrates or color filters, the manufacturing method includes steps: On the main plane of the first transparent insulating circuit board, scan lines, scan line-like electrode terminals, signal line-like electrode terminals, and pixel-like electrodes forming a part of the scan lines are all composed of a transparent conductive layer and a A first metal layer is stacked, sequentially coating a plasma protection layer, a gate insulating layer, a first amorphous silica gel layer free of impurities, and a protective insulating layer, While retaining the protective insulating layer narrower than the grid on the grid, exposing the first amorphous silica gel layer, coating the second amorphous silica gel layer containing impurities, Forming a photosensitive resin mold, which has openings on the scanning line (or electrode terminals such as the scanning line and the signal line) and the pixel electrode, and the photosensitive resin mold is formed on the semiconductor layer on the gate electrode area is thicker than other areas, Using the photosensitive resin mold as a photomask, removing the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, the plasma protection layer and the first metal layer in the opening, And expose the transparent conductive part of the scanning line (or the transparent conductive electrode terminal of the scanning line and the signal line), and the transparent conductive pixel electrode, reducing the film thickness of the above-mentioned photosensitive resin mold, and exposing the second amorphous silicon layer, forming an island-shaped second amorphous silicon layer on the gate, and the first amorphous silicon layer wider than the gate, and exposing the gate insulating layer, After coating the second metal layer that contains more than one layer and has a heat-resistant metal layer, the part where the source wire overlaps the above-mentioned protective insulating layer, and the part where the drain wire overlaps the above-mentioned protective insulating layer and the pixel electrode A photosensitive organic insulating layer is formed on the part of the electrode terminal of the scanning line overlapping with the above-mentioned scanning line, and the electrode terminal of the signal wire that constitutes a part of the above-mentioned signal line, or a photosensitive organic insulating layer is formed on the source wire and the above-mentioned protective insulating layer and A photosensitive organic insulating layer is formed on the portion of the signal wire where the transparent wire electrode terminal overlaps, and the portion where the drain wire overlaps with the above-mentioned protective insulating layer and the pixel electrode, and its thickness is thicker in the signal wire than in other areas, Selectively remove the second metal layer, the second amorphous silicon layer and the first amorphous silicon layer, and form scanning lines, signal line electrode terminals and source/drain wiring, and reducing the thickness of the above-mentioned photosensitive organic insulating layer mold, exposing the above-mentioned scan line and signal line electrode terminals, and the drain wiring. 6. A method for manufacturing a liquid crystal display device, forming at least a scanning line with an insulated gate type thin film transistor on the main plane of a first transparent insulating substrate, which can be used as the gate of the insulated gate type thin film transistor, and can The signal line as the source wiring and the unit pixel formed by the pixel electrode connected to the drain wiring are arranged in a two-dimensional matrix on the first transparent insulating substrate, and the second transparent insulating substrate opposite to the first transparent insulating substrate is filled with liquid crystal. Between transparent insulating substrates or color filters, the manufacturing method includes steps: On the main plane of the first transparent insulating circuit board, scanning lines, scanning line-like electrode terminals, signal line-like electrode terminals, and pixel-like electrodes forming a part of the scanning lines are composed of a transparent conductive layer and a A first metal layer is stacked, sequentially coating a plasma protection layer, a gate insulating layer, a first amorphous silica gel layer free of impurities, and a protective insulating layer, While retaining the protective insulating layer narrower than the grid on the grid, exposing the first amorphous silica gel layer, coating the second amorphous silica gel layer containing impurities, Form a first photosensitive resin mold, which has openings on the scanning line (or electrode terminals such as the scanning line and the signal line) and the pixel electrode, and the first photosensitive resin mold is on the gate electrode. The thickness of the layer-forming region is thicker than other regions, Using the above-mentioned first photosensitive resin mold as a photomask, remove the second amorphous silicon layer, the first amorphous silicon layer, the gate insulating layer, the plasma protection layer and the first metal in the opening. layer, and expose the transparent conductive portion of the scanning line (or the scanning line electrode terminal and the signal line’s transparent conductive electrode terminal), and the transparent conductive pixel electrode, reducing the film thickness of the above-mentioned first photosensitive resin mold, and exposing the second amorphous silicon layer, Using the photosensitive resin mold with reduced thickness as a mask board, an island-shaped second amorphous silicon layer and the first amorphous silicon layer wider than the gate are formed on the gate, and the gate insulation is exposed. layer, After coating an anodizable metal layer containing more than one layer and having a heat-resistant metal layer, the overlapped part of the source wire and the above-mentioned protective insulating layer, the drain wire and the above-mentioned protective insulating layer and the pixel electrode The second photosensitive resin mold is formed on the overlapping portion, the overlapping portion of the scanning line electrode terminal and the above-mentioned scanning line, and the electrode terminal of the signal wire that constitutes a part of the above-mentioned signal line, and its thickness is between the scanning line and the scanning line. The signal line is thicker than other areas, Using the above-mentioned second photosensitive resin module as a photomask, selectively remove the anodizable metal layer, the second amorphous silicon layer and the first amorphous silicon layer, and form an anodizable metal layer The electrode terminals of the scan lines and signal lines and the source/drain wires, reducing the thickness of the above-mentioned second photosensitive resin mold and exposing source/drain wiring, and While protecting the above-mentioned electrode terminals, use the above-mentioned second photosensitive resin mold with reduced thickness as a photomask to carry out the process of anodic oxidation of the above-mentioned source/drain wiring (or partially overlap with the above-mentioned protective insulating layer, After forming the source wiring including part of the transparent conductive signal line electrode terminal, and the drain wiring also including part of the pixel electrode, the above-mentioned source/drain wiring anodic oxidation process is performed).

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