CN1901008A - Electronic circuit, electronic device, method of driving electronic device, electro-optical device, and electronic apparatus - Google Patents

Abstract

A unit circuit (U) is arranged at the intersection between the scanning line (13) and the reference signal line (19) and the data line (15). The unit circuit (U) includes: an electro-optical element (35) driven according to the driving current (Sdr), and an inversion that outputs the driving current (Sdr) within a time period corresponding to the potential (Va) of the input terminal (T). A phase switch (34), a capacitive element having a first electrode (E1) connected to the input terminal (T) and a second electrode (E2) connected to the reference signal line (19). A plurality of scanning lines (13) are sequentially selected every first period, and a data potential (Vdata) is supplied to an input terminal (T) of a unit circuit (U) corresponding to the selected scanning line (13). In each reference signal line (19), the low potential is maintained during the first period in which the scanning line (13) corresponding to the reference signal line (19) is selected, and the potential is different for each reference signal line (19). During the second period of , a reference signal (W[i]) whose potential changes with time is supplied. Accordingly, the period during which the electro-optical element is driven can be sufficiently ensured.

Description

Electronic circuit, electronic device and driving method thereof, electro-optical device and electronic device

technical field

The present invention relates to a method for various driven elements such as organic light emitting diode (hereinafter referred to as "OLED" (Organic LightEmitting Diode)) elements, liquid crystal elements, electrophoretic elements, electrochromic elements, electron emission elements, resistance elements, etc. technology to control the movement.

Background technique

Conventionally, various techniques for driving such driven elements have been proposed. For example, Patent Document 1 discloses a structure in which a plurality of unit circuits including OLED elements as driven elements are arranged in a planar shape. Each unit circuit includes: a driving transistor that controls the current supplied to the OLED element according to a gate voltage; a reset transistor that diode-connects the driving transistor; and a light emission control transistor that controls the current supply and the OLED element. No to switch. According to this configuration, it is possible to compensate for errors (variations) in the threshold voltages of the drive transistors in each unit circuit.

Conventionally, various techniques for driving such driven elements have been proposed. For example, Patent Document 2 discloses a structure in which multiple gray scales are displayed by controlling the pulse width of a drive signal (for example, a current signal) supplied to an OLED element of each pixel. In this structure, the drive signal is controlled for each pixel based on the comparison result between the data signal specifying the gradation of each pixel and a signal (hereinafter referred to as "reference signal") whose level changes over time, such as a triangular wave. the pulse width.

However, it is preferable that the total number of transistors constituting one unit circuit is small. This is because the larger the total number of transistors, the more complicated the structure of the unit circuit, and the higher the manufacturing cost. Furthermore, in an electro-optical device using a unit circuit as a pixel, there is also a problem that the larger the total number of transistors, the lower the aperture ratio. However, according to the conventional configuration, there is a limit to reducing the total number of transistors in each unit circuit. For example, in the structure of Patent Document 1, a light emission control transistor is indispensable in order to turn off the OLED element during data writing in the unit circuit. One of the aspects of the present invention is effective because, for example, the structure of each unit circuit is simplified.

In the structure disclosed in Patent Document 2, one frame is divided into a scanning period and a light emitting period, and after the data signal is supplied to all pixels in the scanning period, the OLED elements of all pixels are turned on by supplying a reference signal in the light emitting period. are driven together (especially refer to FIG. 2 of Patent Document 2). In such a configuration in which the scanning period and the light emitting period are separately set within one frame, there is a problem that, for example, it is difficult to ensure a sufficiently long light emitting period. In addition, in some cases, if the light emission period is not long enough, the luminance of each OLED element may be insufficient, and the display may become dark. Furthermore, if the length of the light emission period is shortened, the pulse width of the drive signal (especially the pulse width corresponding to low luminance) has to be shortened. However, in some cases, especially in electro-optical devices such as OLED devices, the characteristics gradually deteriorate due to the concentration of current in a short period of time (for example, the supply of spike-like current).

Furthermore, in the configuration of Patent Document 2, a data signal is supplied to one electrode of the capacitive element. In this configuration, it may take time to correctly set the potential of the other electrode of the capacitive element when the data signal is supplied.

Patent Document 1: JP-A-2003-122301 (FIG. 1)

Patent Document 2: JP-A-2003-223137 (paragraph 0014 and FIG. 2 )

Contents of the invention

The present invention is made in view of the above problems.

The electronic device of the present invention includes: a plurality of first wirings (such as the scanning lines in FIG. 1) 13, a plurality of second wirings (such as the data lines 15 in FIG. A plurality of unit circuits arranged corresponding to intersections between the first wiring and the plurality of second wirings are used to supply reference signals (for example, reference signals W[1] to W[m in each embodiment) to the plurality of unit circuits. ]), each of the plurality of unit circuits includes: a driven element (such as the electro-optical element 35 in FIG. 3 ), which is driven by the supply of a driving voltage or a driving current; a driving mechanism, which The above-mentioned driving voltage or the above-mentioned driving current is supplied to the above-mentioned driven element (for example, the inverter 34 of FIG. 3 or a group of the inverter 34 and the transistor 39 of FIG. 7 ); The electrical connection between the input terminal (such as the input terminal T of FIG. 3 ) and one of the above-mentioned multiple second wirings is controlled (for example, the transistor 31 of FIG. 3 ); and a capacitive element, which includes the above-mentioned input The terminal is connected to a first electrode, and a second electrode is connected to one of the plurality of reference signal lines, and charge is stored between the first electrode and the second electrode.

In this configuration, during the first period, the data signal is supplied from the second wiring to the input terminal of the drive mechanism via the switching element, and after the first period elapses, if the reference signal changes, the capacitive coupling in the capacitive element , and the potential of the input terminal is changed from the potential of the data signal in the first period before it only by the fluctuation amount of the reference signal. Therefore, during a driving period whose length corresponds to the potential of the input terminal, the driven element to which the driving voltage or driving current is supplied is driven into a state corresponding to the data signal. Furthermore, since the potential of the second electrode of the capacitive element is directly set via the reference signal line, there is an advantage that the potentials of both electrodes of the capacitive element can be set in a short time.

And, the electronic device in the present invention has: a plurality of first wirings (such as the scanning lines 13 of FIG. 1 ); a plurality of second wirings (such as the data lines 15 of FIG. 1 ) intersecting with the plurality of first wirings; A plurality of unit circuits at positions corresponding to intersections between a plurality of first wirings and a plurality of second wirings; a selection circuit for respectively selecting a plurality of first wirings in each first period (for example, the scan of FIG. 1 Line driving circuit 23); In each first period, a data supply circuit (for example, the data line driving circuit 25 of FIG. 1 ) that supplies data potentials to a plurality of second wirings respectively; The first wiring corresponding to the signal line maintains a constant potential during the first period in which the first wiring is selected, and generates a reference signal whose potential changes over time in a period different from every other reference signal line (for example, the reference signal in each embodiment). Signal generation circuit for outputting signals W[1]~W[m]). Furthermore, each of a plurality of unit circuits includes: a driven element (such as the electro-optical element 35 of FIG. 3 ), which is driven by supply of a driving voltage or a driving current; Or the group of the inverter 34 and the transistor 39 of FIG. 7 ), which supplies the driving voltage or the driving current to the driven element during the length corresponding to the potential of the input terminal (for example, the input terminal T of FIG. 3 ); the switch an element (such as the transistor 31 of FIG. 3 ), which electrically connects the input terminal to the second wiring during the first period in which the first wiring corresponding to the unit circuit is selected; and a capacitive element which includes a first wiring connected to the input terminal. An electrode and a second electrode connected to one of the plurality of reference signal lines store charges between the first electrode and the second electrode.

In this structure, a data signal is supplied to the input terminal of the drive mechanism through the switching element during the first period, and in the second period after the first period elapses, if the reference signal changes with time, it is passed through the capacitance of the capacitance element. Coupling, so that the potential of the input terminal changes only by the fluctuation amount of the reference signal from the data potential in the first period before it. Therefore, the driven element to which the driving voltage or the driving current is supplied for a period corresponding to the potential of the input terminal is driven to a state corresponding to the data potential. Furthermore, since the potential of the second electrode of the capacitive element is directly set via the reference signal line, there is an advantage that the potentials of both electrodes of the capacitive element can be set in a short time.

Here, the second period in which the potential of the reference signal changes over time is set separately for each reference signal line, and the timing is different. Therefore, if the data potential of one unit circuit is captured during the first period, the driven elements of this unit circuit are sequentially driven without waiting for the data potential of other unit circuits to be captured. For example, the driven elements are sequentially driven from the unit circuit whose data potential acquisition is completed. Therefore, according to the present invention, compared with the conventional structure in which the period for taking in the data potential and the period for making all the OLED elements emit light together are separately set in all the unit circuits, it is possible to sufficiently ensure that the driven elements of each unit circuit are controlled. drive period.

In addition, it is preferable that the reference signal in the present invention maintains a constant potential during at least a part of the first period in which the data signal is written, and changes in potential over time during at least the driving period. However, the potential of the reference signal and its variation form during other periods can be appropriately set according to the driving form or function of the driven element. In addition, the interval between the first period and the time when the potential of the reference signal starts to change with time may also be appropriately set according to the driving form or function of the driven element.

In a preferred technical solution of the present invention, the respective potentials of the plurality of reference signal lines are changed at a predetermined cycle. More specifically, it includes: a selection circuit that selects each of the plurality of first wirings; and a signal generation circuit that sequentially supplies the reference signals to the plurality of reference signal lines in the order in which the first wirings are selected. According to this technical solution, it is possible to ensure that the second period of each reference signal is sufficiently long. However, the order in which the first wirings are selected does not necessarily match the order in which the second periods arrive for the reference signal lines corresponding to the first wirings.

In a preferred aspect of the present invention, the potential of the input terminal is set by supplying a data signal to the input terminal via the one second wiring and the switching element during the first period. In addition, the length of the driving period in which the driving voltage or the driving current is supplied to the driven element corresponds to the potential of the input terminal set in the first period. According to this aspect, the length of the driving period during which the driving voltage or the driving current is supplied to the driven element can be set according to the data signal. In these technical means, the input terminal is in a floating state during at least a part of a driving period in which a driving voltage or a driving current is supplied to the driven element. According to this aspect, since the electric charge leakage of the first electrode is prevented, the potential of the input terminal can be accurately fluctuated according to the temporal change of the reference signal.

In a more specific technical solution, the driving mechanism supplies the driving voltage or the driving current to the driven element during a period in which the potential of the input terminal exceeds a predetermined potential and in a period in which the potential of the input terminal falls below a predetermined potential. For example, the drive mechanism outputs a drive voltage or a drive current when the potential at the input terminal exceeds a predetermined potential (threshold voltage Vth in each embodiment), and stops the drive voltage or drive current when the potential at the input terminal falls below a predetermined potential. output. According to this technical solution, since the electro-optical element is driven by a binary value, it is possible to suppress fluctuations in the driving state of the driven element (such as the luminance level of the light-emitting element) caused by variations in the characteristics of each part of the unit circuit or the driven element. deviation. A typical example of the driving mechanism in this technical solution is an inverter.

More specifically, the potential of the one reference signal line is set to at least the first potential when the potential of the input terminal is set based on the data signal in the first period, and the above-mentioned potential is set at the beginning of the second period. The potential of one reference signal line is the first potential, and the one reference signal line becomes a second potential having a voltage level different from the first potential during the second period, and the second period ends. The potential of the one reference signal line at time is the first potential. More specifically, the change in the potential of the one reference signal line during the second period is line-symmetric about the time when the second potential becomes the center. That is, the reference signal has a waveform (typical triangular wave) symmetrical about the midpoint between the start point and the end point of the second period (for example, midpoint tc in FIG. 2 or FIG. 4 ) as a reference line.

According to this technical solution, the center of gravity on the time axis during the period in which the driven element is actually driven (for example, the period in which the electro-optical element emits light) can be used as the center of the second period regardless of the data signal. However, the form of the potential change of the reference signal line (the waveform of the reference signal) does not need to be strictly line-symmetric. That is, as long as the shortest driving period other than the driving period whose time length is zero among the plurality of driving periods respectively corresponding to another data signal is compared with the driving period whose time is longer than it and the second period on the time axis In an iterative manner, it is sufficient to set the potentials (ie, reference signals) of each reference signal line. For example, as described with reference to the illustration in FIG. 4 , among the grayscales G0 to G3, the grayscale G1 with the shortest period of time during which the driving period in which the drive circuit Sdr flows becomes non-zero, in accordance with the driving period, relative to the grayscale G2 or The reference signal is generated so that the driving period of the gray level G3 (longer than the driving period corresponding to the gray level G1 ) overlaps on the time axis of the second period Pb[i].

In a preferred technical solution of the present invention, the plurality of reference signal lines extend in a direction intersecting with the plurality of second wirings. According to this configuration, a common reference signal can be reliably supplied to unit circuits commonly connected to one first wiring via the simple-shaped reference signal line extending along the first wiring.

In another different technical solution, each of the above-mentioned plurality of unit circuits includes a reset mechanism (for example, the transistor 37 in FIG. Before a period, set the above-mentioned input terminal to a specified potential. According to this technical solution, since the input terminal is initialized to a predetermined potential before the first period, the potential of the input terminal can be quickly and accurately set to the data potential during the first period.

The electronic devices of the various technical aspects described above are used in various electronic devices. A typical example of such electronic equipment is an equipment using an electronic device as a display device. Examples of such electronic devices include personal computers and mobile phones. However, the use of the electronic device in the present invention is not limited to displaying images. For example, the electronic device of the present invention can also be applied as an exposure device (exposure head) for forming a latent image on an image carrier such as a photoreceptor drum by irradiation with light.

The driven element in the present invention includes all elements driven electrically. A typical example of the driven element is an electro-optical element (for example, a light-emitting element such as an OLED element) that changes optical characteristics such as luminance or transmittance by applying electric energy (for example, application of an electric field). The present invention can also be specified as an electro-optical device dedicated to driving an electro-optical element. The electro-optical device includes: a plurality of scanning lines; a plurality of data lines intersecting the plurality of scanning lines; a plurality of unit circuits arranged corresponding to intersections between the plurality of scanning lines and the plurality of data lines; and a plurality of reference signal lines for supplying reference signals to the plurality of unit circuits, wherein each of the plurality of unit circuits includes: an electro-optical element driven by supply of a driving voltage or a driving current; a driving mechanism whose supplying the driving voltage or the driving current to the electro-optical element; a switching element controlling an electrical connection between an input terminal included in the driving mechanism and one of the plurality of data lines; and a capacitor An element having a first electrode connected to the input terminal and a second electrode connected to one of the plurality of reference signal lines, charges are stored between the first electrode and the second electrode, and the The length of the driving period in which the driving voltage or the driving current is supplied to the electro-optical element is different from the length set by supplying a data signal to the input terminal via the one data line and the switching element in the first period. The potential corresponding to the above-mentioned input terminal. This configuration also achieves the same operations and effects as those of the electronic device of the present invention.

Furthermore, the present invention can also be implemented as a method for driving an electronic device. That is, the driving method in the present invention is a driving method of an electronic device, wherein the electronic device includes: a plurality of first wirings and a plurality of second wirings intersecting each other, and the plurality of first wirings and the plurality of A plurality of unit circuits and a plurality of reference signal lines arranged correspondingly to intersections between the second wirings, the plurality of unit circuits respectively include: a driven element driven by supply of a driving voltage or a driving current; A mechanism that supplies the driving voltage or the driving current to the driven element; and a capacitive element that includes a first electrode connected to an input terminal included in the driving element and a first electrode connected to one of the plurality of reference signal lines The second electrode connected to the reference signal line stores charges between the first electrode and the second electrode, and supplies data to the input terminal from one of the plurality of second wirings during the first period. signal, thereby setting the potential of the above-mentioned input terminal, so that each potential of the above-mentioned multiple reference signal lines changes in a prescribed cycle. Also by this method, the same functions and effects as those of the electronic device of the present invention can be realized.

An electronic device according to a technical solution of the present invention includes: a signal line, a unit circuit connected to the signal line, and a voltage supply line, and the above-mentioned unit circuit includes: a driving transistor having a control terminal (for example, a gate), a first One terminal (one of the source and the drain), and a second terminal (the other of the source and the drain) connected to the voltage supply line, and the first terminal and the second terminal are set according to the voltage of the control terminal. The conduction state between the two terminals; the driven element (such as the electro-optical element 11 of FIG. 10); the first switch element (such as the transistor T1 of FIG. 10), which controls the above-mentioned control terminal and the above-mentioned first terminal of the above-mentioned driving transistor And the electrical connection between any one of the above-mentioned second terminals is controlled; and a capacitive element (such as the capacitive element C of FIG. 10 ), which is connected between the first electrode (such as the first electrode Ea of FIG. 10 ) and the second electrode ( For example, a dielectric is provided between the second electrodes (Eb) of FIG. A level of at least one of them is set according to a conduction state between the first terminal and the second terminal.

In this structure, by electrically connecting the control terminal of the driving transistor to one of the first terminal and the second terminal via the first switching element, the error in the threshold voltage of the driving transistor is compensated, and on the other hand, the gate of the driving transistor is connected to The electrode voltage is set to a voltage value corresponding to the voltage of the signal line by capacitive coupling in the capacitive element. Therefore, with an extremely simple structure, it is possible to correct for an error in the threshold voltage of the driving transistor (the difference between the threshold voltage of one driving transistor and the design value, or the difference between the driving transistor of each unit circuit in a structure including a plurality of unit circuits). difference in threshold voltage) and drive the driven element.

In addition, in the electronic device of the present technical solution, although a switch for controlling the electrical connection between the signal line and the second electrode (switching whether to supply the voltage of the signal line to the second electrode) may also be arranged. However, from the viewpoint of promoting simplification of the unit circuit, it is preferable that the second electrode is directly connected to the signal line (that is, without intervening a switching element).

In a preferred technical solution of the present invention, during the first period (for example, the writing period Pwrt in FIG. 9 ), any one of the first terminal and the second terminal, via the connection between the first switching element and the driving transistor, The control terminal is electrically connected to supply a data signal (for example, the data voltage Vdata in FIG. The second electrode supplies a control signal (for example, the control voltage Vctl of FIG. 9 ) that changes with time during the second period.

In this technical solution, the data signal is stored in the second electrode during the first period, and the voltage of the second electrode changes with time during the second period. Furthermore, the voltage of the first electrode (that is, the gate voltage of the driving transistor) only changes in voltage value corresponding to the difference in level between the data signal and the control signal through capacitive coupling in the capacitive element. Therefore, according to the present aspect, the driven element can be driven for a long period of time corresponding to the data signal. In addition, if the structure in which the first electrode is in a floating state during the second period is adopted, since the leakage of the charge stored in the first electrode can be suppressed, the voltage of the first electrode can be set to be the same as the voltage of the first electrode with high precision. The corresponding voltage value of the data signal.

In addition, in the drive circuit of this claim, the circuit for supplying the data signal to the unit circuit and the circuit for supplying the control signal to the unit circuit may be mounted in the electronic device as a single circuit separated from each other, or may be It is mounted in an electronic device in a state where both are mounted on a single circuit (for example, an IC chip). Furthermore, the structure may be such that the signal line is also used as a wiring for supplying the control signal to the unit circuit, or the control signal may be supplied to the unit circuit via a wiring separate from the signal line.

An electronic device according to a more specific technical solution further includes: a voltage control circuit that sets the voltage of the above-mentioned voltage supply line to any one of a plurality of voltage values (for example, the electrical connection between the voltage supply line and a predetermined potential is performed). control). The voltage control circuit in this aspect, for example, sets the voltage of the voltage supply line to a first voltage value (for example, voltage value Vss) lower in potential than the first terminal during at least a part of the first period. In at least a part of the second period, the voltage of the voltage supply line is set to a second voltage value (for example, a voltage value Vdd) higher in potential than the first terminal.

In this configuration, at least part of the first period (more specifically, at least part of the period during which the first terminal or the second terminal is connected to the control terminal), the voltage of the voltage supply line is set lower than that of the first terminal. The first voltage value of the potential. Therefore, compared with the configuration in which the voltage of the voltage supply line is set to the second voltage value during this period, the electric energy supplied to the driven element (drive current or drive voltage supplied to the driven element) can be reduced. Therefore, even without disposing a switching element for controlling whether to apply electric energy to the driven element (for example, "emission control transistor" in Patent Document 1), it is possible to control the electric energy to the driven element in the first period in principle. The supply of components is suppressed (ideally, stopped). However, although the light emission control transistor is not required in principle, this does not mean that the structure in which the light emission control transistor is arranged is excluded from the scope of the present invention. That is, the purpose of the structure of the present invention is to more precisely define the period during which the driven element is driven, and a switch for controlling whether to apply electric energy to the driven element may be arranged like the light emission control transistor of Patent Document 1. element.

However, as a transistor (especially a drive transistor) constituting a unit circuit, a transistor including a semiconductor layer composed of various semiconductor materials such as polycrystalline silicon, microcrystalline silicon, single crystal silicon, or amorphous silicon (typically thin film transistor). It is known that in a transistor whose semiconductor layer is formed of, for example, amorphous silicon, if the direction of current flowing therein is always fixed, the threshold voltage will fluctuate over time. According to this technical solution, during the first period, a current (such as the current I0 in FIG. 11 ) flows from the first terminal to the voltage supply line through the second terminal, and on the other hand, during the second period, the current flows from the second terminal through the first terminal. is supplied to the driven element. That is, since the direction of the current flowing in the driving transistor is the same in the first period and the second period, according to this technical solution, even if the semiconductor layer of the driving transistor is formed of amorphous silicon, the threshold voltage can be suppressed. changes. In other words, the structure in which the semiconductor layer of the driving transistor is made of amorphous silicon is particularly suitable for application to the present invention.

In yet another technical solution, the above-mentioned first switching element is a switching transistor, and the transistors included in the above-mentioned unit circuit are only the above-mentioned driving transistor and the above-mentioned switching transistor. According to this configuration, transistors included in a unit circuit can be reduced to two transistors, namely, a driving transistor and a switching transistor, and errors in threshold voltages of the driving transistors can be compensated for. In addition, the specific example of this invention is mentioned later as 3rd Embodiment (FIG. 10).

In a more specific technical solution, the driving element is driven when the voltage value of the first terminal exceeds a prescribed voltage value, and the first voltage value becomes higher than the prescribed voltage value according to the voltage value of the first terminal in the first period. The way of lower potential is decided. According to this aspect, since the voltage value of the first terminal in the first period becomes a potential lower than the predetermined voltage value, it is possible to reliably stop the light emission control transistor in the first period even in a configuration in which no light emission control transistor is arranged. Driven by a driven element (such as emitting light).

However, the voltage value of the first terminal of the driving transistor may occasionally fluctuate due to various external factors such as noise. And, depending on the changed voltage value (for example, when the voltage value of the first terminal becomes lower than or equal to the second voltage value, etc.), recovery to the desired state of driving the driven element may be hindered. Therefore, in a more suitable technical solution of the present invention, the unit circuit includes a first reset mechanism that sets the voltage of the first terminal to a predetermined voltage value. According to this technical solution, for example, even if the voltage value of the first terminal fluctuates occasionally, the voltage of the first terminal can be set to a desired voltage value by the first reset mechanism. In this manner, by resetting the voltage of the first terminal to a voltage value at which a desired drive of the driven element can be performed, stable driving of the driven element is realized. In addition, the timing at which the voltage of the first terminal is set to a predetermined voltage value by the reset mechanism is arbitrary. For example, the voltage value of the first terminal may be set at a predetermined cycle before the start of each first period, or the first terminal may be set when the user operates various operators such as an operator for turning on the power. The structure of the voltage value of the terminal.

More specifically, the first reset mechanism includes a second switching element (for example, transistor T2 in FIG. 13 ), which electrically connects the first terminal to the voltage supply line during initialization, and the voltage control circuit, during initialization, supplies voltage to The voltage of the line is set to the above-mentioned second voltage value. According to this technical solution, since the voltage supply line is also used for resetting the voltage value of the first terminal, it is possible to transfer the electron The structure of the device is simplified. In addition, the specific example of this invention is mentioned later as 2nd Embodiment.

Alternatively, the first reset mechanism includes a second switching element (such as the transistor T2 in FIG. 17 ), which electrically connects the first terminal to a power supply line supplying a constant voltage during initialization, and the voltage control circuit may be to connect the voltage to The voltage of the supply line is set to the first voltage value. According to this technical solution, since the voltage of the voltage supply line is set to the first voltage value during the initialization period, there is an advantage that driving (for example, light emission) of the driven element during the initialization period can be stopped reliably. In addition, the specific example of this invention is mentioned later as 3rd Embodiment.

In another aspect of the present invention, the unit circuit includes a second reset mechanism that sets the voltage of the control terminal of the drive transistor to a predetermined voltage value. According to this technical solution, since the voltage of the control terminal of the drive transistor is set to a desired voltage value, it is possible to set the voltage value of the control terminal of the drive transistor with high precision regardless of the condition of the control terminal before it. for the desired value.

More specifically, the second reset mechanism includes a third switching element (for example, transistor T3 in FIG. 20 ), which electrically connects the control terminal to the voltage supply line during initialization, and the voltage control circuit, during initialization, connects the voltage supply line to The voltage of is set as the second voltage value. According to the technical solution, the voltage of the control terminal is set to the second voltage value during initialization. In addition, since the voltage supply line is also used for resetting the voltage value of the control terminal, the structure of the electronic device can be compared with the structure of using a wiring separately from the voltage supply line for resetting the voltage value of the first terminal. simplify. In addition, the specific example of this invention is mentioned later as 6th Embodiment.

The electronic device of the present invention is used in various electronic devices. A typical example of such electronic equipment is an equipment using an electronic device as a display device. As such electronic devices, there are personal computers and mobile phones. However, the use of the electronic device in the present invention is not limited to displaying images. For example, the electronic device of the present invention can also be applied as an exposure device (exposure head) for forming a latent image on an image carrier such as a photoreceptor drum by irradiation of light.

The driven element in the present invention includes all elements driven electrically. A typical example of the driven element is an electro-optical element that changes optical performance (gradation) such as luminance or transmittance by applying electric energy. An electro-optical device in one aspect of the present invention is constituted by using the electronic device in each of the above-mentioned aspects exclusively for driving the electro-optical element. That is, the electro-optical device (for example, a light-emitting device using a light-emitting element as an electro-optical element) includes a signal line, a unit circuit connected to the signal line, and a voltage supply line. terminal, a first terminal, and a second terminal connected to the above-mentioned voltage supply line, and according to the voltage of the above-mentioned control terminal, the conduction state between the above-mentioned first terminal and the above-mentioned second terminal is set; an electro-optical element; a first switch an element controlling electrical connection between the control terminal of the driving transistor and any one of the first terminal and the second terminal; and a capacitive element having a dielectric between the first electrode and the second electrode The first electrode is connected to the control terminal of the driving transistor, the second electrode is connected to the signal line, and the magnitude of any one of the driving current and the driving voltage supplied to the electro-optical element depends on the first terminal and the driving voltage. The conduction state between the above-mentioned second terminals is set. According to this configuration as well, the same functions and effects as those of the electronic device described above can be achieved. In addition, the technical solutions listed above for the electronic device are also applicable to the electro-optical device.

In addition, an electronic circuit according to a technical solution of the present invention is an electronic circuit for driving a driven element, including: a signal line, a unit circuit connected to the signal line, and a voltage supply line, and the above-mentioned unit circuit includes: a driving transistor , which has a control terminal, a first terminal, and a second terminal connected to the voltage supply line, and sets the conduction state between the first terminal and the second terminal according to the voltage of the control terminal; the first switch an element controlling electrical connection between the control terminal of the driving transistor and any one of the first terminal and the second terminal; and a capacitive element having a dielectric between the first electrode and the second electrode The above-mentioned first electrode is connected to the above-mentioned control terminal of the above-mentioned driving transistor, the above-mentioned second electrode is connected to the above-mentioned signal line, and the magnitude of any one of the driving current and the driving voltage supplied to the above-mentioned driven element depends on the above-mentioned first terminal and The conduction state between the above-mentioned second terminals is set. According to this configuration as well, the same functions and effects as those of the electronic device described above can be achieved. Also, it doesn't matter whether there are driven elements in the electronic circuit or not. In addition, the technical solutions listed above for the electronic device are also applicable to the electronic circuit.

In addition, a technical solution of the present invention is a method of driving the electronic device in each technical solution described above. The driving method is used to drive an electronic device having a unit circuit, and the unit circuit includes: a driving transistor having a control terminal, a first terminal and a second terminal connected to the voltage supply line, and according to the voltage of the control terminal , setting the conduction state between the first terminal and the second terminal; and the driven element, during the first period, connecting any one of the first terminal and the second terminal with the control of the driving transistor The terminals are electrically connected, and a data signal is supplied to the second electrode via the signal line during the first period, and a control signal that changes with time in the second period is supplied to the second electrode during the second period. According to this method, the same functions and effects as those of the electronic device in the above technical solutions can also be realized. Moreover, the various technical solutions listed above for the electronic device are also applicable to the driving method.

Description of drawings

FIG. 1 is a block diagram showing the configuration of an electronic device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing waveforms of the scanning signal Y[i] and the reference signal W[i].

FIG. 3 is a circuit diagram showing the structure of one unit circuit.

FIG. 4 is a timing chart showing the relationship between the potential Va and the drive current Sdr.

5 is a circuit diagram showing a configuration of a unit circuit in an electronic device according to a second embodiment of the present invention.

FIG. 6 is a timing chart showing a waveform of a reference signal W[i] according to a modified example.

FIG. 7 is a circuit diagram showing the configuration of a unit circuit according to a modified example.

8 is a block diagram showing the configuration of an electronic device according to a third embodiment of the present invention.

FIG. 9 is a timing chart for explaining the operation of the electronic device.

FIG. 10 is a circuit diagram showing the structure of one unit circuit.

FIG. 11 is a circuit diagram showing the appearance of a unit circuit in a writing period.

FIG. 12 is a circuit diagram showing the appearance of a unit circuit during a driving period.

13 is a circuit diagram showing the configuration of a unit circuit according to a fourth embodiment of the present invention.

FIG. 14 is a timing chart for explaining the operation of the electronic device according to the fourth embodiment.

FIG. 15 is a circuit diagram showing the appearance of a unit circuit in an initialization period.

FIG. 16 is a sequence diagram illustrating operations in a modified example of the fourth embodiment.

17 is a circuit diagram showing the configuration of a unit circuit according to a fifth embodiment of the present invention.

FIG. 18 is a timing chart for explaining the operation of the electronic device according to the fifth embodiment.

FIG. 19 is a circuit diagram showing the appearance of a unit circuit in an initialization period.

20 is a circuit diagram showing the configuration of a unit circuit in a sixth embodiment of the present invention.

FIG. 21 is a timing chart for explaining the operation of the electronic device according to the sixth embodiment.

FIG. 22 is a circuit diagram showing the appearance of a unit circuit in an initialization period.

Fig. 23 is a perspective view showing a form of electronic equipment (personal computer) according to the present invention.

Fig. 24 is a perspective view showing a form (mobile phone) of an electronic device according to the present invention.

Fig. 25 is a perspective view showing a form of an electronic device (portable information terminal) in the present invention.

In the picture:

D-electronic device, 10-element array section, 13-scanning line, 15-data line, signal line, 17-voltage supply line, 19-reference signal line, 23-scanning line driving circuit, 25-data line driving circuit, Signal line driving circuit, 27-voltage control circuit, 29-signal generating circuit, 37-transistor, 33-capacitance element, 34-inverter, T-inverter input end, 35-electro-optical element, Y[i ]—scanning signal, X[j]—data signal, Vdata—potential of data signal, W[i] reference signal, Sdr—driving current, Va—potential of input terminal of inverter.

Detailed ways

(A: first embodiment)

FIG. 1 is a block diagram showing the configuration of an electronic device according to a first embodiment of the present invention. The electronic device D illustrated in this figure is an electro-optical device used as a mechanism for displaying images in various electronic devices, and includes an element array unit 10 in which a plurality of unit circuits U are arranged in a planar form, and A circuit for driving each unit circuit U (scanning line driving circuit 23/data line driving circuit 25/signal generating circuit 27). In addition, the scanning line driving circuit 23, the data line driving circuit 25, and the signal generating circuit 27 can also be installed in the electronic device D as independent circuits, and a part or all of these circuits can also be installed in the electronic device D as a single circuit. Device D.

As shown in FIG. 1, in the element array section 10, m scanning lines 13 extending in the X direction, m reference signal lines 19 extending in the X direction in pairs with each scanning line 13, and m reference signal lines 19 extending in the X direction are formed. n data lines 15 (m and n are both natural numbers) extending in the orthogonal Y direction. Each unit circuit U is arranged at a position corresponding to the intersection between the scanning line 13 and the pair of reference signal lines 19 and the data line 15 . Therefore, these unit circuits U are arranged in a matrix of m rows x n columns.

The scanning line driving circuit 23 is a circuit for sequentially selecting m scanning lines 13 respectively. To describe it in more detail, as shown in FIG. 2 , the scanning line driving circuit 23 generates signals Pa[1] to Pa[ m] successively become high-level scanning signals Y[ 1 ] to Y[m], and output to the respective scanning lines 13 . The scanning signal Y[i] supplied to the scanning line 13 of the i-th row (i is an integer satisfying 1≤i≤m) is that the i-th first period Pa[i] in one frame (1F) becomes A high level signal that maintains a low level during the period other than this. The transition of the scan signal Y[i] to a high level means that the i-th row is selected.

The data line driving circuit 25 in FIG. 1 supplies data signals X[1] to X to each of unit circuits U in one row (n) corresponding to the scanning line 13 selected by the scanning line driving circuit 23 via each data line 15. [n]. In the first period Pa[i] in which the scanning line 13 of the i-th row is selected, the data signal X[j] supplied to the data line 15 of the j-th column (j is an integer satisfying 1≤j≤n) becomes the same as The potential Vdata corresponding to the gradation (brightness) specified by the unit circuit U belonging to the i-th row and the j-th column. The gradation of each unit circuit U is specified by gradation data supplied from the outside.

The signal generation circuit 27 is a circuit that generates reference signals W[ 1 ] to W[m] and outputs them to m reference signal lines 19 , respectively. As shown in FIG. 2, the reference signal W[i] maintains the potential VH from the beginning to the end of the first period Pa[i] in which the scanning signal Y[i] becomes high level, and during the first period Pa [i] A signal in which the potential changes over time from the start point to the end point of a predetermined period (hereinafter referred to as "second period") Pb[i] after elapse of time.

The reference signal W[i] in this embodiment is from the midpoint tc of Pb[i] in the second period (that is, the time from the start point and the end point of the second period Pb[i] to both the same time) to the start point The waveform of and the waveform from the midpoint tc to the end point become a line-symmetrical triangular wave with the center tc as a reference. That is, the reference signal W[i] changes over time from the potential VH to the potential VL lower than VH in the period from the start point of the second period Pb[i] to the midpoint tc of the second period Pb[i]. At the same time, it decreases; in the stage from the midpoint tc to the end point, the potential VL rises with the passage of time and reaches the potential VH.

As shown in FIG. 2 , the phases of the reference signals W[ 1 ] to W[m] are different from each other. That is, the timings of the second periods Pb[1] to Pb[m] during which the reference signals W[1] to W[m] fluctuate are separately set for each reference signal line 19 (each row) and are different from each other. . More specifically, the second periods Pb[1] to Pb[m] defined by the reference signals W[1] to W[m] supplied to the respective reference signal lines 19 correspond to the respective reference signal lines 19 . The order in which each of the scanning signals Y[1] to Y[m] becomes high level comes sequentially. Therefore, as shown in FIG. 2, the reference signal W[i] fluctuates within the range from the potential VH to the potential VL in parallel with the transition of the scanning signal Y[i+1] of the next row to the high level. .

Next, a specific configuration of each unit circuit U will be described with reference to FIG. 3 . In addition, in this figure, although only one unit circuit U located in the i-th row and the j-th column is shown, other unit circuits U have the same configuration.

As shown in FIG. 3 , the unit circuit U includes a transistor 31 , a capacitive element 33 , an inverter 34 , and an electro-optical element 35 . The electro-optical element 35 is an OLED element in which a light-emitting layer made of an organic EL material is interposed between an anode and a cathode, and emits light at a luminance level corresponding to the magnitude of the drive current Sdr output from the inverter 34 . In addition, the accumulated value generated according to the time of the brightness level corresponds to the brightness.

The inverter 34 includes a p-channel transistor 341 and an n-channel transistor 342 . The source of the transistor 341 is connected to a power supply line that supplies the high-side power supply potential Vdd. The source of the n-channel transistor 342 is connected to a ground line that supplies a low-side power supply potential (hereinafter referred to as "ground potential") Vss. The respective drains of the transistor 341 and the transistor 342 are connected in common to the anode of the electro-optical element 35 . Furthermore, the respective gates of the transistor 341 and the transistor 342 are connected to the input terminal T with each other.

When the potential at the input terminal T of the inverter 34 is lower than a predetermined potential (hereinafter simply referred to as “threshold voltage”) Vth, the transistor 341 is turned on and supplies a drive current Sdr to the electro-optical element 35 . This driving current Sdr is a current for causing the electro-optical element 35 to emit light. Conversely, when the potential Va exceeds the threshold voltage Vth, since the transistor 341 is turned off and the transistor 342 is turned on, the supply of the drive current Sdr to the electro-optical element 35 is stopped.

The capacitive element 33 of FIG. 3 includes a first electrode E1 connected to the input terminal T of the inverter 34 and a second electrode E2 connected to the reference signal line 19, and charges are stored between the first electrode E1 and the second electrode E2 . Furthermore, the n-channel transistor 31 is a switching element interposed between the input terminal T of the inverter 34 and the data line 15 and controlling the electrical connection (conduction and non-conduction) of both. The gate of the transistor 31 is connected to the scanning line 13 . Therefore, in the first period Pa[i] in which the scanning signal Y[i] becomes high level, the transistor 31 is turned on; while the scanning signal Y[i] is maintained at a low level, the transistor 31 is turned off. state.

Next, specific operations of the electronic device D in this embodiment will be described. Hereinafter, the operation of the unit circuit U in the j-th column belonging to the i-th row will be divided into a first period Pa[i] and a second period Pb[i], and will be described.

(a) The first period Pa[i]

In the first period Pa[i], since the scanning signal Y[i] transitions to a high level, the transistor 31 is turned on, and the input terminal T and the data line 15 are electrically connected. In this way, the potential Vdata of the data signal X[j] is supplied from the data line 15 to the input terminal T of the inverter 34 , and charges corresponding to the potential Vdata are stored in the capacitive element 33 . As shown in FIG. 2, since the reference signal W[i] supplied to the second electrode E2 of the capacitive element 33 maintains a constant potential (potential VH) in the first period Pa[i], the potential Va of the input terminal T, The potential Vdata corresponding to the gradation of the unit circuit U is held.

(b) Second period Pb[i]

When the first period Pa[i] elapses and the scanning signal Y[i] becomes low level, since the transistor 31 is transferred to an off state, the input terminal T is electrically disconnected from the data line 15 and becomes a floating state . This state is also maintained in the second period Pb[i]. Therefore, when the reference signal W[i] supplied to the second electrode E2 of the capacitive element 33 fluctuates within the range from the potential VH to the potential VL within the second period Pb[i], the capacitance in the capacitive element 33 The coupling causes the potential Va of the input terminal T (the potential of the first electrode E1 ) to fluctuate only by the amount of change of the reference signal W[i] from the potential Vdata set in the previous first period Pa[i].

FIG. 4 is a timing chart showing the relationship between the potential Va of the input terminal T and the drive current Sdr output from the inverter 34 . In this figure, the waveform of the potential Va when each gradation (G0 to G3) is specified in the unit circuit U is also described. In addition, the potentials V0 to V3 in the figure are the potential Vdata of the data signal X[j] when the respective gradations G0 to G3 are specified (that is, the potential Va set in the first period Pa[i]).

As shown in FIG. 4 , the potential Va of the input terminal T changes by ΔV (=VH−VL) in accordance with the variation of the reference signal W[i] in the second period Pb[i]. At the beginning of the second period Pb[i], since the potential Va is set to the potential Vdata corresponding to the gray scale, the potential Va of the input terminal T in the second period Pb[i] is lower than the threshold value of the inverter 34 The period of the voltage Vth (hereinafter referred to as "driving period") is as long as the potential Vdata supplied from the data line 15 in the preceding first period Pa[i]. For example, since the potential Vdata(V1) corresponding to the grayscale G1 is a higher potential than the potential Vdata(V2) corresponding to the grayscale G2, the time for which the potential Va is lower than the threshold voltage Vth when the grayscale G2 is specified is long, It is longer than the time that the potential Va is lower than the threshold voltage Vth at the specified grayscale G1. In addition, when the gradation G0 is specified, the potential Va exceeds the threshold voltage Vth throughout the second period Pb[i].

Since the potential Va of the input terminal T fluctuates as described above, the drive current Sdr is supplied from the inverter 34 to the electro-optical element 35 during a long drive period (pulse width) corresponding to the data signal X[j]. During the remaining period, the supply of the drive current Sdr corresponding to the electro-optical element 35 is stopped. For example, as shown in FIG. 4 , when the grayscale G2 is specified, the driving period for supplying the driving current Sdr to the electro-optical element 35 is longer than when the grayscale G1 is specified. In addition, when the gradation G0 is specified, the supply of the corresponding driving current Sdr to the electro-optical element 35 is stopped throughout the second period Pb[i]. Since the electro-optical element 35 emits light due to the supply of the drive current Sdr, in the present embodiment, the electro-optical element 35 emits light at a time density corresponding to the potential Vdata of the data signal X[j]. In this way, the gradation of the electro-optical element 35 is controlled for each unit circuit U.

Although the operation of one unit circuit U has been described above, the same operation is performed in units of rows in each unit circuit. More specifically, as shown in FIG. 2 , the supply of the potential Vdata to the input terminal T (the first period Pa[i]) and the variation of the potential Va corresponding to the reference signal W[i] (the second period Pb[i] )) Each unit circuit U in each row is sequentially executed at another timing. Therefore, in the first period Pa[i], when the data signal X[j] is captured in one unit circuit U (that is, when the potential Vdata is supplied to the input terminal T), there is no need to wait for data corresponding to other unit circuits U. The electro-optical element 35 is sequentially driven by taking in the signal X[j]. In other words, the electro-optical elements 35 sequentially emit light from the unit circuit U after the acquisition of the data signal X[j] is completed.

As described above, according to the present embodiment, since the electro-optical element 35 is binary-driven according to the supply and stop of the drive current Sdr, the current to be supplied to the electro-optical element 35 (or to the electro-optical The voltage applied to the element 35) can be controlled stepwise, thereby reducing the influence of variations in the characteristics of the transistors constituting the electro-optical element 35 or the inverter 34. Furthermore, in this embodiment, since the potential of the second electrode E2 of the capacitive element 33 is directly set via the reference signal line 19, the potential of each electrode of the capacitive element 33 can be set in a short time.

Furthermore, according to the present embodiment, compared with the conventional structure in which the scanning period for supplying data signals to all the unit circuits and the light-emitting period for making all the OLED elements emit light are separately set, it is possible to secure the light-emitting period of each electro-optical element 35 for a long period of time. . Therefore, each electro-optical element 35 can be made to emit light with sufficient brightness. In addition, since the pulse width of the driving current Sdr can be set longer than the conventional structure, it is possible to avoid the concentration of instantaneous current on the electro-optical element 35 (supply of spike-like current), and to suppress the characteristics of the electro-optical element 35. deteriorating.

(B: Second Embodiment)

Next, a second embodiment of the present invention will be described. In addition, the same code|symbol is attached|subjected to the same element as 1st Embodiment in this embodiment, and each detailed description is abbreviate|omitted suitably.

FIG. 5 is a circuit diagram showing the configuration of one unit circuit U of the electronic device D in the present embodiment. As shown in the figure, the unit circuit U of the present embodiment is configured by adding an n-channel transistor 37 to the structure of the first embodiment illustrated in FIG. 3 . The transistor 37 is a switching element interposed between the input terminal T and the output terminal of the inverter 34 and controlling the electrical connection (conduction and non-conduction) of both.

The gate of the transistor 37 is connected to a wiring for supplying a reset signal R[i]. The reset signal R[i] becomes a high level signal in the period before the start of the first period Pa[i] in which the scanning signal Y[i] becomes high level, and maintains a low level signal in other periods . That is, reset signal R[ 1 ] to reset signal R[m] become high level sequentially in the order in which each row is selected.

In the above structure, when the reset signal R[i] becomes high level, the transistor 37 is turned on and electrically connects the input terminal T and the output terminal of the inverter 34 . Therefore, the potentials of both the input terminal T and the output terminal of the inverter 34 become the difference (Vdd−Vth_P) between the power supply potential Vdd and the threshold voltage Vth_P of the p-channel transistor 341 . In this way, by setting the potential Va of the input terminal T to a predetermined value before the first period Pa[i], the potential Va of the input terminal T can be quickly and accurately set within the first period Pa[i]. Advantages for the potential Vdata. Furthermore, since the potential between the electro-optical element 35 and the output terminal of the inverter 34 is initialized to a predetermined value, the time required for the response of the electro-optical element 35 can be made uniform among the plurality of unit circuits U.

(C: modified example)

Various modifications can be added to the above technical solutions. If a specific modified technical solution is illustrated, it will be as follows. In addition, it is also possible to appropriately combine the following technical solutions.

(1) Modification 1

In each embodiment, although the configuration in which the reference signal W[i] in the second period Pb[i] is a triangular wave is illustrated, the configuration of the reference signal W[i] in the second period Pb[i] is appropriately changed. waveform. For example, each embodiment exemplifies the reference signal W[i] whose waveform is line-symmetrical with respect to the midpoint tc of the second period Pb[i], but the present invention does not require the reference signal W[i]. ] Symmetry. For example, various waveforms such as a ramp wave, a sawtooth wave (sawtooth wave) or a multi-ramp wave (staircase wave) are applied to the reference signal W[i] in the second period Pb[i]. Furthermore, not only a waveform in which the potential changes linearly but also a waveform in which the potential changes in a curve such as a sine wave may be applied to the reference signal W[i] in the second period Pb[i].

In addition, in each embodiment, although the configuration in which the reference signal W[i] becomes a waveform of one period of a triangular wave in the second period Pb[i] is exemplified, the triangular wave or the above-described ramp may be used as an example. Waveforms or sawtooth waves and other various unit waveforms that are continuous in the second period Pb[i] (that is, waveforms that arrange multiple unit waveforms on the time axis in the manner of repeating the rise and fall of potential multiple times) are applied to Reference signal W[i]. In this way, in the present invention, the reference signal W[i] whose potential fluctuates with the passage of time in the second period Pb[i] can be appropriately selected according to the driving form or function of the electro-optical element 35, etc.

Furthermore, in each embodiment, the configuration in which the potential Va of the input terminal T starts to fluctuate from the potential Vdata in the first period Pa[i] when the second period Pb[i] starts is exemplified. The waveform of the reference signal W[i] is selected so that the potential Va of the input terminal T varies at the start point and the end point of the second period Pb[i]. For example, a reference signal W[i] as illustrated in FIG. 6 may also be used. The reference signal W[i] in the figure is that the starting point potential of the second period Pb[i] only rises by the amount of change Vd, and the end point potential of the second period Pb[i] drops by only the amount of change Vd, and from the second period Pb[i] During the period from the start point to the end point of the period Pb[i], the voltage falls and rises within the range of the voltage ΔV similarly to the first embodiment. The potential Va of the input terminal T fluctuates according to the waveform of the reference signal W[i]. That is, as shown in FIG. 6, the potential Va, first, rises only by an amount of change Vd from the potential Vdata at the starting point of the second period Pb[i]; The change amount ΔV is increased only by the change amount ΔV in the interval from the midpoint tc to the end point; thirdly, only Vd is decreased at the end point of the second period Pb[i] to become the potential Vdata. Also in this configuration, as in the respective embodiments, the drive current Sdr is output from the inverter 34 for a period of time corresponding to the data signal X[i].

(2) Modification 2

The specific structure of the unit circuit U is not limited to the illustration in FIG. 3 . For example, the conductivity type of each transistor can be changed arbitrarily from the illustration in FIG. 3 . In addition, although the structure in which the output terminal of the inverter 34 is directly connected to the anode of the electro-optical element 35 is illustrated in each embodiment, as shown in FIG. The gate is connected to the output terminal of the inverter 34. The transistor 39 is a mechanism for generating a driving current Sdr, and is inserted between a power supply line supplied with a power supply potential Vdd and the anode of the electro-optical element 35 . When the transistor 341 is turned on and the power supply potential Vdd is output from the inverter 34, the transistor 39 is turned on. At this time, a drive current Sdr flows in the electro-optical element 35 to emit light. Conversely, when the ground potential Vss is output from the inverter 34, since the transistor 39 is turned off, the supply of current is stopped, and the electro-optical element 35 is turned off. Also with such a configuration, the same operations and effects as those of the respective embodiments can be achieved.

Furthermore, the means for outputting the driving current Sdr (the driving means in the present invention) is not limited to the inverter 34 . For example, instead of the inverter 34 shown in FIG. 3 , FIG. 5 and FIG. 7 , a comparator that compares the potential Va of the input terminal T with a predetermined potential and outputs the drive current Sdr corresponding to the result may be provided. This comparator outputs a power supply potential Vdd when the potential Va is lower than a predetermined potential, and outputs a ground potential Vss when the potential Va exceeds a predetermined potential, for example. This configuration also achieves the same operations and effects as those of the respective embodiments. In addition, the signal supplied to the electro-optical element 35 may be a current signal (the driving current Sdr exemplified in each embodiment) or a voltage signal. According to the above description, the driving mechanism in the present invention only needs the driving signal (driving current Sdr and driving voltage) corresponding to the potential Va of the input terminal T (more specifically, corresponding to the magnitude between the potential Va and the specified potential) The elements of the output will do, regardless of the more specific structure.

(3) Modification 3

In each of the embodiments, although a structure in which the reference signal lines 19 are formed so as to correspond to a plurality of scanning lines 13 (that is, for each row) is illustrated, the correspondence relationship between the scanning lines 13 and the reference signal lines 19 is not limited. here. For example, the configuration may be such that reference signal lines 19 are formed corresponding to groups of m scanning lines 13 divided into predetermined numbers, and each reference signal line 19 is connected to each unit circuit U belonging to one group. In this configuration, the data signal X[i] is captured for each row, while the electro-optical element 35 is varied for each group according to the variation of the reference signal W[i].

(4) Modification 4

In the second embodiment, although the structure in which the input terminal T of the inverter 34 is electrically connected to its output terminal before the first period Pa[i] is exemplified, the connection destination of the input terminal T of the inverter 34 is Can be changed appropriately. For example, a transistor 37 may be interposed between the wiring maintaining a predetermined potential and the input terminal T of the inverter 34, and the inverting The input terminal T of the device 34 is initialized to a predetermined potential.

(5) Modification 5

In the above technical solution, although the OLED element is illustrated as the electro-optical element 35 , the electro-optical element used in the electronic device of the present invention is not limited thereto. For example, instead of OLED elements, inorganic EL elements, field/emission (emission) (FE) elements, surface conduction type emission (SE: Surface-conduction Electron-emitter) elements, ballistic electron emission (BS: Ballistic electron Surface emitting) components, various self-luminous components such as LED (Light Emitting Diode, light emitting diode) components, and various electro-optical components such as electrophoretic components or electroluminescent components. In addition, the present invention is also applied to sensing devices such as biochips. The driven element in the present invention includes all elements driven by application of electric energy, and electro-optical elements such as light emitting elements are merely examples of driven elements.

(A. Third Embodiment)

8 is a block diagram showing the configuration of an electronic device in a third embodiment of the present invention. The electronic device D illustrated in this figure is an electro-optical element used in various electronic devices as a device for displaying images, and includes: an element array section 10 in which a plurality of unit circuits U are arranged in a planar shape; Scanning line driving circuit 23 and signal line driving circuit 25 for driving each unit circuit U; and voltage control circuit 27 for supplying voltage A to each unit circuit U. In addition, the scanning line driving circuit 23, the signal line driving circuit 25, and the voltage control circuit 27 may be installed in the electronic device D as separate circuits, or a part or all of these circuits may be installed as a single circuit. In electronic device D.

As shown in FIG. 8, in the element array section 10, m scanning lines 13 extending in the X direction and n signal lines (data lines) 15 extending in the Y direction perpendicular to the X direction are formed (m and n are both is a natural number). Each unit circuit U is arranged at a position corresponding to the intersection of the scanning line 13 and the signal line 15 . Therefore, these unit circuits U are arranged in a matrix of m rows x n columns.

In the element array section 10 , m voltage supply lines 17 extending in the X direction are formed to oppose the respective scanning lines 13 . These voltage supply lines 17 are commonly connected to output terminals of the voltage control circuit 27 . Therefore, the voltage A output from the voltage control circuit 27 is commonly supplied to a plurality of unit circuits U via the respective voltage supply lines 17 .

FIG. 9 is a timing chart for explaining the operation of the electronic device D. As shown in FIG. As shown in the figure, in this embodiment, one frame (1F) is divided into a writing period Pwrt and a driving period Pdrv. In addition, in the present embodiment, the case where the length of the writing period Pwrt and the length of the driving period Pdrv are approximately equal is exemplified, but the ratio of the lengths of the respective periods can be changed arbitrarily.

As shown in FIG. 9 , the voltage control circuit 27 sets the voltage A of each voltage supply line 17 to a voltage value Vss in a writing period Pwrt, and to a voltage value Vdd in a subsequent driving period Pdrv. The voltage value Vss in the present embodiment is a potential (ground potential) serving as a reference for the voltage of each part. The voltage value Vdd is a voltage higher in potential than the voltage value Vss (for example, on the higher side of the power supply potential).

The scanning line driving circuit 23 in FIG. 8 is a circuit for sequentially selecting each of the m scanning lines 13 (selecting a plurality of unit circuits U in units of rows) in a predetermined order during the writing period Pwrt. To describe in further detail, as shown in FIG. 9 , the scanning line driving circuit 23 generates scanning signals S[1] to S[ m] and output to each scan line 13. The scanning signal S[i] supplied to the scanning line 13 of the i-th row (i is an integer satisfying 1≤i≤m) becomes high during the i-th horizontal scanning period (1H) in the writing period Pwrt Level; a signal that maintains a low level during periods other than this (including the driving period Pdrv). The transition of the scan signal S[i] to a high level means that the i-th row is selected.

On the other hand, the signal line driving circuit 25 in FIG. 8 supplies signals D[1] to D[ n]. As shown in FIG. 9, the signal D[j] supplied to the signal line 15 of the jth column (j is an integer satisfying 1≤j≤n) becomes the data voltage Vdata in the writing period Pwrt; The inside of Pdrv becomes the voltage signal of the control voltage Vctl.

As shown in FIG. 9 , the data voltage Vdata changes sequentially every horizontal scanning period according to the gradation (brightness) specified in each unit circuit U. To describe in further detail, the data voltage Vdata of the signal D[j] becomes the same as that specified in the unit circuit U of the jth column belonging to the ith row in the ith horizontal scanning period of the writing period Pwrt. The voltage value corresponding to the gray scale. The gradation of each unit circuit U is specified by gradation data supplied from the outside.

On the other hand, the voltage value of the control voltage Vctl changes with time during the driving period Pdrv. The control voltage Vctl in this embodiment is a waveform from the midpoint tc of the driving period Pdrv (that is, a time equal to the time from both the start point and the end point of the drive period Pdrv) to the start point and the waveform from the midpoint tc to the end point, A triangular wave that is line-symmetric with respect to the midpoint tc. That is, as shown in FIG. 9, the control voltage Vctl rises linearly with time from the start point to the middle point tc of the driving period Pdrv from the voltage value VL to a voltage value VH at a higher potential. From the point tc to the end point, the voltage value VH decreases linearly with time and reaches the voltage value VL.

Next, a specific configuration of each unit circuit U will be described with reference to FIG. 10 . In addition, in this figure, although only one unit circuit U located in the i-th row and the j-th column is shown, other unit circuits U have the same configuration.

As shown in FIG. 10 , the unit circuit U includes an electro-optical element 11 , a driving transistor Tdr, a transistor T1 and a capacitive element C. Among them, the electro-optical element 11 is an element to be driven in the electronic device D (hereinafter referred to as "driven element"). The electro-optical element 11 of the present embodiment is a current-driven light-emitting element that emits light with a luminance corresponding to a supplied current (hereinafter referred to as "driving current"). In this embodiment, as the electro-optical element 11 , an OLED element in which a light-emitting layer made of an organic EL (ElectroLuminescent) material is interposed between an anode and a cathode is used. The cathodes of the electro-optical elements 11 in the unit circuits U are commonly grounded (voltage value Vss). The electro-optical element 11 emits light by applying a forward voltage exceeding the threshold voltage Vth_EL.

The driving transistor Tdr in FIG. 10 is an n-channel transistor for controlling the current value of the driving current. More specifically, the drive transistor Tdr generates a current corresponding to the gate voltage Vg by changing the gate voltage (hereinafter referred to as "gate voltage") Vg according to the electrical conduction state between the source and the drain. The size of the drive current I1. Therefore, the electro-optical element 11 is driven with a brightness corresponding to the on state of the drive transistor Tdr (that is, a brightness corresponding to the gate voltage Vg).

In addition, in this embodiment, since the voltage values of the source and the drain of the driving transistor Tdr are sequentially reversed, in a strict sense, the drain and the source of the driving transistor Tdr are randomly alternated. Therefore, in the following, for convenience of explanation, the voltage at each terminal of the driving transistor Tdr when the driving current I1 is supplied to the electro-optical element 11 through the driving transistor Tdr is taken as a reference. The terminal is marked as "source (S)", and the terminal on the opposite side is marked as "drain "D""

The drive transistor Tdr is interposed between the electro-optical element 11 and the voltage supply line 17 . That is, the drain of the drive transistor Tdr is connected to the voltage supply line 17 , and the source thereof is connected to the anode of the electro-optical element 11 . The source of the drive transistor Tdr is directly connected to the electro-optical element 11 . That is, no switching element is intervened on the path of the drive current 11 from the source of the drive transistor Tdr to the anode of the electro-optical element 11 .

The transistor T1 is an n-channel transistor interposed between the source and the drain of the drive transistor Tdr and controlling the electrical connection of both. The gate of this transistor T1 is connected to the scanning line 13 . Therefore, during the period when the scanning signal S[i] maintains a high level (the i-th horizontal scanning period), the transistor T1 is switched to an on state, the driving transistor Tdr is diode-connected, and when the scanning signal S[i] is switched to a low level level, the transistor T1 is turned off, and the diode connection of the drive transistor Tdr is released.

As shown in FIG. 10 , the capacitive element C includes a first electrode Ea and a second electrode Eb opposite to each other and a dielectric in the gap between the two electrodes. The first electrode Ea is connected to the gate of the driving transistor Tdr. The second electrode Eb is connected to the signal line 15 . The capacitive element C is a mechanism for holding charges corresponding to the potential difference between the first electrode Ea and the second electrode Eb (that is, the potential difference between the signal line 15 and the gate of the driving transistor Tdr).

Next, specific operations of the electronic device D will be described with reference to FIGS. 11 and 12 . Hereinafter, the operation of the j-th column unit circuit belonging to the i-th row will be described by dividing it into a writing period Pwrt and a driving period Pdrv.

(a) Pwrt during writing (Figure 11)

When the scanning signal S[i] transitions to high level in the writing period Pwrt, the transistor T1 is turned on, and the source and gate of the driving transistor Tdr are electrically connected (diode connection). On the other hand, in the writing period Pwrt, the voltage A of the voltage supply line 17 maintains the voltage value Vss. That is, since the voltage A of the voltage supply line 17 becomes lower than the voltage value of the source or the gate of the driving transistor Tdr, during the writing period Pwrt, as shown in FIG. The gate flows into the voltage supply line 17 after passing through the source and drain of the transistor T1 and the drive transistor Tdr in this order.

In this embodiment, the structures and materials of the electro-optical element 11 and the driving transistor Tdr are selected so that the threshold voltage Vth_EL of the electro-optical element 11 is higher than the threshold voltage Vth_TR of the driving transistor Tdr. That is, the voltage (Vss+Vth_TR) at the source of the driving transistor Tdr in the writing period Pwrt is lower than the threshold voltage Vth_EL of the electro-optical element 11 . Therefore, during the writing period Pwrt, no current flows through the electro-optical element 11, so that the electro-optical element 11 is turned off.

According to the above, when the current I0 flows in the driving transistor Tdr, the gate voltage Vg of the driving transistor Tdr (in other words, the voltage of the first electrode Ea) converges to An added value (Vss+Vth_TR) between the voltage value Vss and the threshold voltage Vth_Tr of the driving transistor Tdr. On the other hand, in the horizontal scanning period, the data voltage Vdata of the signal D[j] is supplied to the first electrode Ea. Still maintaining such a voltage relationship, when the horizontal scanning period passes and the scanning signal S[i] transitions to a low level, the transistor T1 is turned off, and the first electrode Ea of the capacitive element C is in a floating state. Therefore, the potential difference between the first electrode Ea (Vss+Vth_TR) and the second electrode Eb (Vdata) at the time when the scan signal S[i] transitions to low level is held in the capacitive element C.

In the write period Pwrt, as described above, the operation for accumulating charges corresponding to the data voltage Vdata and the threshold voltage Vth_TR in the capacitive element C is performed for each unit circuit U from the i-th row to the n-th row. Repeated in sequence during the horizontal scan.

(b) Pdrv during driving (Figure 12)

In the driving period Pdrv, since the scanning signals S[1] to S[m] maintain the low level, the transistors T1 of all the unit circuits U are turned off, and the diode connection of the driving transistor Tdr is released. Therefore, the first electrodes Ea of the capacitive elements C in all the unit circuits U maintain a suspended state. On the other hand, in the driving period Pdrv, the voltage control circuit 27 maintains the voltage A of the voltage supply line 17 at the voltage value Vdd.

In the above case, the control voltage Vctl that changes with time is supplied to the second electrode Eb of the capacitive element C of each unit circuit U via each signal line 15 . Here, since the first electrode Ea becomes in a floating state, the gate voltage Vg of the drive transistor Tdr (that is, the voltage of the first electrode Ea) is only changed by the capacitive coupling with the second electrode Eb due to the capacitive coupling generated by the capacitive element C. Voltage variation corresponding to the voltage value ΔV. The relationship between the voltage change of the first electrode Ea and the driving current I1 is described in detail as follows.

First, when the control voltage Vctl applied to the second electrode Eb in the driving period Pdrv becomes a higher potential than the data voltage Vdata applied in the previous writing period Pwrt, the gate voltage Vg of the driving transistor Tdr (the first The voltage of the first electrode Ea) increases from the voltage value (Vss+Vth_TR) set in the writing period Pwrt by a voltage value ΔV corresponding to the difference between the control voltage Vctl and the data voltage Vdata. At this time, since the drive transistor Tdr is turned on, as shown in FIG. 12 , the drive current I1 is supplied from the voltage supply line 17 to the electro-optical element 11 via the drive transistor Tdr. Then, the electro-optical element 11 emits light by the supply of the drive current I1.

On the other hand, when the control voltage Vctl applied to the second electrode Eb during the driving period Pdrv becomes a potential lower than the data voltage Vdata applied in the previous writing period Pwrt, the gate voltage Vg of the driving transistor Tdr, Only the voltage value ΔV corresponding to the difference between the data voltage Vdata and the control voltage Vctl is dropped from the voltage value (Vss+Vth_TR) set in the writing period Pwrt. At this time, since the drive transistor Tdr is turned off (non-conductive), the path from the voltage supply line 17 to the electro-optical element 11 is cut off, and the electro-optical element 11 is turned off.

In this way, the driving transistor Tdr of each unit circuit U in the driving period Pdrv is turned on while the control voltage Vctl is higher than the data voltage Vdata, and is turned on when the control voltage Vctl is higher than the data voltage Vdata. It becomes off state during the period of low potential. That is, the electro-optical element 11 of each unit circuit U emits light for a period of time corresponding to the voltage value of the data voltage Vdata in the driving period Pdrv, and turns off the light during the remaining period of the driving period Pdrv. Therefore, each electro-optical element 11 is controlled to have a gradation (integrated value of luminance in the driving period Pdrv) corresponding to the data voltage Vdata (gradation control by pulse width modulation)

As described above, in the present embodiment, the gate voltage Vg of the drive transistor Tdr is set to a voltage value corresponding to the threshold voltage Vth_TR in the writing period Pwrt. In other words, the driving transistor Tdr, regardless of the threshold voltage Vth_TR, can be forcibly shifted to the boundary state between the conduction state and the non-conduction state. Therefore, the driving transistor Tdr is turned on in the driving period Pdrv, and the length of time for supplying the driving current I1 to the electro-optical element 11 is determined by the data voltage Vdata, not depending on the threshold voltage Vth_TR of the driving transistor Tdr. That is, according to the present embodiment, the error (difference from the design value) of the threshold voltage Vth_TR of the driving transistor Tdr can be compensated, and the electro-optical element 11 can be controlled to a desired gradation with high precision.

In addition, in the present embodiment, the total number of transistors included in one unit circuit U is "2". Therefore, compared with the structure of Patent Document 1 in which at least three transistors are indispensable for each unit circuit in order to compensate for variations in the threshold voltage of the driving transistor Tdr, the structure of the electronic device D can be simplified. In addition, the aperture ratio of each unit circuit U (the ratio of the area where the radiated light from the electro-optical element 11 exits in the area where the unit circuits U are distributed) can be increased.

However, as each transistor (in particular, the drive transistor Tdr) constituting the unit circuit U, for example, a thin film transistor using polycrystalline silicon/microcrystalline silicon/single crystal silicon or amorphous silicon as the material of the semiconductor layer, or a transistor made of bulk silicon can be used. (bulk silicon) formed transistors. Among these transistors, especially a transistor whose semiconductor layer is formed of amorphous silicon, it is known that if the direction of current flowing therein is always fixed, the threshold voltage will fluctuate over time.

In the configuration of this embodiment, in contrast to the drive current I1 flowing from the drain to the source of the drive transistor Tdr during the drive period Pdrv, the current I0 flows from the source to the drain during the write period Pwrt as shown in FIG. 1 . . That is, the direction of the current flowing in the driving transistor Tdr is reversed in the writing period Pwrt and the driving period Pdrv. Therefore, according to the present embodiment, in a structure in which a thin-film transistor whose semiconductor layer is composed of amorphous silicon is used as the driving transistor Tdr, it is possible to suppress the temporal variation of the threshold voltage Vth_TR.

(B: fourth embodiment)

Next, a fourth embodiment of the present invention will be described.

In the third embodiment, the current I0 is generated by lowering the voltage A of the voltage supply line 17 to Vss in the writing period Pwrt so that the gate voltage Vg of the drive transistor Tdr converges to a value corresponding to the threshold voltage Vth_TR. The structure of the voltage value (Vss+Vth_TR). However, when the source voltage of the drive transistor Tdr accidentally drops below the voltage value Vss due to some disturbance such as noise, no current I0 will be generated even if the voltage A is lowered to the voltage value Vss. The voltage Vg does not converge to a voltage value corresponding to the threshold voltage Vth_TR. In order to solve such a problem, in the present embodiment, the source voltage of the driving transistor Tdr is forcibly set to a voltage value capable of generating the current I0. In addition, about the same elements in this embodiment as those in the third embodiment, common reference numerals are assigned to them, and explanations thereof are appropriately omitted.

FIG. 13 is a circuit diagram showing the configuration of the unit circuit U in this embodiment. As shown in the figure, the unit circuit U of the present embodiment includes a p-channel transistor T2 in addition to the elements shown in FIG. 10 . This transistor T2 is a mechanism for setting the voltage Vn at the connection point N (the source of the driving transistor Tdr or the anode of the electro-optical element 11) between the driving transistor Tdr and the electro-optical element 11 to a voltage value Vdd, and is Inserted between the connection point N and the voltage supply line 17 . The gate of the transistor T2 is paired with the scanning line 13 and connected to the reset signal line 141 extending in the X direction. A common reset signal RSa is supplied from the scanning line driver circuit 23 to the reset signal line 141 of each row. However, a circuit that generates a reset signal RSa and outputs it to each reset signal line 141 may be provided separately from the scanning line driving circuit 23 .

Next, FIG. 14 is a timing chart showing the operation of the electronic device D in this embodiment. As shown in the figure, one frame (1F) includes an initialization period Prs1 before the writing period Pwrt in addition to the writing period Pwrt and the driving period Pdrv. The voltage A of each voltage supply line 17 is set to the voltage value Vss in the writing period Pwrt, and is set to the voltage value Vdd in the initializing period Prs1 and the driving period Pdrv.

The reset signal RSa supplied to each reset signal line 141 becomes low level in the initializing period Prs1, and maintains high level in periods other than this (writing period Pwrt or driving period Pdrv). In addition, the scanning line driving circuit 23 makes all the scanning signals S[1] to S[m] transition to high level at once in the initializing period Prs1. The scanning signals S[1] to S[m] in the writing period Pwrt or the driving period Pdrv are the same as those in the first embodiment.

FIG. 15 is a circuit diagram showing an appearance of one unit circuit U in the initialization period Prs1. As shown in the figure, in the initialization period Prs1 , the transistor T1 is kept on due to the high-level scan signal S[i], and the transistor T2 is kept on due to the low-level reset signal RSa. That is, the connection point N and the gate of the driving transistor Tdr are electrically connected to the voltage supply line 17 via the transistor T2. At this time, the voltage A of the voltage supply line 17 is set to the voltage value Vdd. Therefore, in the initialization period Prs1 , as shown in FIG. 15 , the voltage Vn of the connection point N and the gate voltage Vg of the driving transistor Tdr are forcibly set to the voltage value Vdd. In the initializing period Prs1 , since the transistor T1 and the transistor T2 are turned on, it is set to be long enough for the voltage Vn of the connection point N to reach the voltage value Vdd.

Operations in the writing period Pwrt and the driving period Pdrv are the same as those in the third embodiment. According to this embodiment, in the initializing period Prs1 before the writing period Pwrt, the voltage Vn of the connection point N is set to be higher than the voltage value Vss of the voltage supply line 17 in the writing period Pwrt and the threshold value of the driving transistor Tdr. The added value between the voltages Vth_TR is higher than the voltage value Vdd, so even if the voltage Vn falls below the voltage value Vss before the initialization period Prs1, the current I0 can be properly transferred from the drive transistor Tdr to the voltage value in the writing period Pwrt. The supply line 17 flows. Therefore, according to this embodiment, in addition to the same effect as that of the first embodiment, the effect of reducing the influence of disturbance such as noise and achieving stable operation can be obtained.

Also, in the initialization period Prs1, since the voltage value (Vdd) of the voltage Vn exceeds the threshold voltage Vth_EL, the electro-optical element 11 emits light. However, if the length of the initialization period Prs1 is sufficiently shorter than that of the writing period Pwrt or the driving period Pdrv, the light emission of the electro-optical element 11 in this initialization period Prs1 actually hardly affects the gray seen by the observer. degree of impact. In addition, although this embodiment exemplifies the case where the initialization period Prs1 is set before each writing period Pwrt, the timing of the initialization period Prs1 is arbitrary. For example, the initialization period Prs1 may be set every multiple frames, and the voltage Vn may be initialized.

In addition, as shown in FIG. 16 , the structure may be such that the scan signal S[i] is switched from the time when the initializing period Prs1 rises to the high level to the time when the end of the first horizontal scanning period falls to the low level. maintain high level. The amount of charge held in the capacitive element C of the unit circuit U in the i-th row is determined at the moment after the scanning signal S[i] falls to the low level (that is, the end of the i-th horizontal scanning period). Therefore, even according to the driving method shown in FIG. 16 , it is possible to compensate the error in the threshold voltage Vth_TR and control the electro-optical element 11 to a gradation corresponding to the data voltage Vdata similarly to the third embodiment or the present embodiment. In addition, according to the method of FIG. 16 , since the number of times of changing the level of the scanning signal S[i] is reduced compared with the method of FIG. 14 , there is an advantage that the power consumed by the scanning line driving circuit 23 can be reduced. On the other hand, according to the method of FIG. 14 , since the pulse width of the scanning signal S[i] in each initialization period Prs1 and writing period Pwrt can be the same value in the entire row, it is possible to generate the scanning signal. The advantage of the simplification of the structure of S[i].

(C: fifth embodiment)

Next, a fifth embodiment of the present invention will be described.

In the fourth embodiment, since the voltage Vn of the connection point N is set to the voltage value Vdd, the configuration in which the voltage supply line 17 is also used is exemplified. On the contrary, in the present embodiment, the voltage Vn is forcibly set to a predetermined value by conducting the connection point N with a wiring other than the voltage supply line 17 . In addition, about the same elements in this embodiment as those in the third embodiment, common reference numerals are assigned to them, and explanations thereof are appropriately omitted.

FIG. 17 is a circuit diagram showing the configuration of the unit circuit U in this embodiment. Like the fourth embodiment, the unit circuit U of this embodiment includes a transistor T2 for setting the voltage Vn of the connection point N to a predetermined value (here, Vdd). This transistor T2 is inserted between the connection point N and the power supply line 18 . The power supply line 18 is a wiring extending in the X direction that is opposite to the scanning line 13 . The voltage of the power supply line 18 of each row is always fixed at the voltage value Vdd by the voltage control circuit 27 . In addition, the configuration may be such that a circuit for supplying a voltage (Vdd) to the power supply line 18 is provided separately from the voltage control circuit 27 . The gate of the transistor T2 is connected to the reset signal line 141 as in the fourth embodiment.

FIG. 18 is a timing chart for explaining the operation of the electronic device D according to this embodiment. Like the fourth embodiment, one frame (1F) in this embodiment includes, in addition to the writing period Pwrt and the driving period Pdrv, an initialization period Prs1 preceding the writing period Pwrt. The voltage A of each voltage supply line 17 is set to the voltage value Vdd in the driving period Pdrv, and is set to the voltage value Vss in the initialization period Prs1 and the writing period Pwrt. On the other hand, the waveforms of the scan signal S[i] and the reset signal RSa are the same as those of the fourth embodiment ( FIG. 14 ). However, it is also possible to use the scanning signals S[1] to S[m] with waveforms illustrated in FIG. 16

FIG. 19 is a circuit diagram showing an appearance of one unit circuit U in the initialization period Prs1. As shown in the figure, when the transistor T1 and the transistor T2 are turned on during the initialization period Prs1, the connection point N and the gate of the driving transistor Tdr are electrically connected to the power supply line 18 via the transistor T2. Since the voltage of the power supply line 18 is fixed at the voltage value Vdd, in the initialization period Prs1, as shown in FIG. . Therefore, also according to this embodiment, the same effect as that of the fourth embodiment can be achieved.

In addition, in the present embodiment, the voltage A of the voltage supply line 17 in the initialization period Prs1 can be set to the voltage value Vss. This is different from the fourth embodiment because the power supply line 18 for setting the connection point N to the voltage value Vdd in the initialization period Prs1 is formed separately from the voltage supply line 17 . In this way, in the present embodiment, since the voltage supply line 17 is set to the voltage value Vss (see FIG. 19 ) in the initialization period Prs1 , the drive current I1 is not supplied to the electro-optical element 11 in the initialization period Prs1 . In other words, as shown in FIG. 18 , at the end of the driving period Pdrv, since the voltage A of the voltage supply line 17 drops to the voltage value Vss, the electro-optical element 11 stops emitting light. Therefore, according to this embodiment, compared with the fourth embodiment in which the electro-optical element 11 can emit light even in the initialization period Prs1, it is advantageous in that the period during which each electro-optical element 11 emits light can be specified with high precision and can be respectively control in the desired grayscale. However, according to the fourth embodiment, since the voltage Vn of the connection point N is set to the voltage value Vdd, the voltage supply line 17 is also used, and therefore the dedicated power supply line 18 for initialization of the voltage Vn is not required. Therefore, there is an advantage of simplifying the structure of the unit circuit U.

(D: sixth embodiment)

Next, a sixth embodiment of the present invention will be described.

With the configuration of the third embodiment, the electric charge stored in the capacitive element C in the writing period Pwrt remains until the start of the writing period Pwrt of the next frame. Therefore, in some cases, the amount of charge (or gate voltage Vg) stored in the capacitive element C during the writing period Pwrt of a certain frame is affected by the charge stored in the capacitor during the writing period Pwrt of the previous frame. The effect of the amount of charge in element C. Therefore, in the present embodiment, before the write period Pwrt, the gate voltage Vg of the drive transistor Tdr is forcibly set to a predetermined value. Components in this embodiment that are the same as those in the first embodiment are assigned the same reference numerals, and descriptions thereof are appropriately omitted.

FIG. 20 is a circuit diagram showing the configuration of the unit circuit U in this embodiment. As shown in the figure, the unit circuit of this embodiment includes a p-channel transistor T3 in addition to the elements shown in FIG. 10 . This transistor T3 is a mechanism for setting the gate voltage Vg of the driving transistor Tdr to the voltage value Vdd, and is inserted between the voltage supply line 17 and the gate of the driving transistor Tdr. The gate of the transistor T3 is connected to the reset signal line 142 extending in the X direction. A common reset signal line RSb is supplied from the scanning line driver circuit 23 to the reset signal line 142 of each row. In addition, the configuration may be such that a circuit that generates a reset signal RSb and outputs it to each reset signal line 142 may be provided separately from the scanning line driving circuit 23 .

FIG. 21 is a timing chart for explaining the operation of the electronic device D in this embodiment. As shown in the figure, each frame includes an initialization period Prs2 before the writing period Pwrt. The voltage A of each voltage supply line 17 is set to the voltage value Vss in the writing period Pwrt, and is set to the voltage value Vdd in the initializing period Prs2 and the driving period Pdrv, as in the second embodiment. On the other hand, the reset signal RSb transitions to a low level during the initialization period Prs2, and maintains a high level during other periods. In addition, the waveforms of the scan signals S[1] to S[m] are the same as those in the first embodiment.

FIG. 22 is a circuit diagram showing the appearance of the unit circuit U in the initialization period Prs2. As shown in the figure, in the initialization period Prs2, since the reset signal RSb transitions to low level, the transistor T3 transitions to the on state, and the gate of the driving transistor Tdr is electrically connected to the voltage supply line 17 . Therefore, the gate voltage Vg of the driving transistor Tdr is set to the voltage value Vdd supplied to the voltage supply line 17 at this point in time. Operations in the writing period Pwrt and the driving period Pdrv are the same as those in the third embodiment.

As described above, in the present embodiment, since the gate voltage Vg is initialized to the voltage value Vdd before the writing period Pwrt, regardless of the amount of charge stored in the capacitive element C in the previous frame, in each writing period Pwrt can correctly store the charge corresponding to the data voltage Vdata in the capacitive element C. Therefore, according to the present embodiment, compared with the first embodiment, each electro-optical element 11 can be controlled to a desired gradation with high precision.

(E: modified example)

Various modifications can be added to the above technical solutions. If the specific modification technical solution is illustrated as an example, it will be as follows. In addition, it is also possible to appropriately combine the following technical solutions.

(1) Modification 1

The waveforms of the signals D[1] to D[n] (the waveform of the control voltage Vctl) in the driving period Pdrv are appropriately changed. For example, each embodiment exemplifies a triangular wave whose waveform is line-symmetrical with respect to the midpoint tc of the drive period Pdrv, but various waveforms such as a ramp wave, a sawtooth wave, or a multi-ramp wave (staircase wave) may also be used. As the control voltage Vctl. In addition, not only a waveform in which the voltage value changes linearly, but also a waveform in which the voltage value changes in a curve such as a sine wave may be used as the control voltage Vctl.

In addition, although the configuration in which the control voltage Vctl of the driving period Pdrv becomes a waveform of one cycle of a triangular wave is illustrated in each embodiment, it is also possible to use various unit waveforms such as a triangular wave or the ramp wave or sawtooth wave exemplified above. A plurality of waveforms (that is, waveforms that repeat the rise and fall of the voltage many times) that are continuous within the driving period Pdrv are applied to the control voltage Vctl. In the electronic device D of the present invention, various waveforms in which the voltage fluctuates with time in the driving period Pdrv can be used as the control voltage Vctl.

(2) Modification 2

In the fourth and fifth embodiments, the configuration in which the voltage Vn of the connection point N is set to the voltage value Vdd in the initialization period Prs1 is illustrated, but in the initialization period Prs1 is set to the voltage of the voltage Vn The value can be changed appropriately. However, from the viewpoint that the current I0 flows accurately during the writing period Pwrt in which the voltage A of the voltage supply line 17 becomes the voltage value Vss, it is preferable that the voltage Vn of the initializing period Prs1 is set to be equal to the voltage value Vss A voltage value having a higher potential than the added value (Vss+Vth_TR) of the threshold voltage Vth_TR of the drive transistor Tdr.

In addition, in the sixth embodiment, the structure in which the gate voltage Vg is set to the voltage value Vdd in the initialization period Prs2 is illustrated, but the voltage value of the gate voltage Vg in the initialization period Prs2 is arbitrary. of. For example, a configuration may be adopted in which the voltage A of the voltage supply line 17 in the initialization period Prs2 is set as the voltage value Vss, and the gate voltage Vg in the initialization period Prs2 is set as the voltage value Vss.

(3) Modification 3

The structure of each unit circuit U can be changed appropriately. More specifically, the conductivity type of the transistors constituting the unit circuit U in each embodiment is arbitrary. For example, the transistor T1 of the third embodiment may be of a p-channel type, and the transistor T2 of the fourth and fifth embodiments, or the transistor T3 of the sixth embodiment may be of an n-channel type.

Furthermore, although the drive transistor Tdr has been illustrated as having an n-channel structure in each embodiment, the drive transistor Tdr may also have a p-channel structure. In the structure using the p-channel drive transistor Tdr, even if the voltage A of the voltage supply line 17 does not change during the writing period Pwrt and the driving period Pdrv, the same operations and effects as those of the respective embodiments can be achieved. In this structure, in the writing period Pwrt (the voltage A is the same voltage value Vdd as the driving period Pdrv), when the transistor T1 is turned on, the drain voltage of the driving transistor Tdr (that is, the anode of the electro-optical element 11 ), which is set as the value (Vdd−Vth_TR) obtained by subtracting the threshold voltage Vth_TR from the voltage value Vdd.

(4) Modification 4

In the above technical solution, although the OLED element is illustrated as the electro-optical element 11 , the electro-optical element used in the electronic device of the present invention is not limited thereto. For example, instead of OLED elements, inorganic EL elements, field/emission (FE) elements, surface conduction type emission elements, ballistic electron emission elements (BS: Ballistic electron Surface emitting) elements, and LED (Light Emitting Diode) elements can also be used. Various self-luminous elements, as well as various electro-optical elements such as electrophoretic elements, electroluminescent elements, and liquid crystal elements. In addition, the present invention can also be applied to sensor devices such as biochips. The driven element of the present invention is a concept including all elements driven by application of electric energy, and electro-optical elements such as light emitting elements are merely examples of driven elements.

(F: Application example)

Next, an electronic device using the electronic device of the present invention will be described.

FIG. 23 is a perspective view showing the structure of a portable personal computer using the electronic device D described above as a display device. The personal computer 2000 includes an electronic device D as a display device and a main body 2010 . In the main body part 2010, a power switch 2001 and a keyboard 2002 are provided. Since the electronic device D uses an OLED element for the electro-optical element 11, it can display an easy-to-view screen with a wide viewing angle.

FIG. 24 shows the structure of a mobile phone to which the electronic device D according to the embodiment is applied. A mobile phone 3000 includes a plurality of operation keys 3001 and scroll keys 3002, and an electronic device D as a display device. The screen displayed on the electronic device D is scrolled by operating the scroll key 3002 .

FIG. 25 shows the configuration of a mobile information terminal (PDA: Personal Digital Assistants) to which the electronic device D in the embodiment is applied. The mobile information terminal 4000 includes a plurality of operation keys 4001, a power switch 4002, and an electronic device D as a display device. Various information such as an address book and a schedule are displayed on the electronic device D when the power switch 4002 is operated.

In addition, as electronic equipment to which the electronic device (electro-optical device) related to the present invention is applied, digital still cameras, televisions, video cameras, car navigation devices, pagers, electronic Notebooks, electronic paper, calculators, word processors, workbenches, TV phones, POS terminals, printers, scanners, copiers, video recorders, machines with touch screens, etc. Moreover, the use of the electronic device in the present invention is not limited to displaying images. For example, in an image forming apparatus such as an optical writing printer or an electronic copier, a writing head that exposes a photoreceptor according to an image to be formed on a recording material such as paper is used, but even as such writing head, the electronic device of the present invention can also be utilized. The term "unit circuit" in the present invention is a concept including not only circuits constituting pixels of a display device (so-called pixel circuits), but also circuits serving as units of exposure in image forming devices.

Claims (31)

1. An electronic device, It includes: a plurality of first wirings; a plurality of second wirings intersecting the plurality of first wirings; and a plurality of units arranged corresponding to intersections between the plurality of first wirings and the plurality of second wirings a circuit; and a plurality of reference signal lines for supplying reference signals to the plurality of unit circuits, Each of the plurality of unit circuits includes: a driven element, which is driven by supply of a driving voltage or a driving current; a drive mechanism that supplies the drive voltage or the drive current to the driven element; a switching element that controls electrical connection between an input terminal included in the driving mechanism and one of the plurality of second wirings; and a capacitive element, which includes a first electrode connected to the input terminal and a second electrode connected to one of the plurality of reference signal lines, between the first electrode and the second electrode store charge. 2. The electronic device according to claim 1, wherein: The plurality of reference signal lines intersect with the plurality of second wirings. 3. The electronic device according to claim 1, wherein: Each potential of the plurality of reference signal lines changes at a predetermined period. 4. The electronic device according to claim 3, characterized in that it comprises: a selection circuit that selects the plurality of first wirings, respectively; and and a signal generation circuit that sequentially supplies the reference signals to the plurality of reference signal lines in the order in which the first wiring is selected. 5. The electronic device according to claim 1, characterized in that, During the first period, the potential of the input terminal is set by supplying a data signal to the input terminal via the one second wiring and the switching element. 6. The electronic device according to claim 5, wherein: A length of a driving period in which the driving voltage or the driving current is supplied to the driven element corresponds to the potential of the input terminal set during the first period. 7. The electronic device according to claim 5 or 6, characterized in that, The potential of the input terminal fluctuates from the potential set by the data signal during the first period in accordance with a change in the potential of the one reference signal line. 8. The electronic device according to claim 7, wherein: The input terminal is in a floating state during at least a part of a driving period in which the driving voltage or the driving current is supplied to the driven element. 9. The electronic device according to claim 5, wherein: In the first period, the potential of the input terminal set by the data signal exceeds a predetermined potential and the period in which the potential of the input terminal is lower than a predetermined potential sets the The drive voltage or the drive current is supplied to the driven element. 10. The electronic device according to claim 9, wherein: The potential of the one reference signal line is set to at least a first potential when the potential of the input terminal is set according to the data signal in the first period, The potential of the one reference signal line at the start of the second period is the first potential, the one reference signal line becomes a second potential having a different voltage level from the first potential during the second period, The potential of the one reference signal line at the end of the second period is the first potential. 11. The electronic device according to claim 10, wherein: A change in the potential of the one reference signal line during the second period is line-symmetric about a time when the one reference signal line becomes the second potential. 12. The electronic device according to claim 1, wherein: Each of the plurality of unit circuits includes a reset mechanism that sets the input terminal to specified potential. 13. An electro-optical device, It has: a plurality of scanning lines; a plurality of data lines intersecting the plurality of scanning lines; a plurality of unit circuits corresponding to the intersections between the plurality of scanning lines and the plurality of data lines; and for a plurality of reference signal lines supplying reference signals to the plurality of unit circuits, Each of the plurality of unit circuits includes: an electro-optical element driven by supply of a driving voltage or a driving current; a drive mechanism that supplies the drive voltage or the drive current to the electro-optical element; a switching element that controls electrical connection between an input terminal included in the drive mechanism and one of the plurality of data lines; and a capacitive element having a first electrode connected to the input terminal and a second electrode connected to one of the plurality of reference signal lines, between the first electrode and the second electrode store charge, The length of a driving period in which the driving voltage or the driving current is supplied to the electro-optical element is the same as the length of the driving period in which data is supplied to the input terminal via the one data line and the switching element during the first period. signal to be set corresponding to the potential of the input. 14. An electronic device comprising the electronic device according to any one of claims 1 to 12 or the electro-optical device according to claim 13. 15. An electronic circuit for driving a driven element, comprising a signal line, a unit circuit connected to the signal line, and a voltage supply line, The unit circuit includes: a driving transistor having a control terminal, a first terminal, and a second terminal connected to the voltage supply line, and setting a conductance between the first terminal and the second terminal according to the voltage of the control terminal pass status; a first switching element that controls electrical connection between the control terminal of the drive transistor and any one of the first terminal and the second terminal; and a capacitive element having a dielectric between a first electrode and a second electrode, the first electrode being connected to the control terminal of the drive transistor, the second electrode being connected to the signal line, A magnitude of at least one of a driving current and a driving voltage supplied to the driven element is set according to a conduction state between the first terminal and the second terminal. 16. An electronic device comprising a signal line, a unit circuit connected to the signal line, and a voltage supply line, The unit circuit includes: a driving transistor having a control terminal, a first terminal, and a second terminal connected to the voltage supply line, and setting a conductance between the first terminal and the second terminal according to the voltage of the control terminal pass status; driven element; a first switching element that controls electrical connection between the control terminal of the drive transistor and any one of the first terminal and the second terminal; and a capacitive element having a dielectric between a first electrode and a second electrode, the first electrode being connected to the control terminal of the driving transistor, the second electrode being connected to the signal line, A magnitude of at least one of a driving current and a driving voltage supplied to the driven element is set according to a conduction state between the first terminal and the second terminal. 17. The electronic device according to claim 16, wherein: The second electrode is directly connected to the signal line. 18. The electronic device according to claim 16 or 17, characterized in that, In the first period, the control terminal of the driving transistor is electrically connected to either one of the first terminal and the second terminal via the first switching element, During the first period, a data signal is supplied to the second electrode via the signal line, In the second period, a control signal that changes with time in the second period is supplied to the second electrode. 19. The electronic device according to claim 18, wherein: The first electrode is in a floating state during at least a part of the second period. 20. The electronic device according to claim 18 or 19, wherein: A voltage control circuit is included that sets the voltage of the voltage supply line to any one of a plurality of voltage values. 21. The electronic device according to claim 20, wherein: The voltage control circuit sets the voltage of the voltage supply line to a first voltage value lower than that of the first terminal during at least a part of the first period, and sets the voltage of the voltage supply line to a first voltage value lower than that of the first terminal during at least a part of the second period. , setting the voltage of the voltage supply line to a second voltage value higher than that of the first terminal. 22. The electronic device according to any one of claims 16 to 21, wherein The first switching element is a switching transistor, The only transistors included in the unit circuit are the drive transistor and the switch transistor. 23. The electronic device according to claim 21, wherein: the driven element is driven when the voltage value of the first terminal exceeds a predetermined voltage value, The first voltage value is determined such that a voltage value of the first terminal during the writing period is lower than the predetermined voltage value. 24. The electronic device according to claim 21, wherein: The unit circuit includes a first reset mechanism for setting the voltage of the first terminal to a predetermined voltage value. 25. The electronic device according to claim 24, wherein: said first reset mechanism comprising a second switching element electrically connecting said first terminal to said voltage supply line during initialization, The voltage control circuit sets the voltage of the voltage supply line to the second voltage value during the initialization period. 26. The electronic device according to claim 24, wherein: the first reset mechanism includes a second switching element electrically connecting the first terminal to a power supply line supplying a constant voltage during initialization, The voltage control circuit sets the voltage of the voltage supply line to the first voltage value during the initialization period. 27. The electronic device according to claim 21, wherein: The unit circuit includes a second reset mechanism for setting the voltage of the control terminal of the drive transistor to a predetermined voltage value. 28. The electronic device according to claim 27, wherein: the second reset mechanism includes a third switching element electrically connecting the control terminal to the voltage supply line during initialization, The voltage control circuit sets the voltage of the voltage supply line to the second voltage value during the initialization period. 29. An electronic device comprising the electronic device according to any one of claims 16 to 28. 30. An electro-optical device comprising a signal line, a unit circuit connected to said signal line, and a voltage supply line, The unit circuit includes: a driving transistor having a control terminal, a first terminal, and a second terminal connected to the voltage supply line, and setting a conductance between the first terminal and the second terminal according to the voltage of the control terminal pass state; Electro-optical components; a first switching element that controls electrical connection between the control terminal of the drive transistor and any one of the first terminal and the second terminal; and a capacitive element having a dielectric between a first electrode and a second electrode, the first electrode being connected to the control terminal of the driving transistor, the second electrode being connected to the signal line, A magnitude of at least one of a driving current and a driving voltage supplied to the electro-optical element is set according to a conduction state between the first terminal and the second terminal. 31. A method for driving an electronic device, for driving an electronic device having a unit circuit, the unit circuit comprising a driving transistor and a driven element, the driving transistor having a control terminal, a first terminal, and a voltage supply line connected and setting the conduction state between the first terminal and the second terminal according to the voltage of the control terminal, During the first period, any one of the first terminal and the second terminal is electrically connected to the control terminal of the driving transistor, and during the first period, the The two electrodes supply data signals, In the second period, a control signal that changes with time in the second period is supplied to the second electrode.

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