DE3462969D1 - Method of manufacturing a semiconductor device having lightly doped regions - Google Patents

Method of manufacturing a semiconductor device having lightly doped regions

Info

Publication number
DE3462969D1
DE3462969D1 DE8484100874T DE3462969T DE3462969D1 DE 3462969 D1 DE3462969 D1 DE 3462969D1 DE 8484100874 T DE8484100874 T DE 8484100874T DE 3462969 T DE3462969 T DE 3462969T DE 3462969 D1 DE3462969 D1 DE 3462969D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
lightly doped
doped regions
lightly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484100874T
Other languages
German (de)
Inventor
Hiroshi Momose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3462969D1 publication Critical patent/DE3462969D1/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE8484100874T 1983-01-27 1984-01-27 Method of manufacturing a semiconductor device having lightly doped regions Expired DE3462969D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58011970A JPS59138379A (en) 1983-01-27 1983-01-27 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
DE3462969D1 true DE3462969D1 (en) 1987-05-07

Family

ID=11792470

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484100874T Expired DE3462969D1 (en) 1983-01-27 1984-01-27 Method of manufacturing a semiconductor device having lightly doped regions

Country Status (4)

Country Link
US (1) US4488351A (en)
EP (1) EP0127725B1 (en)
JP (1) JPS59138379A (en)
DE (1) DE3462969D1 (en)

Families Citing this family (48)

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USRE32800E (en) * 1981-12-30 1988-12-13 Sgs-Thomson Microelectronics, Inc. Method of making mosfet by multiple implantations followed by a diffusion step
US4599118A (en) * 1981-12-30 1986-07-08 Mostek Corporation Method of making MOSFET by multiple implantations followed by a diffusion step
JPH0693494B2 (en) * 1984-03-16 1994-11-16 株式会社日立製作所 Method for manufacturing semiconductor integrated circuit device
US5352620A (en) * 1984-05-23 1994-10-04 Hitachi, Ltd. Method of making semiconductor device with memory cells and peripheral transistors
US4918501A (en) * 1984-05-23 1990-04-17 Hitachi, Ltd. Semiconductor device and method of producing the same
JPS6116571A (en) * 1984-07-03 1986-01-24 Ricoh Co Ltd Manufacture of semiconductor device
US4727038A (en) * 1984-08-22 1988-02-23 Mitsubishi Denki Kabushiki Kaisha Method of fabricating semiconductor device
US4658496A (en) * 1984-11-29 1987-04-21 Siemens Aktiengesellschaft Method for manufacturing VLSI MOS-transistor circuits
US4590665A (en) * 1984-12-10 1986-05-27 Solid State Scientific, Inc. Method for double doping sources and drains in an EPROM
JPS61147571A (en) * 1984-12-21 1986-07-05 Toshiba Corp Manufacturing method of heterojunction bipolar transistor
US4585517A (en) * 1985-01-31 1986-04-29 Motorola, Inc. Reactive sputter cleaning of semiconductor wafer
JPS61191070A (en) * 1985-02-20 1986-08-25 Toshiba Corp Manufacturing method of semiconductor device
US4653173A (en) * 1985-03-04 1987-03-31 Signetics Corporation Method of manufacturing an insulated gate field effect device
US4649629A (en) * 1985-07-29 1987-03-17 Thomson Components - Mostek Corp. Method of late programming a read only memory
JPH0740604B2 (en) * 1985-07-30 1995-05-01 ソニー株式会社 Method for manufacturing MOS semiconductor device
US4843023A (en) * 1985-09-25 1989-06-27 Hewlett-Packard Company Process for forming lightly-doped-drain (LDD) without extra masking steps
US4722909A (en) * 1985-09-26 1988-02-02 Motorola, Inc. Removable sidewall spacer for lightly doped drain formation using two mask levels
US4745086A (en) * 1985-09-26 1988-05-17 Motorola, Inc. Removable sidewall spacer for lightly doped drain formation using one mask level and differential oxidation
DE3576610D1 (en) * 1985-12-06 1990-04-19 Ibm METHOD FOR PRODUCING A FULLY SELF-ADJUSTED FIELD EFFECT TRANSISTOR.
US5247199A (en) * 1986-01-15 1993-09-21 Harris Corporation Process for forming twin well CMOS integrated circuits
US5028554A (en) * 1986-07-03 1991-07-02 Oki Electric Industry Co., Ltd. Process of fabricating an MIS FET
US4774207A (en) * 1987-04-20 1988-09-27 General Electric Company Method for producing high yield electrical contacts to N+ amorphous silicon
US5214302A (en) * 1987-05-13 1993-05-25 Hitachi, Ltd. Semiconductor integrated circuit device forming on a common substrate MISFETs isolated by a field oxide and bipolar transistors isolated by a groove
US4753898A (en) * 1987-07-09 1988-06-28 Motorola, Inc. LDD CMOS process
US4907048A (en) * 1987-11-23 1990-03-06 Xerox Corporation Double implanted LDD transistor self-aligned with gate
JPH01175260A (en) * 1987-12-29 1989-07-11 Nec Corp Method for manufacturing insulated gate field effect transistors
US4908326A (en) * 1988-01-19 1990-03-13 Standard Microsystems Corporation Process for fabricating self-aligned silicide lightly doped drain MOS devices
US5238859A (en) * 1988-04-26 1993-08-24 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
JPH0666329B2 (en) * 1988-06-30 1994-08-24 株式会社東芝 Method for manufacturing semiconductor device
US4978627A (en) * 1989-02-22 1990-12-18 Advanced Micro Devices, Inc. Method of detecting the width of lightly doped drain regions
JPH02265250A (en) * 1989-04-05 1990-10-30 Nec Corp Manufacture of semiconductor device
FR2646291B1 (en) * 1989-04-21 1991-06-14 Thomson Hybrides Microondes METHOD FOR PRODUCING A SELF-ALIGNED TRANSISTOR
US5013675A (en) * 1989-05-23 1991-05-07 Advanced Micro Devices, Inc. Method of forming and removing polysilicon lightly doped drain spacers
JPH0779101B2 (en) * 1989-05-24 1995-08-23 株式会社東芝 Manufacturing method of semiconductor device
US5212105A (en) * 1989-05-24 1993-05-18 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method and semiconductor device manufactured thereby
US5030590A (en) * 1989-06-09 1991-07-09 Applied Materials, Inc. Process for etching polysilicon layer in formation of integrated circuit structure
JP2760068B2 (en) * 1989-07-18 1998-05-28 ソニー株式会社 Method of manufacturing MIS type semiconductor device
US5024959A (en) * 1989-09-25 1991-06-18 Motorola, Inc. CMOS process using doped glass layer
US5200351A (en) * 1989-10-23 1993-04-06 Advanced Micro Devices, Inc. Method of fabricating field effect transistors having lightly doped drain regions
US5102816A (en) * 1990-03-27 1992-04-07 Sematech, Inc. Staircase sidewall spacer for improved source/drain architecture
EP0456318B1 (en) * 1990-05-11 2001-08-22 Koninklijke Philips Electronics N.V. CMOS process utilizing disposable silicon nitride spacers for making lightly doped drain transistors
JP3380117B2 (en) * 1995-07-24 2003-02-24 セイコーインスツルメンツ株式会社 Semiconductor device and manufacturing method thereof
TW339470B (en) * 1997-09-01 1998-09-01 United Microelectronics Corp The manufacturing method for spacer
US6063668A (en) * 1997-12-18 2000-05-16 Advanced Micro Devices, Inc. Poly I spacer manufacturing process to eliminate polystringers in high density nand-type flash memory devices
US6281078B1 (en) 1997-12-18 2001-08-28 Advanced Micro Devices, Inc. Manufacturing process to eliminate ONO fence material in high density NAND-type flash memory devices
US5994239A (en) * 1997-12-18 1999-11-30 Advanced Micro Devices, Inc. Manufacturing process to eliminate polystringers in high density nand-type flash memory devices
US6093610A (en) * 1998-06-16 2000-07-25 Texas Instruments Incorporated Self-aligned pocket process for deep sub-0.1 μm CMOS devices and the device
US7022596B2 (en) * 2003-12-30 2006-04-04 Advanced Micro Devices, Inc. Method for forming rectangular-shaped spacers for semiconductor devices

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54115085A (en) * 1978-02-28 1979-09-07 Cho Lsi Gijutsu Kenkyu Kumiai Method of fabricating semiconductor
US4209350A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming diffusions having narrow dimensions utilizing reactive ion etching
JPS5735341A (en) * 1980-08-12 1982-02-25 Toshiba Corp Method of seperating elements of semiconductor device
US4356623A (en) * 1980-09-15 1982-11-02 Texas Instruments Incorporated Fabrication of submicron semiconductor devices
US4337132A (en) * 1980-11-14 1982-06-29 Rockwell International Corporation Ion etching process with minimized redeposition
US4432132A (en) * 1981-12-07 1984-02-21 Bell Telephone Laboratories, Incorporated Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features

Also Published As

Publication number Publication date
JPS59138379A (en) 1984-08-08
EP0127725A1 (en) 1984-12-12
JPH0434819B2 (en) 1992-06-09
EP0127725B1 (en) 1987-04-01
US4488351A (en) 1984-12-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee