FI74355C - Steer memory. - Google Patents

Description

TyjS ^ Tl ANNOUNCEMENT.

»* Sf $ [B] (11) utläggningsskrift * ^ (45) 1" (51) Kv.lk.4 / lnt.CI4 G 06 F 9/22

SUOMI FINLAND

(Fl) (21) Patent application-Patentansökning 8001 18 (22) Application date - Ansökningsdag 15.01.80

National Board of Patents and Registration (23) Start date - Giltighetsdag 15.01.80

Patant-och registerstyrelsen (47) Tu (lutJU, k (SekS (.Bi, vrtoffenti.g 17.07.80) (44) Date of dispatch and of publication - og gg g-j

Ansökan utlagd och utl skriften publicerad 'Ό' (86) Kv. Application - Int ansökan (32) (33) (31) Privilege claimed - Begärd priority 16.01. 79 USA (US) 3841 (71) Digital Equipment Corporation, 146 Main Street, Maynard, Massachusetts USA (US) (72) William H. Roberts, Corona de Mar, California,

Spencer S. Hu, Wayland, Massachusetts, USA (74) Oy Kolster Ab (54) Control Memory - Styrminne This invention relates to a control block for numerical computers. More specifically, the invention relates to a microprogram control memory that uses a fast, flexible, and efficient method of interpreting computer machine instructions. Although the present invention is mostly described by the names of MOS / LSI implementations of control memories, the basic technique is applicable to other types of implementations, such as normal bipolar components.

Modern computers utilize micro-programming technology to implement their control block. This involves storing a microgram representing the control order of the machine in the control memory. This memory can be implemented in the form of a read-only memory (ROM) or write memory. The execution sequence is controlled by a micro-program with a micro-level program counter or by moving the address of the next micro-instruction in the control word together with the micro-instruction. The latter method is disclosed in this patent, but the present invention is not limited to that formula.

2 74355

In order to execute a machine language instruction on a computer, it is necessary to direct the selector to the correct part (s) of the machine language instruction currently being executed and located in the instruction register. The normal method for interpreting a computer instruction and controlling the execution order of a microprogram is to "map" the instruction execution code to an output control memory address via a ROM or PLA (Programmable Logic Array). In many cases, only one initial survey is required. Subsequent mappings may be performed or conditional micro-level branches may be obtained by testing certain bits or combinations of bits in the instruction register. Often, micro-level subroutines are used to direct control to other parts of the micro-program without losing the results of the initial mapping, which of course is extracted from the micro-program address at the time of the sub-program call.

Typically, the mapping diagram provides the address of the control memory, which is then used to obtain the first microinstruction resulting from the interpretation of the instruction. Obtaining an address first from the mapping operation and then accessing the first control word as a sequential operation is time consuming. This is because the mapping time is usually almost the same as the control memory access time. This invention is directed to achieving substantial time savings in the interpretation of machine language instructions. It can also be used to interpret other input data such as interrupts, graft, stack memory overflow, etc.

It is therefore an object of the present invention to provide a microprocessor control memory which uses a fast, flexible and efficient method of interpreting machine language instructions on a computer.

Another object of the present invention is to provide a control program of a microprogram in which the interpretation of a machine language instruction of a computer and the acquisition of the first control word resulting from the interpretation take place simultaneously.

It is a further object of the present invention to provide a firmware control memory that allows one or more control words to change bits or codes of other control words to change their interpretation, thereby reducing the number of control words that would otherwise be required.

It is a further object of the present invention to provide a firmware control memory including PLA and ROM components that allows 3 74355 control words whose access is independent of the instruction in question to be stored in a ROM component structure that is generally less expensive and smaller than a PLA structure; and storing those control words whose access depends on the instruction in question in the PLA structure.

Yet another object of the present invention is to provide a microprocessor control memory having both ROM and PLA structures, the configuration of which in the form of a MOS / LSI circuit can be combined, resulting in a reduction of circuits and interconnections and thus a smaller microcircuit.

It is a further object of the present invention to provide a PLA portion of a microprogram control memory in which control words are displayed by both machine status and an executable instruction; therefore, the execution order of the computer control section is the result of the interpretation of the computer-language instruction executed by the PLA.

Yet another object of the present invention is to provide a control memory which uses the PLA portion of the control program of the microprogram because of the command interpretation power and the ROM because of the control word storage capability.

The above and other objects of the present invention are achieved according to an embodiment of the present invention by reserving a computer control section of a microprogram having both a PLA device for storing control words and a ROM device for storing control words. The access device of the ROM storage mechanism is based on the address inputs obtained from the address register. The PLA control word access devices are based on address inputs and part or all command inputs available from the instruction register. The interleaver connected to the ROM and PLA parts selects their inputs based on the interpretation of certain bits of the address inputs. This output gives a microinstruction and the next address. There is also a feedback device for connecting the output of the next address from the interleaver to the register of the next address.

The above and other objects and novel features of the present invention will become more fully apparent from the following description when read in conjunction with the accompanying drawings, in which:

Figure 1 schematically illustrates a block diagram structure of a control program of a microprogram used in the implementation of the present invention.

Figure 2 schematically illustrates a block diagram structure of an embodiment of the present invention in which the PLA and ROM structures 4 74355 combine so that a single column bit line or network of the PLA is co-located with a corresponding ROM column bit line.

Figure 3 schematically illustrates an example of a combined ROM and PLA control memory with nine 2-bit control pins and one 2-bit control output.

Figures 4a and 4b schematically define the symbols of the ports used in the example of Figure 3.

Figure 5 illustrates in tabular form the coding of the example control memory of Figure 3.

The present invention utilizes a computer control block having a control memory constructed of both PLA and ROM type structures for storing control words. Read-only memory (ROM) is an extract memory in which data is permanently stored in memory and thus the memory can only be read. The memory has n address inputs, which we exhaustively interpreted as access to 2n memory locations. EPROMs, PROMs and similar devices are included in this same product family.

A programmable logic network (PLA) comprises two networks: one is a set of AND gates and the other is a set of OR gates. AND gates have n actual inputs and their complement, which can be programmed as connections as desired. The OR gates have inputs from the outputs of the AND gates and the connections can be programmed as desired.

Both ROM and PLA structures store control words consisting of a microinstruction and the following address. This control memory, which is constructed of both PLA 2 and ROM 4 type structures for storing control words, is illustrated in Figure 1. The part 2 of the control memory built into the PLA is variable, but could normally be a 1 / nth part of the total memory. where n is 2, 4 or 8. Each memory structure 2 and 4 receives the respective address inputs 12 and 14 from the next address register 4. The register 4 contains the next address to be followed from the last control word via the next address line 30. The PLA 2 also receives input 22 from instruction register 8 or another source of input to be interpreted. Typically, the AND gate decoders of PLA structure 2 and ROM structure 4 use both the inputs themselves and their complements. The ROM structure 4 comprises a ROM memory network 16 for storing control words and a decoder network 18. The decoder network 18 receives 5 74355 parts of the address as input data and its outputs activate the line selection lines of the ROM memory network 16. Each line selection line output from the ROM decoder 18 selects a few control words from the memory network 16, of which the output interleaver 20 then selects one under the control of the remaining address bits. The fact that the ROM decoder 16 is divided into a plurality of control words on each line selection line and has fewer inputs than the control memory PLA 2 AND gate decoder is important considering the range of silicon chip required to implement the control memory as a MOS / LSI component.

The PLA 2 comprises two parts, an OR gate network 24 and an AND gate network 26. The OR gate network 24 is the same as the ROM 4 memory network 16 except that only one control word can be selected on each line selection line. The AND gate network 26 acts as a decoder to activate the line selection lines and thus to select each control word of the OR gate network 24. The PLA memory and port network 24 are less efficient than the ROM memory network 16 because there is one decoding AND gate for each word and the AND gates 24 have much more inputs than the decoder 18 of the ROM 4. The reason why there is one decoding per control word AND gate, is due to the fact that the programming of the AND gate network 26 must be unique for each control word. Each control word stored in the PLA structure 2 of the control memory is displayed by the appropriate state of the address inputs 12 and the instruction inputs 22 to be interpreted, such as the contents of the instruction register of the computer.

The selection between the PLA OR gate network 24 and the ROM memory network 16 is performed by some bit or combination of bits of the next address 14 and 16. This depends on the number of 2 lines (AND gates) of the PLA, the number of 20 lines of the ROM, and the number of control words received from each line of the ROM 20. That selection takes place in the interleaver 28.

It is important to note that in this control memory structure, the control words may be located in either part of the memory. The control words to be displayed as a result of some interpretation of the contents of the instruction register 8 are located in the PLA memory network 24, while other words can be placed in the memory ROM network 16 as well as in the PLA memory network 24. Consecutive words can be displayed as well from each structure by specifying the next address from the desired memory area.

The program microinstructions can be mixed between the ROM memory network 16 and the PLA OR port network 24 in any manner. A machine language program can perform appropriate configurations when creating a micro-program.

As already mentioned, the inputs to the AND gate network 26 of the PLA structure 2 are generally the next address 12 itself and the parts of the instruction 22 required to control the order of the microprogram and their complements. Therefore, the AND gate network 26 is not a complete interpretation of the inputs, as is the case with the ROM decoder 18; only the interpretations of income 12 and 22 necessary to bring each word to light are required. The next address (12) acts as a "mapping code" that selects a group of AND gates from port network 26. The AND gate (s) to be activated for each mapping code depends on the coding of the instruction input (22). This procedure is further illustrated in the following example. The entire range of addresses defined for PLA structure 2 may not be used because the number of codes required is equal to the number of mappings required. The use of the mapping code as the next address represents the points in the micro-program where the access to the control word depends on the codes or private bits of the instruction register 8. In fact, this mapping is similar to that previously described for other types of controls, where the mapping produced a control address, but here the PLA structure 2 produces a microinstruction rather than a microinstruction address. This results in a faster retrieval of the microinstruction than if the mapping would only give the address of the control word. It also allows mapping to be done in control memory rather than in a separate structure. Since each mapping code can control countless AND gates in the AND gate group 26, it is possible to obtain countless mappings up to the number of available AND gates and addresses assigned to the PLA structure. Flexibility is obtained for the control block by allowing the mapping or testing of command inputs at any point in the microgram without wasting time. In addition, AND gates can be programmed with "do not care" inputs to respond to a range or set of mapping codes and / or command codes. This results in efficient micro-programming technology when combined with the ability to convert control words, as described in the next section.

The OR gate network 24 stores control words, such as the memory network 16 of the ROM 4. Each control word is displayed under the control of its AND gate 7 74355. One unique feature of this control diagram is that logic can be performed in an OR gate memory network 24 when more than one AND gate is active at a time. This causes more than one word to be displayed at a time, with the result being an OR or AND delivery of all the selected control words. The logic operation to be performed depends on the logical polarity agreement applicable to the network 24. One or more control words with substitute ones and zeros can be used to modify another control word. The change may occur in the microinstruction or in the next address portion of the control word. Exploitation of this technique requires the ability to define bits and codes for microinstruction and addresses so that the correct control word change can occur. For example, a group of microinstructions can be programmed for byte deliveries, and all microinstructions in the group can be converted to word deliveries with a single word obtained at the same time as one of the byte microinstructions. Such a word replaces the bit or code defining the byte delivery with one that defines the word delivery.

Figure 2 illustrates the arrangement of the combined PLA and ROM structure. (Note that similar reference numerals indicate identical or corresponding parts in the drawings.) The control memory is implemented in a MOS / LSI type implementation. The PLA and ROM structures can thus be combined on the same silicon chip. By combining the two memory structures, certain savings are achieved and chip size is overcome compared to the two separate structures. In conventional ROM models, all the column bit lines of a given bit are located next to each other to allow the placement of the output interleaver. When the PLA and ROM are combined, as shown in Figure 2, a single column bit line of the OR group of the PLA is located together with the corresponding ROM-Sara bit lines. For the same reasons, the additional transfer interleaver 40 selects the column bit lines of the PLA, while the inputs of the second interleaver select the ROM column bit lines. By placing the PLA bit lines together with the ROM bit lines, a considerable amount of chip routing is removed. This results in a smaller chip and a higher operating speed. This is shown in Figure 3 on the right. Note that the PLA bit lines 103 and 104 are adjacent to the ROM bit lines 101 and 102, making connection to the interleaver 105 easier.

It is common practice in large ROM models to place the deco derivative network in the center of the memory network and route the line selection to the center of the memory network and route the line selection line from both sides of the decoder to the control memory network, thus halving the line selection line length. This produces faster access time by reducing the propagation delay on line selection lines. Such a technique is generally illustrated in Figure 2. In the combined structure of Figure 2, a single AND gate network 42 is located in the center of the entire memory network 44. This network 42 functions both as an AND gate network of the PLA and as a decoder network of the ROM. Individual AND gates activate each line selection line. The port acts as the AND gate of the PLA for a single control word of the line selection from the PLA structure and as a ROM decoder for the other control words of the line selection line.

The AND gate network 42 of the combined structure 44 has two sets of inputs. The second set is the same as the set of the ROM structure 4 according to Fig. 1 and the second set of inputs is the same as the set of the PLA structure 2 according to Fig. 1. The AND gates of network 42 are combinations of the AND gate of the PLA and the AND gate decoding the ROM. To make the port act as the AND gate of the PLA according to Figure 2, the PLA set of inputs is input and the ROM set of the inputs is set to the true state so that the port is a function of the PLA programming. Similarly, to make the AND gate function as the ROM decoder of Figure 2, the ROM set of inputs is input and the PLA set is set to true. The combined AND decode report 42 is made to operate as the AND gates of the PLA operate when the next address is in the range of addresses assigned to the PLA. At that point, the output interleaver 40 selects the column bit line of the PLA. When the next address is in the range of addresses assigned to the ROMs, the AND gate 42 is made to act as a ROM decoder 18 and the output interleaver 40 selects one ROM column bit line. The combined AND gate network 42 is necessary to allow numbering between the ROM and PLA bit lines while keeping the line selection lines as short as possible. It also results in chip area savings as the load boost or circuits considered to be current for the second set of AND gates and associated buffer amplifiers are eliminated.

An illustrative example of a combined ROM and PLA control memory is shown in Figure 3. Of course, this simplified example is rudimentary in nature and is used for explanatory purposes only, and the basic technique illustrated can be applied to any of a myriad variations of control words and address bit lengths.

In this example, there are nine two-bit control words, four in the control memory 100 in the ROM block, and five in the control memory 100 in the PLA block. Memory 100 is initially divided in half between ROM bit line sets 101 and 102 and PLA sets 103 and 104. The two sets of bit lines are interleaved by an interleaver 105 comprising AND gates 106-109 and OR gates 110 and 111 controlled by address input 304 (complement of A2 and A2). Note that the example does not illustrate the technique of Figure 2 to place the decoder network in the center of the memory network and control the line selection line on both sides. This can be easily accomplished by extending the line selection bit lines 200-204 to the left and mirroring the amplifiers 700-704 and and the control memory 100 on the right.

The figure shows five line selection lines 200-204, of which only four, 200-203, are used for ROM and five are used for PLA.

(This additional PLA selection line is somewhat underused because there is room for the fifth ROM word, but the same cannot be done because the codes for the ROM address inputs, 303 and 304, are already fully interpreted.) There are 10 inputs to the control memory; three address lines labeled AO, A1 and A2, true and complement (address inputs 300, 301 and 304); and two instruction register lines labeled 10 and II, true and complement (instruction inputs 302 and 303). Address input 304 performs a choice between ROM and PLA. When not maintained, ROM is selected by connecting ROM bit lines 101 and 102 to the two output lines 600 and 601, and the eight inputs (via OR gates 500-507) of the PLA and AND gate portions of the combined AND decoder are valid. When address input 304 is maintained, PLA bit lines 103 and 104 are connected to two output lines 600 and 601, and the four inputs of the decoder portion of the combined AND / decoder (via OR gates 400-403) are valid.

In the example of Figure 3, gates 800 and 900 are shown with half-filled circles and intersecting lines. The two ports of the first focus 800, separated by dotted lines, are illustrated in Figure 4a. The filled parts of the circle 99 of the gates 800 represent the inputs of the gate. Input lines 811 and 812 run to the gate inputs (99). The complete gate is denoted when a line (here line 820) runs perpendicular to the input line 74115 (811 and 812) and bisects the circles 98. Line 820 in Figure 4a therefore acts as the output line. If the control memory is implemented as a MOS / FET type implementation, one manufacturing method is illustrated in Figure 4b. The "gate" terminal of transistor 801 operates like the gate input 99 of Figure 4a and is connected to input lines 811 and 812. The "anode" terminal 802 is connected to lines 811 and 812, which run perpendicular to the input line 820 in the diagram. "Cathode pole 803 is connected to logic ground 804. Second focus 900 works in the same way as focus 800, except that the supply lines and gate connections are rotated 90 degrees counterclockwise.

The coding of the control memory in the example of Fig. 3 is shown in Fig. 5. The first four addresses (from 000 to 011) 0 as address bit 304 display the four words stored in the ROM part of the memory. Addresses 100 and 101 act as mapping codes that activate portions of the PLA portion of the memory. The actual word or words obtained from the PLA depend on the encoding of the inputs 302 and 303 from the instruction register. Note that the address input data 100 and the command input X, where X stands for "do not care", do not display any words from the control memory and therefore produce the default output data 0. The substitution principle is illustrated in the last three entries of Fig. 5, all of which are the conversion code address input 101. The last two entries are mutually exclusive, indicating independence from instruction input 302 and produce the corresponding results 10 and 01. Third, the last entry is a function of instruction input 302. If input 302 is applied, it is selected along with the input that is the second of the last two inputs. The result is an OR delivery of the selected words or in this case 10 or 11.

The treatment method illustrated in the example above can be adapted to many different treatment systems with the same associated advantages. It will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the invention. Therefore, it is an object of the following claims to cover all such modifications and variations as fall within the true spirit and scope of the present invention.

Claims (8)

1. Control unit intended to be used in a data processing device in a data processing system by means of which control unit is generated iteratively control word on the basis of an order and preceding control word, each control word containing an address part and the data processing device having processing circuits which perform functions on the base of control words from the controller to which the controller belongs an order register (8), an address register (6), a first control word memory (2) and a second control word memory (4), characterized in that the first control word memory (2) address input terminals (12, 22) are coupled to receive address signals from both the order register (8) and the address register (6), that the address terminals (14) of the second control word memory (4) are coupled to receive address signals only from the address register (6) and that the output terminals of both the first and the second control word memory (2, 4) are coupled to a multiplexer (28) which is controlled by a signal from the address memory (6), which, during each iteration, selects a control word generated by either the first or the second control word memory for transmission to the processing circuits. Control unit according to claim 1, characterized in that the output of the multiplexer (28) is further connected (30) to the address register (6) for transmitting the address part of a selected control word to said address register (6), where it is used in selecting a control words during a later iteration. Control unit according to claim 1, characterized in that the first control word memory includes memory circuits (24), whose output terminals are connected to the input terminals of the multiplexer (28), which memory circuits comprise several memory locations storing a control word, and a decoding circuit. (26), whose input terminals are connected to both the order register (8) and the address register (6) for selecting the memory location, so that its contents upon transmission to the multiplexer (28) correspond to address signals received from both the order register (8) and the address register (6). ). 14 74 35 5 Control unit according to claim 1, characterized in that the second control word memory (4) includes memory circuits (16), whose output terminals are connected to the input terminals of the multiplexer (28), which memory circuits comprise several memory locations storing a control word. , a decoding circuit (18), whose input terminals are coupled to the address register (16) to select a selected number of memory locations and an output multiplexer (20) for coupling the contents of a memory location to the multiplexer (28) on the base of address signals from the address register. Control unit according to claims 3 and 4, characterized in that the decoding circuit includes several coincidence gates whose inputs (400-402) are connected to the decoding circuit's input terminals and whose outputs output a signal which selects the memory location. Control unit according to claim 5, characterized in that each coincidence gate is formed by a control line, to which at least one circuit element is connected, and by an output, one of the signals received by the address terminal activating each circuit element, which control line transmits an output signal only where all the circuit elements connected thereto are activated. Control unit according to claim 6, characterized in that at least one of the coincidence gates forming the decoding circuit of both the first and the second control word memory has a common control line (200-204), in which each decoding circuit further hears a circuit which activates all the circuit elements which connect to either the first or second control word memory when the multiplexer transmits a control word of either memory. 8. A control unit according to claim 7, characterized in that each memory circuit is formed by a plurality of controllers, to each of which at least one circuit element is coupled, and by an output connected to the multiplexer, the control input of each and a circuit element of the first and second memory circuits is joined to the control line of the coincidence gate of the first and second memory, respectively. the second decoding circuit, said memory circuit transmitting an output signal at which at least one of the associated circuit elements is activated.