FR1397424A - Method for making contacts for silicon semiconductor devices - Google Patents

Method for making contacts for silicon semiconductor devices

Info

Publication number
FR1397424A
FR1397424A FR967890A FR967890A FR1397424A FR 1397424 A FR1397424 A FR 1397424A FR 967890 A FR967890 A FR 967890A FR 967890 A FR967890 A FR 967890A FR 1397424 A FR1397424 A FR 1397424A
Authority
FR
France
Prior art keywords
semiconductor devices
silicon semiconductor
making contacts
contacts
making
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR967890A
Other languages
French (fr)
Inventor
Jean-Pierre Rioult
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Radiotechnique SA
Original Assignee
Radiotechnique SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Radiotechnique SA filed Critical Radiotechnique SA
Priority to FR967890A priority Critical patent/FR1397424A/en
Application granted granted Critical
Publication of FR1397424A publication Critical patent/FR1397424A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
FR967890A 1964-03-19 1964-03-19 Method for making contacts for silicon semiconductor devices Expired FR1397424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR967890A FR1397424A (en) 1964-03-19 1964-03-19 Method for making contacts for silicon semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR967890A FR1397424A (en) 1964-03-19 1964-03-19 Method for making contacts for silicon semiconductor devices

Publications (1)

Publication Number Publication Date
FR1397424A true FR1397424A (en) 1965-04-30

Family

ID=8825847

Family Applications (1)

Application Number Title Priority Date Filing Date
FR967890A Expired FR1397424A (en) 1964-03-19 1964-03-19 Method for making contacts for silicon semiconductor devices

Country Status (1)

Country Link
FR (1) FR1397424A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0720234A2 (en) * 1994-12-30 1996-07-03 SILICONIX Incorporated Vertical power MOSFET having thick metal layer to reduce distributed resistance and method of fabricating the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0720234A2 (en) * 1994-12-30 1996-07-03 SILICONIX Incorporated Vertical power MOSFET having thick metal layer to reduce distributed resistance and method of fabricating the same
EP0720234A3 (en) * 1994-12-30 1997-09-10 Siliconix Inc Vertical power MOSFET having a thick metal layer to reduce the distributed resistance and manufacturing method
US6043125A (en) * 1994-12-30 2000-03-28 Siliconix Incorporated Method of fabricating vertical power MOSFET having low distributed resistance
US6066877A (en) * 1994-12-30 2000-05-23 Siliconix Incorporated Vertical power MOSFET having thick metal layer to reduce distributed resistance

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