FR2808121A1 - Large scale integrated package for computer, forms wiring pattern on build up layer so that it is connected between substrate input/output terminal and bare chip input/output terminal - Google Patents

Large scale integrated package for computer, forms wiring pattern on build up layer so that it is connected between substrate input/output terminal and bare chip input/output terminal Download PDF

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Publication number
FR2808121A1
FR2808121A1 FR0103447A FR0103447A FR2808121A1 FR 2808121 A1 FR2808121 A1 FR 2808121A1 FR 0103447 A FR0103447 A FR 0103447A FR 0103447 A FR0103447 A FR 0103447A FR 2808121 A1 FR2808121 A1 FR 2808121A1
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Prior art keywords
bare chip
substrate
input
output terminal
output terminals
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Granted
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FR0103447A
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French (fr)
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FR2808121B1 (en
Inventor
Hitoshi Hoshino
Tomiji Sato
Atsushi Taga
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

La présente invention propose un boîtier LSI sans passer par les étapes consistant à former des perles de soudure sur une puce nue et à les souder à un film interposé. Dans la présente invention, une puce nue (4) est montée sur le boîtier LSI en formant des motifs de câblage (6) qui connectent les bornes d'entrée/ sortie (3) de ladite puce nue (4) dans une couche de montage (2) d'un substrat (1). De plus, les motifs de câblage (6) sont formés de manière à connecter les bornes E/ S extérieures (7) sur le substrat (1).The present invention provides an LSI package without going through the steps of forming solder beads on a bare chip and soldering them to an interposed film. In the present invention, a bare chip (4) is mounted on the LSI package by forming wiring patterns (6) which connect the input / output terminals (3) of said bare chip (4) in a mounting layer. (2) of a substrate (1). In addition, the wiring patterns (6) are formed so as to connect the outer I / O terminals (7) on the substrate (1).

Description

BOITIER LSI <B>ET</B> PROCEDE <B>DE</B> CONNEXION INTERNE <B>UTILISE</B> POUR <B>CELUI-CI</B> <U>CONTEXTE DE L'INVENTION</U> <U>Domaine de l'invention</U> La présente invention concerne un boîtier ("Large Scale Intégration" ou "Intégration à grande échelle") et un procédé de connexion interne utilise pour celui-ci.  CASE LSI <B> AND </ B> PROCESS <B> FROM </ B> INTERNAL CONNECTION <B> USED </ B> FOR <B> THIS </ B> <U> CONTEXT OF THE INVENTION </ FIELD OF THE INVENTION The present invention relates to a case ("Large Scale Integration" or "Large Scale Integration") and an internal connection method used for it.

<U>Description de l'art antérieur</U> En ce moment, dans le domaine des boîtiers pour semi-conducteurs, des boîtiers ayant de nouveaux types de formes sont développés l'un après l'autre, afin répondre à des demandes telles que la miniaturisation l'allègement, l'accélération, et l'amélioration fonctions, pour des appareils électroniques tels que ordinateurs. En conséquence, toute une variété de boîtiers existe actuellement. <U> Description of the Prior Art </ U> At the moment, in the field of semiconductor packages, housings having new types of shapes are developed one after the other, in response to requests. such as miniaturization, lightening, acceleration, and enhancement functions, for electronic devices such as computers. As a result, a variety of packages exist today.

Dans 1a structure typique des boîtiers, une puce nue qui est montée sur un socle moulé sous pression est connectée avec des conducteurs pour réaliser une <B>a</B> -z connexion électrique avec des circuits extérieurs des fils de connexion. De plus, sur le socle moulé sous pression, la puce nue et les canaux qui comprennent conducteurs sont recouverts d'un boîtier moulé. In the typical housing structure, a bare chip which is mounted on a die-cast base is connected with conductors to provide an electrical connection with external circuits of the lead wires. In addition, on the die-cast base, the bare chip and channels that include conductors are covered with a molded case.

Les boîtiers LSI présentant de telles structures sont utilisés en 'étant montés sur des cartes de circuits imprimés de divers appareils électroniques. Les boîtiers LSI décrits ci-dessus sont révélés dans les demandes de brevet japonais non examinées, première publication, N ' Hei 114776 et Hei 8-279590 et autres demandes similaires. LSI packages having such structures are used by being mounted on printed circuit boards of various electronic devices. The LSI packages described above are disclosed in Japanese Unexamined Patent Applications, First Publication, No. 114776 and Hei 8-279590 and other similar applications.

Dans une puce conventionnelle, la puce nue est connectée en formant des perles ("bumps") de soudure sur la puce nue et soudant les perles à un substrat ou un film qui est appelé "film interposé". Toutefois, il est difficile former de très petites perles de soudure. In a conventional chip, the bare chip is connected by forming beads ("bumps") of solder on the bare chip and soldering the beads to a substrate or film which is called "interposed film". However, very small solder beads are difficult to form.

L'objet de présente invention est de résoudre le problème ci-dessus et de proposer un boîtier LSI sans passer par étapes consistant à former les perles de soudure sur la puce nue et à les souder au film interposé, et un procédé de connexion interne utilisé pour celui-ci. The object of the present invention is to solve the above problem and to provide a step-wise LSI package consisting of forming the solder beads on the bare chip and soldering them to the interposed film, and an internal connection method used. for this one.

<U>Résumé de l'invention</U> La présente invention concerne un boîtier LSI comprenant un substrat dans lequel une puce nue est montée, dans lequel un procédé de montage est utilisé pour former des motifs de câblage qui connectent les bornes d'entrée/sortie de ladite puce nue et les bornes d'entrée/sortie extérieures dudit substrat. The present invention relates to an LSI package comprising a substrate in which a bare chip is mounted, wherein a mounting method is used to form wiring patterns that connect the terminals of the invention. input / output of said bare chip and external input / output terminals of said substrate.

Avantageusement lesdits motifs de câblage sont formés dans une couche de montage dudit substrat pour connecter lesdites bornes d'entrée/sortie qui sont formées sur la surface côté substrat de ladite puce nue et lesdites bornes d'entrée/sortie extérieures qui sont formées sur la surface dudit substrat faisant face à ladite puce nue. Avantageusement lesdits motifs de connexion sont formés dans une couche de montage dudit substrat pour connecter lesdites bornes d'entrée/sortie qui sont formées sur la surface côté substrat de ladite puce nue et sur des puces nues factices qui sont formées de maniere à être adjacentes à ladite puce nue, lesdites bornes d'entrée/sortie extérieures qui sont formées sur la surface dudit substrat faisant face ladite puce nue. Advantageously said wiring patterns are formed in a mounting layer of said substrate for connecting said input / output terminals which are formed on the substrate side surface of said bare chip and said external input / output terminals which are formed on the surface. said substrate facing said bare chip. Advantageously, said connection patterns are formed in a mounting layer of said substrate for connecting said input / output terminals which are formed on the substrate side surface of said bare chip and on dummy nude chips which are formed to be adjacent to each other. said bare chip, said external input / output terminals which are formed on the surface of said substrate facing said bare chip.

La présente invention concerne également procédé de connexion interne pour un boîtier LSI comprenant un substrat dans lequel une puce nue est montée, dans lequel le procédé comprend une étape consiste à former des motifs de câblage qui connectent les bornes d'entrée/sortie de ladite puce nue et bornes d'entrée/sortie extérieures dudit substrat par un procédé de montage. The present invention also relates to an internal connection method for an LSI package comprising a substrate in which a bare chip is mounted, wherein the method comprises a step of forming wiring patterns that connect the input / output terminals of said chip. and external input / output terminals of said substrate by a mounting method.

Un boîtier LSI selon la présente invention comprend donc un substrat dans lequel une puce nue est montée, dans lequel un procédé de montage est utilisé pour former des motifs de câblage qui connectent les bornes d'entrée/sortie de la puce nue et les bornes d'entrée/sortie extérieures du substrat. An LSI package according to the present invention therefore comprises a substrate in which a bare chip is mounted, wherein a mounting method is used to form wiring patterns which connect the input / output terminals of the bare chip and the terminals of external input / output of the substrate.

De plus, le procédé de connexion interne pour un boîtier LSI selon la présente invention est un procédé de connexion interne pour un boîtier LSI comprenant un substrat dans lequel une puce nue est montée. Le procédé comprend une étape consistant à former des motifs de câblage qui connectent les bornes d'entrée/sortie de la puce nue et les bornes d'entrée/sortie extérieures du substrat un procédé de montage. In addition, the internal connection method for an LSI package according to the present invention is an internal connection method for an LSI package comprising a substrate in which a bare chip is mounted. The method comprises a step of forming wiring patterns that connect the input / output terminals of the bare chip and the external input / output terminals of the substrate a mounting method.

A savoir, le boîtier LSI selon la présente invention est caractérisé par l'utilisation des motifs de câblage formés par le procédé de montage à titre de moyens pour monter la puce nue et pour la connexion interne de celui-ci, au lieu des connexions sur perles de soudure conventionnelles. Namely, the LSI package according to the present invention is characterized by the use of the wiring patterns formed by the mounting method as means for mounting the bare chip and for the internal connection thereof, instead of the connections on the conventional welding beads.

Dans la présente invention, étant donné que la connexion entre la puce nue et le film interposé est réalisée par le procédé de montage plutôt que par des connexions sur perles de soudure, la connexion peut être réalisée sans utiliser de soudure entre les très petites perles de soudure et le film interposé. Par conséquent, il n'est pas nécessaire de passer par les étapes consistant à former les perles de soudure sur la puce et à les souder au film interposé. In the present invention, since the connection between the bare chip and the interposed film is performed by the mounting method rather than weld bead connections, the connection can be made without using solder between the very small beads of the solder. solder and the interposed film. Therefore, it is not necessary to go through the steps of forming the solder beads on the chip and soldering them to the interposed film.

<U>Brève explication des dessins</U> figure 1 est une vue en perspective expliquant la connexion par le procédé de montage selon un mode de réalisation de la présente invention. Brief Description of the Drawings FIG. 1 is a perspective view explaining the connection by the mounting method according to one embodiment of the present invention.

figure 2 est une vue en coupe transversale d'un boîtier LSI selon un mode de réalisation la présente invention. Figure 2 is a cross-sectional view of an LSI package according to an embodiment of the present invention.

figure 3 est une illustration expliquant la connexion d'une puce nue selon un mode réalisation de la présente invention.. Figure 3 is an illustration explaining the connection of a bare chip according to an embodiment of the present invention.

La figure 4 est un organigramme iquant le procédé de connexion interne selon mode de réalisation de la présente invention. <U>Description des modes de réalisation</U> préferés Les modes de réalisation préférés seront présentés ci-dessous en référence aux figures. La figure 1 est une vue en perspective expliquant la connexion par le procédé de montage selon un mode de réalisation de la présente invention. La figure 2 est une vue en coupe transversale d'un boîtier LSI selon un mode de réalisation de la présente invention, la figure 3 est une illustration expliquant la connexion d'une puce nue selon un mode de réalisation la présente invention. La connexion de la puce nue selon le mode de réalisation de la présente invention sera expliquée en référence aux figures 1 à 3. Fig. 4 is a flowchart illustrating the internal connection method according to an embodiment of the present invention. <U> Description of the Preferred Embodiments The preferred embodiments will be presented below with reference to the figures. Fig. 1 is a perspective view explaining the connection by the mounting method according to an embodiment of the present invention. Fig. 2 is a cross-sectional view of an LSI package according to an embodiment of the present invention, Fig. 3 is an illustration explaining the connection of a bare chip according to one embodiment of the present invention. The connection of the bare chip according to the embodiment of the present invention will be explained with reference to FIGS. 1 to 3.

Une pluralité de bornes E/S (entrée/sortie) de puce nue 3 sont formées sur une puce nue 4, et la puce nue 4 est montée sur le boîtier LSI formant des motifs de câblage 6 qui connectent les bornes E/S de puce nue 3 dans une couche de montage 2 un substrat 1. De plus, les motifs de câblage 6 sont formés de manière à connecter les bornes E/S extérieures 7 sur le substrat 1. A plurality of bare chip I / O (input / output) terminals 3 are formed on a bare chip 4, and the bare chip 4 is mounted on the LSI package forming wiring patterns 6 which connect the chip I / O terminals. 3 in a mounting layer 2 a substrate 1. In addition, the wiring patterns 6 are formed to connect the outer I / O terminals 7 to the substrate 1.

La figure 4 est un organigramme expliquant le procède de connexion interne selon le mode de réalisation de la présente invention. Le procédé de connexion interne du boîtier LSI selon le mode de réalisation de la présente invention sera expliqué en référence aux figures 1 à 4. Fig. 4 is a flowchart explaining the internal connection procedure according to the embodiment of the present invention. The internal connection method of the LSI package according to the embodiment of the present invention will be explained with reference to FIGS. 1 to 4.

Dans le procédé de connexion selon ce mode de réalisation, d'abord, une feuille de cuivre recouverte de rés' est stratifiée sur des puces nues factices Sa et 5b et sur les bornes E/S de puce nue 3 sur la puce 4 (étape S1 sur la figure 4), et ensuite, des trous sont alésés dans les bornes E/S de puce nue 3 par laser (étape S2 sur la figure 4). In the connection method according to this embodiment, first, a copper foil coated with res' is laminated on fake naked chips Sa and 5b and on the bare chip I / O terminals 3 on chip 4 (step 4). S1 in Fig. 4), and then holes are bored into the laser-free nib 3 I / O terminals (step S2 in Fig. 4).

Après cela, les motifs de câblage 6 sont formés la couche de montage 2 du substrat 1 par placage, exposition et décapage après développement (formation motifs) (étape S3 sur la figure 4) ; les bornes E/S extérieures 7 sont formées de manière à connecter les motifs de câblage 6 sur le substrat dans lequel la puce nue 4 est montée (étape S4 sur la figure 4). After that, the wiring patterns 6 are formed the mounting layer 2 of the substrate 1 by plating, exposing and stripping after developing (patterning) (step S3 in Fig. 4); the outer I / O terminals 7 are formed to connect the wiring patterns 6 to the substrate in which the bare chip 4 is mounted (step S4 in FIG. 4).

Comme décrit ci-dessus, dans présente invention, étant donné que les motifs de câblage 6 pour la connexion entre les bornes E/S de puce nue 3 et les bornes E/S extérieures 7 sont formés dans la couche de montage 2 par le procédé de montage, la connexion de la puce nue 4 peut être réalisée sans utiliser de soudure entre les très petites perles de soudure et le film interposé. Par conséquent, selon la présente invention, il n'est pas nécessaire de passer les étapes consistant à former des perles de soudure sur la puce 4 et à les souder au film interpose lorsque l'on fabrique le boîtier LSI qui comprend le substrat dans lequel la puce nue est montée.As described above, in the present invention, since the wiring patterns 6 for the connection between the bare chip I / O terminals 3 and the outer I / O terminals 7 are formed in the mounting layer 2 by the method mounting, the connection of the bare chip 4 can be achieved without using solder between the very small solder beads and the interposed film. Therefore, according to the present invention, it is not necessary to pass the steps of forming solder beads on chip 4 and soldering them to the interposed film when making the LSI package which comprises the substrate in which the bare chip is mounted.

Claims (4)

<U>REVENDICATIONS</U><U> CLAIMS </ U> 1. Boîtier LSI comprenant un substrat (1) dans lequel une puce nue (4) est montée, caractérise en ce qu'un procédé de montage est utilisé pour former des motifs de câblage (6) qui connectent les bornes d'entrée/sortie (3) de ladite puce nue (4) et les bornes d'entrée/sortie extérieures (7) dudit substratAn LSI package comprising a substrate (1) in which a bare chip (4) is mounted, characterized in that a mounting method is used to form wiring patterns (6) which connect the input / output terminals. (3) of said bare chip (4) and external input / output terminals (7) of said substrate 2. Boîtier LSI selon la revendication dans lequel lesdits motifs de câblage (6) sont formés dans couche de montage (2) dudit substrat (1) pour connecter lesdites bornes d'entrée/sortie (3) qui sont formées sur la surface côté substrat de ladite puce nue (4) et lesdites bornes d'entrée/sortie extérieures (7) qui sont formées sur la surface dudit substrat (1) faisant face à ladite puce nue (4).The LSI package according to claim wherein said wiring patterns (6) are formed in a mounting layer (2) of said substrate (1) for connecting said input / output terminals (3) which are formed on the substrate side surface. said bare chip (4) and said external input / output terminals (7) which are formed on the surface of said substrate (1) facing said bare chip (4). 3. Boîtier LSI selon la revendication 1, dans lequel lesdits motifs de connexion (6) sont formés dans une couche de montage (2) dudit substrat (1) pour connecter lesdites bornes d'entrée/sortie (3) qui sont formées sur la surface côté substrat de ladite puce nue ( et sur des puces nues factices qui sont formées de manière à être adjacentes à ladite puce nue (4), et lesdites bornes d'entrée/sortie extérieures (7) qui sont formées sur la surface dudit substrat (1) faisant face à ladite puce nue (4).The LSI package according to claim 1, wherein said connection patterns (6) are formed in a mounting layer (2) of said substrate (1) for connecting said input / output terminals (3) which are formed on the substrate-side surface of said bare chip (and on dummy chips chips that are formed adjacent to said bare chip (4), and said external input / output terminals (7) which are formed on the surface of said substrate (1) facing said bare chip (4). 4 Procédé de connexion interne pour un boîtier LSI comprenant un substrat (1) dans lequel une puce nue (4) montée, ledit procédé étant caractérisé en ce qu'il comprend une étape qui consiste a former des motifs de câblage (6) qui connectent les bornes d'entrée/sortie (3) de ladite puce nue (4) et les bornes d'entrée/sortie extérieures (7) dudit substrat (1) par un procédé de montage.An internal connection method for an LSI package comprising a substrate (1) in which a bare chip (4) is mounted, said method being characterized in that it comprises a step of forming wiring patterns (6) which connect the input / output terminals (3) of said bare chip (4) and the external input / output terminals (7) of said substrate (1) by a mounting method.
FR0103447A 2000-03-15 2001-03-14 LSI HOUSING AND INTERNAL CONNECTION METHOD USED THEREFOR Expired - Fee Related FR2808121B1 (en)

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US6653168B2 (en) 2003-11-25
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AU778518B2 (en) 2004-12-09
JP2001267449A (en) 2001-09-28
AU2798201A (en) 2001-09-20
US20010050426A1 (en) 2001-12-13
US20030122234A1 (en) 2003-07-03

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