FR3150040A1 - Display pixel comprising light emitting diodes for a display screen - Google Patents

Abstract

Display pixel comprising light-emitting diodes for a display screen The present description relates to a display pixel for a display screen, comprising at least one light-emitting device, a driver circuit for driving the light-emitting device, the display pixel receiving a first voltage (Vcc) and a first binary signal, the light-emitting device being powered by the first voltage. The display pixel further comprises a power supply circuit (60) providing a supply voltage (Vdd), lower than the first voltage, for powering the driver circuit. The power supply circuit comprises a first capacitor (C1) charged with a reference supply voltage (Vdd_Ref) from the first binary signal. The power supply circuit further comprises a voltage follower circuit (OAmp) providing the supply voltage at its output, the voltage follower circuit being powered by the first voltage, connected to the first capacitor, and maintaining the supply voltage equal to the reference supply voltage. Figure for abstract: Fig. 5.

Description

Display pixel comprising light emitting diodes for a display screen

This disclosure generally relates to display pixels comprising light emitting diodes for a display screen.

An image pixel corresponds to the unit element of the image displayed by a display screen. For the display of color images, a display screen generally comprises, for the display of each pixel of the image, at least three components, also called display subpixels, which each emit light radiation substantially in a single color (for example red, green and blue). The superposition of the radiation emitted by the three display subpixels provides the observer with the colored sensation corresponding to the pixel of the displayed image. In this case, the assembly formed by the three display subpixels used for the display of a pixel of an image is called a display pixel of the display screen. Each display subpixel may comprise a light source, in particular a light-emitting diode.

Display pixels can be arranged in a matrix, with each display pixel located at the intersection of a row (or line) and a column of the matrix. Typically, each row of display pixels is selected in succession, and the display pixels in the selected row are programmed to display the desired image pixels.

An active matrix is a display drive architecture that keeps all rows of pixels active for the entire duration of an image, unlike so-called passive matrices, in which each row is active only for a time T = Tframe/N (where Tframe is the duration of the image and N is the number of rows on the display). This allows the brightness of the display screen to be increased. In addition, it is possible to send low levels of current or voltage on the matrix control lines, which allows larger data streams to be displayed.

In the context of a display based on micrometer-sized light-emitting diodes formed on electronic circuits, the size of the light-emitting diode circuit is generally smaller than the size of the image pixel due to the inherently high brightness of the light-emitting diodes. One solution used is therefore to deposit these unit light-emitting diodes on a support (also called a wafer) containing the control electronics. Another solution involves the use of display pixels comprising light-emitting diodes and a circuit for controlling the light-emitting diodes. These are referred to as smart pixels. This makes it possible in particular to simplify the formation of an active matrix, since the electronic circuit for controlling the light-emitting diodes of the display pixel is, for the most part, integrated into the display pixel. WO 2018/185433 describes an example of a smart pixel.

For a smart pixel, the number of conductive connection pads used for the electrical connection of the smart pixel to the support imposes the dimensions of the smart pixel, in particular because of the minimum size of these pads and the minimum space to be provided between these pads. To limit the number of conductive connection pads, it is known to provide a single electrical supply voltage to the display pixels, and each display pixel generates, internally, one or a plurality of electrical supply voltages, in particular to polarize components of the electronic circuit.

The static power consumption of a display pixel is the electrical power consumed by the display pixel when it is not emitting light. It may consist of component leakage currents or currents required for the internal operation of the display pixel drive circuit. In the context of smart pixels, a significant portion of the static power consumption comes from power supply voltages internal to the smart pixel.

It may be considered to provide an additional conductive pad, on each smart pixel, to supply the smart pixel with the reduced power supply voltage so that it is not generated in the smart pixel. However, this may cause an increase in the dimensions of the smart pixel, which is not desirable.

The trend is to increase the number of display pixels of the display screen. The static power consumption of the display pixels can then become a critical factor. Indeed, for a so-called 4K display screen with a resolution of 2,160 by 3,840 display pixels, the static power consumption of the display screen can be greater than 150 W.

There is a need to reduce the static power consumption of the display screen.

An object of an embodiment is to provide a display screen comprising light emitting diodes which overcomes all or part of the disadvantages of existing display screens comprising light emitting diodes.

Another object of an embodiment is to provide display pixels having dimensions smaller than 200 µm, which limits the number of pads between the display pixel and the display pixel support.

One embodiment provides a display pixel for a display screen, comprising at least one light emitting device, for example a light emitting diode, a driver circuit for driving the light emitting device, the display pixel being configured to receive a first voltage and a first binary signal, the light emitting device being powered with the first voltage, the display pixel further comprising a power supply circuit configured to provide a supply voltage, lower than the first voltage, for powering the driver circuit, the power supply circuit comprising a first capacitor configured to be charged with a reference supply voltage from the first binary signal, said power supply circuit further comprising a voltage follower circuit providing the supply voltage at its output, the voltage follower circuit being powered by the first voltage, being connected to the first capacitor, and being configured to maintain the supply voltage equal to the reference supply voltage.

A charge of the first capacitor occurs when the first binary signal is in a logic state "1". Therefore, the reference drop voltage is generated when the first binary signal is in the high state "1". Therefore, the reference drop voltage can be obtained accurately because it is generated from the first binary signal which is accurately supplied. The operational amplifier provides the drop voltage and supplies the electronic components of the driver circuit connected to the output of the operational amplifier with a current which is advantageously drawn from the source of the high reference potential and not from the pad receiving the first binary signal. The reference drop voltage is used only as a comparison voltage for generating the drop voltage. Therefore, the discharge of the first capacitor occurs mainly by very small leakage currents but not by the power consumption of components of the driver circuit.

In one embodiment, the display pixel includes at least first, second, and third electrically conductive bonding pads, the first binary signal being received on the third electrically conductive bonding pad, the first binary signals alternating between a second voltage, lower than the first voltage, and a third voltage, lower than the second voltage, the driver circuit being configured to drive the light-emitting device from the first binary signal received on the third electrically conductive bonding pad. Charging of the first capacitor is performed solely by currents drawn from the third electrically conductive bonding pad.

According to one embodiment, the power supply circuit comprises a first branch connecting the third electrically conductive connection pad and the first capacitor, the first branch comprising only one or more Schottky diodes, diodes and/or transistors. The component on the first branch advantageously prevents a discharge of the first capacitor through the third electrically conductive connection pad when the first binary signal is in a logic state "0".

According to one embodiment, the power supply circuit further comprises a second capacitor, the voltage follower circuit being configured to charge the second capacitor with the supply voltage. The second capacitor allows for better stabilization of the supply voltage, particularly when a high current is drawn by the components of the driver circuit supplied with the supply voltage.

According to one embodiment, the voltage follower circuit is powered by the first voltage through a switch and the power supply circuit further comprises a trigger circuit configured to control the switch, preferably on the basis of the first binary signal. The voltage follower circuit can be activated, by closing the switch, only when high inrush currents appear. This advantageously makes it possible to reduce the power consumption of the voltage follower circuit.

According to one embodiment, the trigger circuit is configured to close the switch, for a given duration, after each rising edge and/or each falling edge of the first binary signal.

According to one embodiment, the second capacitor is configured to be charged by the first binary signal. A charge of the second capacitor occurs when the first binary signal is in a logic state "1". The charging of the second capacitor is also advantageously carried out by means of the first binary signal.

According to one embodiment, the power supply circuit comprises a second branch connecting the third electrically conductive connection pad and the second capacitor, the second branch comprising only one or more Schottky diodes, diodes and/or transistors. The component on the second branch advantageously prevents a discharge of the second capacitor through the third electrically conductive connection pad when the first binary signal is in a logic state "0".

According to one embodiment, the display pixel is to receive a second binary signal, and the first capacitor is configured to be charged with the reference supply voltage from the first binary signal and the second binary signal. Charging of the first capacitor is advantageously improved because it is performed by both the first binary signal and the second binary signal.

According to one embodiment, the display pixel comprises at least a fourth electrically conductive bonding pad, the second binary signal being received on the fourth electrically conductive bonding pad, the driver circuit being configured to drive the light-emitting device from the first binary signal received on the third electrically conductive bonding pad and the second binary signal received on the fourth electrically conductive bonding pad, the second binary signal alternating between the second voltage and the third voltage.

According to one embodiment, the power supply circuit comprises a third branch connecting the fourth electrically conductive connection pad and the first capacitor, the third branch comprising only one or more Schottky diodes, diodes and/or transistors. The component on the third branch advantageously prevents a discharge of the first capacitor through the fourth electrically conductive connection pad when the second binary signal is in a logic state "0".

According to one embodiment, the second capacitor is also configured to be charged by the second binary signal. The charging of the second capacitor is advantageously improved because it is also carried out by the second binary signal.

According to one embodiment, the power supply circuit comprises a fourth branch connecting the fourth electrically conductive connection pad and the second capacitor, the fourth branch comprising only one or more Schottky diodes, diodes and/or transistors. The component on the fourth branch advantageously prevents a discharge of the second capacitor through the fourth electrically conductive connection pad when the second binary signal is in a logic state "0".

According to one embodiment, the voltage follower circuit comprises an operational amplifier having a non-inverting input, an inverting input, and an output, the non-inverting input of the operational amplifier being connected to the first capacitor, the output of the operational amplifier providing the supply voltage, and the inverting input of the operational amplifier being connected to the output of the operational amplifier.

According to one embodiment, each of the first capacitors and the second capacitors comprises an electrode connected to the second electrically conductive bonding pad.

According to one embodiment, the driver circuit is configured to determine a digital signal from values of the received second binary signal relative to the first pulses of the first binary signal and to control the light emitting device based on the digital signal.

According to one embodiment, the driver circuit is configured to control the light emitting device in pulse width modulation based on the digital signal.

According to one embodiment, the driver circuit is configured to turn on or off the light emitting device at the frequency of the second pulses of the first binary signal at the second voltage or the third voltage.

According to one embodiment, the display pixel comprises only the first, second and third electrically conductive bonding pads.

According to one embodiment, the first binary signal is a first binary voltage and the second binary signal is a second binary voltage.

An embodiment also provides a display screen comprising an array of display pixels as defined above, the display screen further comprising circuitry for providing, for each display pixel, the first voltage between the first and second electrically conductive bonding pads, the first binary signal on the third electrically conductive bonding pad and the second binary signal on the fourth electrically conductive bonding pad.

An embodiment also provides a method of controlling a display screen comprising a matrix of display pixels as defined above, the method comprising providing, for each display pixel, the first voltage between the first and second electrically conductive bonding pads, providing the first binary signal on the third electrically conductive bonding pad and providing the second binary signal on the fourth electrically conductive bonding pad.

In one embodiment, the method includes providing the first binary signal and the second binary signal such that, in operation, the ratio of the average duration that at least one of the first binary signal and the second binary signal is at the second voltage to the sum of the average duration that the first binary signal and the second binary signal are at the third voltage and the average duration that at least one of the first binary signal and the second binary signal is at the second voltage is greater than 75%.

According to one embodiment, the method comprises providing the first binary signal and the second binary signal such that, at any time of the operation, at least one of the first binary signal and the second binary signal is at the second voltage.

According to one embodiment, the reference supply voltage is less than 10% lower than the second voltage and wherein the supply voltage is less than 10% lower than the second voltage.

These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in connection with the attached figures, among which:

there partially and schematically represents an example of a display screen;

there is a very simplified cross-sectional view of an example display pixel;

there is a bottom view of the display pixel of the ;

there represents a block diagram of an embodiment according to the invention of a display pixel of the display screen of the ;

there represents a block diagram of an embodiment of a circuit for charging a capacitor of the display pixel of the ;

there represents a block diagram of another embodiment of a circuit for charging a capacitor of the display pixel of the ;

there represents a block diagram of another embodiment of a circuit for charging a capacitor of the display pixel of the ;

there represents examples of timing diagrams of signals of the display pixel of the according to one embodiment of a method of operating the display screen;

there represents a block diagram of another embodiment of a circuit for charging a capacitor of the display pixel of the ;

there represents a block diagram of another embodiment of a circuit for charging a capacitor of the display pixel of the ;

there represents a block diagram of another embodiment of a circuit for charging a capacitor of the display pixel of the ;

there represents a block diagram of another embodiment of a circuit for charging a capacitor of the display pixel of the ;

there represents an electrical diagram of an embodiment of a portion of the capacitor charging circuit of the , 9, 11 or 12;

there represents an electrical diagram of an embodiment of another part of the capacitor charging circuit of the , 9, 11 or 12;

there represents a more detailed block diagram of an embodiment according to the invention of the display pixel of the ;

there represents examples of timing diagrams of signals of the display pixel of the according to one embodiment of a method of operating the display screen;

there represents examples of timing diagrams of signals of the display pixel of the according to another embodiment of a method of operating the display screen;

there represents an electrical diagram of an embodiment of the current source of the display pixel of the ; And

there represents an electrical diagram of another embodiment of the current source of the display pixel of the .

The same elements have been designated by the same references in the different figures. In particular, the structural and/or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed.

Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected together, this means that these two elements can be connected or be connected through one or more other elements.

Furthermore, a signal that alternates between a first constant state, for example a low logic state, denoted "0", and a second constant state, for example a high logic state, denoted "1", is called a "binary signal". The high and low states of different binary signals in the same electronic circuit may be different. In practice, binary signals may correspond to voltages or currents that may not be perfectly constant in the high or low state.

Furthermore, in the following description, the "power terminals" of an insulated gate field effect transistor, or MOS transistor, are referred to as the source and drain of the MOS transistor.

Furthermore, unless otherwise indicated, when speaking of a voltage at a conductive pad, we consider the difference between the potential at said conductive pad and a reference potential, for example, ground, assumed to be equal to 0 V.

Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%. In addition, the expression "substantially constant" means varying by less than 10% over time relative to a reference value.

In the following description, embodiments are described for a color display screen comprising color display pixels, each display pixel comprising light-emitting diodes adapted to emit radiation of different colors. However, these embodiments also apply to a monochrome display screen comprising monochrome display pixels, each monochrome display pixel comprising a light-emitting diode or only light-emitting diodes adapted to emit radiation of a single color.

There partially and schematically represents a known example of a display screen 10. The display screen 10 comprises display pixels 12 _i,j , for example arranged in M rows and N columns, M being an integer varying from 1 to 8,000 and N being an integer varying from 1 to 16,000, i being an integer varying from 1 to M and j being an integer varying from 1 to N. As an example, in , M and N are equal to 6. Each display pixel 12 _i,j is connected to a source of low reference potential Gnd, for example, ground, via an electrode 14 _i and to a source of high reference potential Vcc via an electrode 16 _j . As an example, the electrodes 14 _i are shown as being aligned along the rows in and the 16 _j electrodes are shown as being aligned along the columns in , the reverse structure being possible. The supply voltage of the display screen 10 corresponds to the voltage between the high reference potential Vcc and the low reference potential Gnd and is denoted Vcc as the high reference potential. The supply voltage Vcc depends in particular on the structure of the light-emitting diodes and the technology by which the light-emitting diodes are manufactured. For example, the supply voltage Vcc can be of the order of 3.5 V to 5.5 V.

For each row, the display pixels 12 _i,j in the row are connected to a row electrode 18 _i . For each column, the display pixels 12 _i,j in the column are connected to a column electrode 20 _j . The display screen 10 comprises a selection circuit 22 connected to the row electrodes 18 _i and adapted to provide a selection and synchronization signal Com _i on each row electrode 18 _i . The display screen 10 comprises a data supply circuit 24 connected to the column electrodes 20 _j and adapted to provide a data signal Data _j on each column electrode 20 _j . The selection circuit 22 and the control circuit 24 are controlled by a circuit 26, comprising for example a processor.

There is a very simplified cross-sectional view of a known example of a 12 _i,j display pixel and the is a bottom view of the display pixel 12 _i,j . Each display pixel 12 _i,j comprises a control circuit 30 covered by a display circuit 32. The display circuit 32 comprises at least one light-emitting diode, LED, preferably at least three light-emitting diodes LED. The display pixel comprises a lower surface 34 and an upper surface 35 opposite the lower surface 34, the surfaces 34 and 35 preferably being planar and parallel. The control circuit 30 further comprises conductive connection pads P_Gnd, P_Vcc, P_Col, P_Row on the lower surface 34. The control circuit 30 may correspond to an integrated circuit comprising electronic components, in particular insulated gate field effect transistors, also called MOS transistors, or thin film transistors, also called TFTs. Preferably, the display circuit 32 comprises only LEDs and the conductive elements of these LEDs and the control circuit 30 comprises all the electronic components necessary for controlling the LEDs of the display circuit 32. Alternatively, the display circuit 32 may comprise other electronic components in addition to the LEDs. The LEDs may be 2D LEDs, also called planar LEDs, comprising a stack of planar layers, or 3D LEDs, each comprising a three-dimensional semiconductor element covered with an active area. , the LEDs are shown as being connected to a common anode. However, it may be desirable to arrange the LEDs in another configuration. For example, the LEDs may be connected to a common cathode, or may be connected independently of each other.

According to one embodiment, the display pixel 12 _i,j comprises three light sources emitting light at first, second and third wavelengths. According to one embodiment, the first wavelength corresponds to blue light and is in the range of 430 nm to 490 nm. According to one embodiment, the second wavelength corresponds to green light and is in the range of 510 nm to 570 nm. According to one embodiment, the third wavelength corresponds to red light and is in the range of 600 nm to 700 nm.

Each conductive pad P_Gnd, P_Vcc, P_Col, P_Row is intended to be connected to one of the electrodes 14 _i , 16 _j , 18 _i , 20 _j shown schematically in . The first conductive pad P_Vcc is connected to the electrodes 14 _i and receives the high reference potential Vcc. The second conductive pad P_Gnd is connected to the electrodes 16 _j and receives the low reference potential Gnd. The third conductive pad P_Col is connected to the column electrodes 20 _j and receives the data signal Data _j . The fourth conductive pad P_Row is connected to the row electrodes 18 _i and receives the selection and synchronization signal Com _i . The dimensions of the conductive pads P_Gnd, P_Vcc, P_Col, P_Row and the structure of the conductive pads P_Gnd, P_Vcc, P_Col, P_Row on the surface 34 are notably imposed by the rules for drawing the display pixel 12 _i,j and by the method for assembling display pixels 12 _i,j in the display screen 10. According to one embodiment, in the bottom view, the display pixel 12 _i,j has dimensions of less than 200 µm.

There represents an example of a block diagram of a display pixel 12 _i,j of the display screen 10.

According to one example, the display pixel 12 _i,j comprises at least three light-emitting diodes, with only one light-emitting diode LED being shown in . Each light-emitting diode LED is connected in series to a controllable current source CS. In the present example, for each light-emitting diode LED, the anode of the light-emitting diode LED is for example connected to the conductive pad P_Vcc receiving the high reference potential Vcc and the cathode of the light-emitting diode LED is for example connected to a terminal of the controllable current source CS, the other terminal of the controllable current source CS being connected to the conductive pad P_Gnd receiving the low reference potential Gnd. According to a variant, for each light-emitting diode LED, the cathode of the light-emitting diode LED is for example connected to the conductive pad P_Gnd receiving the low reference potential Gnd and the anode of the light-emitting diode LED is connected to a terminal of the controllable current source CS, the other terminal of the controllable current source CS being connected to the conductive pad P_Vcc receiving the reference potential Vcc.

The display pixel 12 _i,j further comprises a circuit 40 for driving the controllable current source CS. The driver circuit 40 may in particular comprise electronic components such as MOS transistors or TFTs. The driver circuit 40 may be formed, in whole or in part, in the control circuit 30. The driver circuit 40 may correspond mainly to a logic circuit.

It may be desirable to use a reduced supply voltage Vdd, lower than the supply voltage Vcc, for example lower than 4 V, in particular, of the order of 1 V or 1.8 V, to power the electronic components of the driver circuit 40, this reduced supply voltage corresponding for example to the voltage likely to be applied between the power terminals of the MOS transistors. To do this, the display pixel 12 _i,j comprises a supply circuit 60 which supplies the reduced supply voltage Vdd. The supply circuit 60 receives the high reference potential Vcc, and at least one of the selection signal Com _i and the data signal Data _j and supplies the reduced supply voltage Vdd. As an example, in , the power supply circuit is shown receiving the high reference potential Vcc, the selection signal Com _i and the data signal Data _j .

According to one embodiment, the selection and synchronization signal Com _i , received at the conductive pad P_Row of each display pixel 12 _i,j , is a binary signal alternating between a low state "0" and a high state "1", the low state corresponding to the low reference potential Gnd and the high state "1" corresponding to a low voltage, substantially equal to the reduced supply voltage Vdd. The data signal Data _j is a binary signal alternating between a low state "0" and a high state "1", the low state corresponding to the low reference potential Gnd and the high state "1" corresponding to a low voltage, substantially equal to the reduced supply voltage Vdd.

There represents a block diagram of an embodiment of the power supply circuit 60. The power supply circuit 60 comprises a first capacitor C1 and a first diode D1 connecting, to a first electrode of the capacitor C1, a conductive pad of the display pixel 12 _i,j receiving a signal that does not correspond to a constant voltage. In the present embodiment, the diode D1 connects the conductive pad P_Row receiving the binary signal Com _i to the first electrode of the capacitor C1. According to a variant, the diode D1 can connect the conductive pad P_col receiving the binary signal Data _j to the first electrode of the capacitor C1. In the present embodiment, the anode of the diode D1 is connected to the conductive pad P_Row and the cathode of the diode D1 is connected to the first electrode of the capacitor C1. The capacitor C1 has a second electrode receiving the low reference potential Gnd. The voltage across the capacitor C1 corresponds to a reduced reference supply voltage Vdd_ref. Diode D1 can correspond to a Schottky diode, a common diode or a MOS transistor mounted as a diode.

The power supply circuit 60 further comprises an operational amplifier OAmp having a non-inverting input (+), an inverting input (-) and an output. The operational amplifier OAmp is connected as a voltage follower circuit. The non-inverting input (+) is connected, preferably connected, to the first electrode of the capacitor C1. The inverting input (-) of the operational amplifier Oamp is connected, preferably connected, to the output of the operational amplifier Oamp. The output of the operational amplifier Oamp provides the reduced voltage Vdd. The power supply of the operational amplifier Oamp is obtained by connecting the operational amplifier Oamp to the high reference voltage Vcc and the low reference voltage Gnd. The reduced voltage Vdd is used for the power supply of the electrical components of the driver circuit 40, in particular the MOS transistors.

A charge of capacitor C1 is performed when the selection and synchronization signal Com _i is at a logic state "1". Diode D1 prevents the discharge of capacitor C1 through the P_Row pad when the selection and synchronization signal Com _i is at a logic state "0". The charge of capacitor C1 is performed only by currents drawn from the P_Row pad through diode D1. Therefore, the reference lowered supply voltage Vdd_ref is generated when the synchronization signal Com _i is equal to the high state "1". Therefore, the reference lowered supply voltage Vdd_ref can be obtained accurately because it is generated from the selection and synchronization signal Com _i which is accurately supplied by the selection circuit 22.

The operational amplifier OAmp maintains equal the voltage at its non-inverting input (+) and the voltage at its inverting input (-), i.e. the voltages Vdd_ref and Vdd. Consequently, the operational amplifier Oamp provides a reduced voltage Vdd and supplies the electronic components of the driver circuit 40 connected to the output of the operational amplifier Oamp with a current drawn from the P_Vcc pad receiving the high reference potential and not from the P_Row pad receiving the selection and synchronization signal Com _i . The reduced reference voltage Vdd_ref is used only as a comparison voltage for the generation of the reduced voltage Vdd. Consequently, the discharge of the capacitor C1 is carried out essentially by extremely low leakage currents but not by the electrical consumption of the components of the driver circuit 40.

There represents a block diagram of another embodiment of the power supply circuit 60. The power supply circuit 60 represented in includes all the elements of the power supply circuit 60 shown in and further comprises a capacitor C2 having a first electrode connected, preferably connected, to the output of the operational amplifier Oamp. The capacitor C2 may have a second electrode receiving the low reference potential Gnd. The voltage across the capacitor C2 corresponds to the reduced supply voltage Vdd. The capacitor C2 makes it possible to obtain better stabilization of the supply voltage Vdd, in particular when a high current is drawn by the components of the driver circuit 40 supplied with the supply voltage Vdd.

There represents a block diagram of another embodiment of the power supply circuit 60. The power supply circuit 60 represented in includes all the elements of the power supply circuit 60 shown in and further comprises a controllable switch SW. The operational amplifier OAmp is connected, preferably connected, to the conductive pad P_Vcc receiving the high reference voltage Vcc by means of the controllable switch SW. The power supply circuit 60 further comprises a trigger circuit 62 configured to provide a binary signal Ctrl controlling the switch SW.

When the switch SW is closed, the operational amplifier OAmp is powered by the supply voltage Vcc. The operational amplifier OAmp therefore maintains equal the voltage at its non-inverting input (+) and the voltage at its inverting input (-), i.e. the voltages Vdd_Ref and Vdd. Consequently, a charge of the capacitor C2 can be done by means of the operational amplifier OAmp, i.e. by a current drawn from the P_Vcc pad receiving the high reference potential Vcc. When the switch SW is open, the operational amplifier OAmp is not powered by the supply voltage Vcc and does not charge the capacitor C2. The charge of the capacitor C2 is done by a current drawn from the P_Row pad or by a current drawn from the P_Vcc pad.

The inventors noted that the highest inrush currents drawn by the components of the driver circuit 40 occur just after a rising and/or falling edge of the signal that synchronizes the operation of the driver circuit 40, in particular the switching between on and off states of the transistors of the driver circuit 40. According to one embodiment, the operation of the driver circuit 40 is synchronized by the selection and synchronization signal Com _i . The inventors noted that the highest inrush currents drawn by the components of the driver circuit 40 occur just after an edge of the binary selection and synchronization signal Com _i . In this embodiment, the trigger circuit 62 is connected, preferably connected, to the P_Row pad receiving the binary selection and synchronization signal Com _i and provides the trigger signal Ctrl based on the selection and synchronization signal Com _i such that the switch SW is closed during each current draw of the driver circuit 40. Therefore, the current, during each current draw of the driver circuit 40, is drawn from the P_Vcc pad receiving the high reference voltage Vcc and not from the P_Row pad receiving the selection and synchronization signal Com _i and the P_Col pad receiving the data signal Data _j . This is advantageous because, in particular for the display screen 10 comprising a high number of display pixels 12 _i,j , for example more than 100 display pixels 12 _i,j per row, it may be necessary to provide a damping resistor on each row electrode 18 _i and/or on each column electrode 20 _j in order to prevent oscillations of the voltages on these electrodes. If the current during a current draw of the driver circuit 40 is drawn from the pad P_Row receiving the selection and synchronization signal Com _i and/or the pad P_Col receiving the data signal Data _j , this could lead to a large voltage drop across the damping resistor so that the voltage level of the selection and synchronization signal Com _i and/or the data signal Data _j , reaching some display pixels 12 _i,j , could be too low.

There represents examples, for the display pixels 12 _i,j of the and for the power supply circuit 60 of the , timing diagrams of the selection and synchronization signal Com _i received by the display pixel 12 _i,j , of the current IL drawn by the driver circuit 40 due to the power consumption of the driver circuit 40 and of the signal Ctrl provided by the trigger circuit 62 according to an embodiment of a method of operating the display screen 10. According to one embodiment, the largest inrush currents drawn by the components of the driver circuit 40 occur just after each rising edge of the binary selection and synchronization signal Com _i . The current IL comprises a peak Pk just after each rising edge of the binary selection and synchronization signal Com _i . According to one embodiment, when the binary trigger signal Ctrl is at logic level "0", the switch SW is open and when the binary trigger signal Ctrl is at logic level "1", the switch SW is closed. The trigger circuit 62 sets the trigger signal Ctrl to the logic value "1" for a duration D upon detection of a rising edge of the selection and synchronization signal Com _i . According to one embodiment, the duration D is in the range from 10 ns to 30 ns. According to one embodiment, the trigger circuit 62 comprises logic gates.

There represents a block diagram of another embodiment of the power supply circuit 60. The power supply circuit 60 represented in includes all the elements of the power supply circuit 60 shown in and further comprises a second diode D2 connecting the conductive pad P_Row to the first electrode of the capacitor C2. The anode of the diode D2 is connected to the conductive pad P_Row and the cathode of the diode D2 is connected to the first electrode of the capacitor C2. The diode D2 may correspond to a Schottky diode, a common diode, or a MOS transistor mounted as a diode.

A charge of capacitor C1 and capacitor C2 occurs when the synchronization signal Com _i is at logic level "1". Diode D1 prevents a discharge of capacitor C1 through the P_Row pad when the selection and synchronization signal Com _i is at logic level "0" and diode D2 prevents a discharge of capacitor C2 through the P_Row pad when the selection and synchronization signal Com _i is at logic level "0".

When the switch SW is closed, the operational amplifier OAmp is powered by the supply voltage Vcc. The operational amplifier OAmp then maintains equal the voltage at its non-inverting input (+) and the voltage at its inverting input (-), i.e. the voltages Vdd_ref and Vdd. Consequently, a charge of the capacitor C2 can occur by means of the operational amplifier OAmp, i.e. by a current drawn from the P_Vcc pad receiving the high reference potential Vcc. When the switch SW is open, the operational amplifier OAmp is not powered by the supply voltage Vcc and does not participate in the charging of the capacitor C2. The charging of the capacitor C2 is then carried out by means of a current drawn from the P_Row pad.

There represents a block diagram of another embodiment of the power supply circuit 60. The power supply circuit 60 represented in includes all the elements of the power supply circuit 60 shown in and further comprises a third diode D3 connecting the conductive pad P_Col to the first electrode of the capacitor C1. The anode of the diode D3 is connected to the conductive pad P_Col and the cathode of the diode D3 is connected to the first electrode of the capacitor C1. The diode D3 may correspond to a Schottky diode, a common diode, or a MOS transistor mounted as a diode.

A charge of capacitor C1 occurs when at least one of the selection and synchronization signal Com _i and the data signal Data _j is at logic state "1". Diode D1 prevents a discharge of capacitor C1 through pad P_Row when the selection and synchronization signal Com _i is at logic state "0" and diode D3 prevents a discharge of capacitor C1 through pad P_Col when the data signal Data _j is at logic state "0". The charge of capacitor C1 is only carried out by currents drawn from pad P_Row through diode D1 and/or from pad P_Col through diode D3. Therefore, the reduced reference voltage Vdd_ref is generated when the synchronization signal Com _i and/or the data signal Data _j are at logic state "1". Therefore, the reference decreased voltage Vdd_ref can be obtained accurately because it is generated from the selection and synchronization signal Com _i and the data signal Data _j which are accurately supplied by the selection circuit 22 and the data supply circuit 24.

There represents a block diagram of another embodiment of the power supply circuit 60. The power supply circuit 60 represented in includes all the elements of the power supply circuit 60 shown in and further comprises the third diode D3 connecting the conductive pad P_Col to the first electrode of the capacitor C1, as shown in .

There represents a block diagram of another embodiment of the power supply circuit 60. The power supply circuit 60 represented in includes all the elements of the power supply circuit 60 shown in and further comprises diode D2 connecting conductive pad P_Row to the first electrode of capacitor C1, as shown in , and a fourth diode D4 connecting the conductive pad P_Col to the first electrode of the capacitor C2. The anode of the diode D4 is connected to the conductive pad P_Col and the cathode of the diode D4 is connected to the first electrode of the capacitor C2. The diode D4 can correspond to a Schottky diode, a common diode, or a MOS transistor mounted as a diode.

A charge of capacitor C1 and capacitor C2 occurs when at least one of the selection and synchronization signal Com _i and the data signal Data _j is at the logic state "1". Diode D1 prevents a discharge of capacitor C1 through the pad P_Row when the selection and synchronization signal Com _i is at the logic state "0" and diode D2 prevents a discharge of capacitor C2 through the pad P_Row when the selection and synchronization signal Com _i is at the state "0". Diode D3 prevents a discharge of capacitor C1 through the pad P_Col when the data signal Data _j is at the state "0" and diode D4 prevents a discharge of capacitors C2 through the pad P_Col when the data signal Data _j is at the state "0".

There represents an electrical diagram of an embodiment of the operational amplifier OAmp of FIGS. 5 to 7 and 9 to 12 and of the switch SW of the power supply circuit 60 of the , 9, 11 or 12.

The operational amplifier OAmp comprises a differential pair comprising a MOS transistor T1, for example an N-MOS transistor, and a MOS transistor T2, for example an N-MOS transistor. The gate of the transistor T1 corresponds to the non-inverting input of the operational amplifier OAmp and receives the voltage Vdd_ref. The gate of the transistor T2 corresponds to the inverting input of the operational amplifier OAmp and receives the voltage Vdd. The operational amplifier OAmp further comprises a current mirror comprising a MOS transistor T3, for example a P-MOS transistor, and a MOS transistor T4, for example a P-MOS transistor. The gate of the transistor T3 is connected, preferably connected, to the gate of the transistor T4 and to the drain of the transistor T3. The source of the transistor T3 and the source of the transistor T4 are connected, preferably connected, to a node N. The drain of the transistor T3 is connected, preferably connected, to the drain of the transistor T1. The drain of transistor T4 is connected, preferably connected, to the drain of transistor T2. The operational amplifier OAmp further comprises a transistor T5, for example an N-MOS transistor. The gate of transistor T5 is connected, preferably connected, to node N. The drain of transistor T5 is connected, preferably connected, to the sources of transistors T1 and T2. The source of transistor T5 receives the low reference voltage Gnd. The operational amplifier OAmp further comprises a transistor T6, for example an N-MOS transistor, and a MOS transistor T7, for example an N-MOS transistor. The drain of transistor T6 is connected, preferably connected, to node N. The gate of transistor T6 is connected, preferably connected, to the drain of transistor T2. The source of transistor T7 receives the low reference voltage Gnd. The source of transistor T6 is connected, preferably connected, to the drain of transistor T7. The gate of transistor T7 is connected, preferably connected, to the gate of transistor T5. The source of transistor T6 corresponds to the output of the operational amplifier OAmp.

The switch SW of the power supply circuit 60 comprises a MOS transistor T8, for example a P-MOS transistor, a MOS transistor T9, for example an N-MOS transistor, and a MOS transistor T10, for example an N-MOS transistor. The gate of each transistor T8, T9 and T10 receives a /Ctrl signal which is the opposite of the Ctrl signal provided by the trigger circuit 62. The source of the transistor T8 receives the high reference potential Vcc. The source of the transistor T9 receives the low reference potential Gnd. The drain of the transistor T8 and the drain of the transistor T9 are connected, preferably connected, to the node N. The source of the transistor T10 receives the low reference potential Gnd. The drain of the transistor T10 is coupled, preferably connected, to the drain of the transistor T2. When the Ctrl signal is a logic value "0", the transistors T9 and T10 are in an on state and the transistor T8 is in a blocked state. Node N is substantially at the low reference voltage Gnd and the drain of transistor T2 is substantially at the low reference voltage Gnd. The operational amplifier OAmp is not electrically powered and does not operate. When the Ctrl signal is a logic value "1", transistors T9 and T10 are in a blocked state and transistor T8 is in an on state. Node N is substantially at the high reference voltage Vcc and the drain of transistor T2 can rise from the low reference voltage Gnd. The operational amplifier OAmp is electrically powered by the supply voltage Vcc and can operate.

There represents an electrical diagram of an embodiment of the trigger circuit 62 of the power supply circuit 60 of the , 9, 11 or 12. The trigger circuit 62 comprises a delay circuit DEL receiving the selection and synchronization signal Com _i and providing a signal DCom corresponding to the selection and synchronization signal Com _i shifted in time by the duration D. The trigger circuit 62 further comprises an inverter INV and a logic AND gate, AND. The input of the inverter INV is connected, preferably connected, to the output of the delay circuit DEL. The inverter INV receives the signal DCom and provides a signal /DCom, which is the opposite of the signal DCom. A first input of the logic AND gate is connected, preferably connected, to the output of the inverter INV. The first input of the logic AND gate receives the signal /DCom and a second input of the logic AND gate receives the selection and synchronization signal Com _i . The output of the logic AND gate provides the trigger signal Ctrl. When the selection and synchronization signal Com _i remains at the logic value "0" or "1", the /DCom signal has the opposite value of the selection and synchronization signal Com _i so that the Ctrl signal is at the logic value "0". When the selection and synchronization signal Com _i changes from the logic value "0" to the logic value "1", that is, for a rising edge of the selection and synchronization signal Com _i , the /DCOM signal remains for a duration D at the previous value of the signal Com _i , that is, "0". Therefore, the two inputs of the AND logic gate are at the logic value "1" and the Ctrl signal is at the logic value "1". When the selection and synchronization signal Com _i changes from the logic value "1" to the logic value "0", that is, for a falling edge of the selection and synchronization signal Com _i , the /DCom signal remains for a duration D at the previous value of the signal Com _i , which is "1". Therefore, both inputs of the AND logic gate are at logic value "0" and the Ctrl signal is at logic value "0".

There represents a more detailed block diagram of an embodiment of the driver circuit 40 of the display pixel 12 _i,j of the configured to drive LEDs using pulse width modulation (PWM).

The driver circuit 40 comprises a circuit 46 (Mode selection) connected to the conductive pad P_Col which receives the data signal Data _j and connected to the conductive pad P_Row which receives the selection and synchronization signal Com _i , and configured to provide a clock signal Clk and data Data to a storage circuit 48 (Color Data registers) or to provide a PWM signal to implement a pulse width modulation to a circuit 50 (LED driver) to control the controllable current source CS associated with each light-emitting diode LED. The storage circuit 48 is configured to store color signals R, G, B representative of the image pixel to be displayed. The circuit 50 is configured to control the controllable current sources CS connected to the light-emitting diodes LED with signals I_red, I_green and I_blue, obtained from the color signals R, G, B and from the PWM signal. In the present embodiment, the data Data may correspond to the data signal Data _j and the clock signal Clk is obtained from the selection and synchronization signal Com _i .

Alternatively, the data signals Data _j allow both the determination, by each display pixel 12 _i,j , of a clock signal and the color signals R, G, B representative of the desired light intensities for the radiation at the first, second and third wavelengths. In this case, the driver circuit 40 further comprises a circuit connected to the conductive pad P_Col which receives the data signal Data _j and provides, on the basis of the data signal Data _j , the clock signal Clk and the data Data. The circuit 46 (Mode selection) receives the signals Clk and Data, and is connected to the conductive pad P_Row receiving the selection and synchronization signal Com _i , and is configured to provide the signals Clk and Data to the storage circuit 48 or to provide the PWM signal to the circuit 50.

There represents a timing diagram of signals received by the display pixel 12 _i,j having the structure shown in for an embodiment of a method of displaying an image on the display screen 10.

The potentials Vcc and Gnd are substantially constant. The image pixels of a new image to be displayed are displayed successively from the row of rank 1 to the row of rank M. The frame duration T denotes the duration separating two successive selections of the same row of the display screen 10. Timing diagrams of the Com ₁ and Data ₁ signals will be detailed for the row of rank 1, knowing that the timing diagrams of the Com _i signals are similar to the timing diagram of the Com ₁ signal, although shifted in time. The Data ₁ data signal contains a succession of bits having the same duration and in the "1" or "0" state, represented by rectangles containing a cross in . Displaying a new pixel by a display pixel 12 _1,j , where j varies from 1 to N from the row of rank 1 comprising a first phase P1 followed by a second phase P2. During the phase P1, data signals Data _j are transmitted to each display pixel 12 _1,j of the row of rank 1, only the signal Data _j being represented in . During the second phase P2, the light-emitting diodes of each display pixel 12 _1,j are controlled from the color signals R, G, B determined on the basis of the data signals _{Data j} .

During the first phase P1, the selection and synchronization signal Com ₁ comprises successive pulses regularly spaced at the state "1". The succession of pulses at the state "1" of the signal Com ₁ is detected by the circuit 46 of each display pixel 12 _1,j of the row of rank 1 and thus makes it possible to select the display pixels 12 _1,j of this row, while the display pixels of the other rows are not selected. During the first phase P1, the data signals Data _j are transmitted on the column electrodes 20 _j . For each display pixel 12 _1,j , the circuit 44 determines the clock signal Clk on the basis of the pulses of the selection and synchronization signal Com _i and the data Data on the basis of the data signal Data _j . The circuit 46 of each display pixel 121,j of the selected row, provides, at the frequency of the clock signal Clk, the data Data which are stored in the circuit 50 in the form of the digital signals R, G, B which have their bits provided by the successive values of the signal Data. The end of the first period P1 for a row corresponds to the beginning of the first period P1 for the following row.

Alternatively, during the first phase P1, the selection and synchronization signal Com ₁ is set to the "0" state and the clock signal Clk and data signal Data are determined on the basis of the data signal Data _j . For example, each pulse of the data signal Data _j may have a first duration or a second duration, longer than the first duration. The signal Clk may correspond to a sequence of pulses of the same durations whose rising edges coincide, with a possible constant offset, with the rising edges of the pulses of the data signal Data _j . The data Data may correspond to a binary signal at the "0" state when the pulse of the signal Data _j has the first duration, and at the "1" state when the pulse of the signal Data _j has the second duration. Circuit 46, selected by signal Com1 at state "0", provides, at the frequency of clock signal Clk, the data Data which are stored in circuit 50 in the form of digital signals R, G, B having their bits provided by the successive values of signal Data. The end of the first period P1 for a row corresponds to the start of the first period P1 for the following row.

According to one embodiment, the light-emitting diodes of the display pixel 12 _1,j are controlled by pulse width modulation or PWM control. To do this, during the second phase P2, the selection and synchronization signal Com ₁ has the repetition of a succession of pulses in state "1" which are transmitted by the circuit 46 of each display pixel 12 _1,j of the row of rank 1 to the circuit 50 (PWM signal) to synchronize the operation of the circuit 50 for the control of the light-emitting diodes LED by pulse width modulation. The number of pulses in the succession corresponds to the number of bits of each digital signal R, G, B. For example, when the controllable current source CS comprises a MOS transistor in series with a current source, this transistor is on or off, at the frequency of the PWM pulses, depending on the value "0" or "1" of each bit of the color signal R, G or B, starting from the most significant bit, this transistor being kept on or off until the next pulse of the signal Com ₁ . The duration between two successive pulses of the signal Com ₁ is divided by two each time, so that the total duration during which the light-emitting diode is on depends on the value of the color signal R, G or B. The succession of pulses of the signal Com ₁ is repeated until the first following phase P1 of the row of rank 1, a single repetition being shown as an example in . Alternatively, the transistor of the controllable current source CS is turned on or off at the frequency of the PWM pulses, depending on the value "0" or "1" of each bit of the R, G or B signal, starting with the most significant bit, this transistor being kept on or off until the next pulse of the Com ₁ signal. The duration between two successive pulses of the Com ₁ signal is then multiplied by two each time, so that the total duration during which the light-emitting diode is on depends on the value of the R, G or B color signal.

In the present embodiment, the selection and synchronization signal Com _i is most of the time in the state "1". This advantageously makes it possible to obtain a more frequent recharge of the capacitors C1 or C2 of the circuit 60 to provide the reduced voltage Vdd, and thus to further reduce the capacitance of the capacitors C1 and C2. As a variant, the selection and synchronization signal Com _i can be inverted with respect to what is shown in .

Generally, according to one embodiment, the ratio of the average duration during which at least one of the signal Com _i and the signal Data _j is at the reduced voltage Vdd to the sum of the average duration during which the signal Com _i and the signal Data _j are at the low reference potential Gnd and the average duration during which at least one of the signal Com _i and the signal Data _j is at the voltage Vdd is greater than 75%, preferably greater than 85%, more preferably greater than 95%.

There represents a timing diagram of signals received by the display pixel 12 _i,j having the structure shown in according to another embodiment of a method of displaying an image on the display screen 10.

In the , the timing diagrams of the Com ₁ , Com ₂ , Com ₃ and Data ₁ signals for the rows of rank 1, 2 and 3 and the column of rank 1 are shown, knowing that the timing diagrams of the other Com _i signals are similar to the timing diagram of the Com ₁ signal although shifted in time. The timing diagrams of the Vcc, Gnd signals, not shown and of the Com _i signals of the embodiment shown in may be identical to those shown in . The timing diagrams of the Com _i signals and the Data _j data signals of the embodiment shown in are identical to those shown in with the difference that each phase P1 comprises two successive phases P1.1 and P1.2. During phase P1.1, each data signal Data _j , j varying from 1 to N, is maintained at the state "1" when one of the signals Com _i , i varying from 1 to N, is at the state "0" for a long duration during the selection of the row of rank i. During phase P1.2 which follows phase P1.1, the data signals Data _j are transmitted on the column electrodes 20 _j and are acquired by the display pixels 12 _i,j of the row of rank i. This embodiment is advantageous because, at any time, for each display pixel 12 _i,j , at least one of the signals Com _i and Data _j received by the display pixel 12 _i,j is at the state "1".

In the embodiments described above, the LEDs of the display pixel 121,j are controlled by pulse width modulation. However, the control of the LEDs of the display pixel 121,j may be different from a control by pulse width modulation. According to one embodiment, the control of the LEDs is a control of the current level.

There represents an embodiment of the current source CS, in which the current source CS comprises N controllable elementary sources CS1 to CSN, where N is an integer greater than or equal to 2. Preferably, N is equal to the number of bits of the digital color signal R, G or B. In the present embodiment, the elementary current sources CSj, j ranging from 1 to N, are assembled in parallel between a node A1 and a node A2. When the light-emitting diodes LED are connected in common anode, as shown in , for each color, node A1 is connected, preferably connected, to the cathode of the light-emitting diode LED corresponding to the color considered, and node A2 is folded, preferably connected, to the conductive pad P_Gnd connected to the low reference potential source Gnd. When the light-emitting diodes LED are assembled with a common cathode, node A1 is connected, preferably connected, to a conductive pad P_Vcc folded to the high reference potential source Vcc and, for each color, node A2 is coupled, preferably connected, to the anode of the light-emitting diode LED corresponding to the color considered.

Each elementary current source CSj is activated or deactivated by the circuit 50 by means of a control signal Cj. For example, the control signal Cj is a binary signal corresponding to the bit of rank j of the digital color signal R, G or B. The elementary current source CSj is deactivated when the signal Cj is in a first state, for example, the low state, and the current source CSj is activated when the signal Cj is in a second state, for example, the high state.

The greater the number of activated current sources CSj, the greater the intensity of the current ICS. According to one embodiment, the current source CS is capable of supplying a current ICS having an intensity at one of a plurality of constant levels and having its level depending on the number of general light-emitting diodes that are conductive. The currents provided by the elementary current sources CSj of the current source CS may be identical or different. According to one embodiment, each elementary current source CSj is capable of supplying a current of intensity I*2j-1. The current source CS is then adapted to supply a current having an intensity ICS which can, according to the control signals Cj, take any value k*I, with k varying from 0 to 2M-1.

According to one embodiment, the control of the light-emitting diodes LED is an analog control.

There represents an embodiment of a current source CS, in which the current source comprises a MOS transistor T connected in series with a resistor Rs between nodes A1 and A2, nodes A1 and A2 being defined as previously in relation to the 8. The current source CS further comprises a digital-to-analog converter DAC receiving the digital color signal R, G or B and an operational amplifier OA whose inverting input (-) is coupled, preferably connected, to the midpoint between the resistor Rs and the MOS transistor and whose non-inverting input (+) receives the analog signal provided by the digital-to-analog converter DAC. The transistor T is made more or less conductive depending on the digital color signal R, G or B transmitted to the digital-to-analog converter DAC.

Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art. In particular, the PWM modulation may be generated internally in the control circuit 30 of the pixel display 12i,j to avoid using the Comi signal to generate it. Other embodiments may also not use PWM modulation but linear control of the LEDs. Other embodiments may also use other electro-optical components such as organic light-emitting diodes.

Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims (26)

Display pixel (12 _i,j ) for a display screen (10), comprising at least one light-emitting device (LED), a driver circuit (40) for driving the light-emitting device (LED), the display pixel (12 _i,j ) being configured to receive a first voltage (Vcc) and a first binary signal (Com _i ), the light-emitting device being supplied with the first voltage (Vcc), the display pixel further comprising a power supply circuit (60) configured to provide a supply voltage (Vdd), lower than the first voltage (Vcc), for supplying the driver circuit (40), the power supply circuit (60) comprising a first capacitor (C1) configured to be charged with a reference supply voltage (Vdd_Ref) from the first binary signal (Com _i ), said power supply circuit (60) further comprising a voltage follower circuit (OAmp) providing the supply voltage (Vdd) at its output, the voltage follower circuit (OAmp) being supplied by the first voltage (Vcc), being connected to the first capacitor (C1), and being configured to maintain the supply voltage (Vdd) equal to the reference supply voltage (Vdd_Ref). Display pixel (12 _i,j ) according to claim 1, comprising at least first, second and third electrically conductive bonding pads (P_Vcc, P_Gnd, P_Row), the first voltage (Vcc) being received between the first and second electrically conductive bonding pads (P_Vcc, P_Gnd), the first binary signal (Com _i ) being received on the third electrically conductive bonding pad (P_Row), the first binary signals alternating between a second voltage, lower than the first voltage (Vcc), and a third voltage (Gnd), lower than the second voltage, the driver circuit (40) being configured to drive the light emitting device (LED) from the first binary signal (Com _i ) received on the third electrically conductive bonding pad (P_Row). The display pixel (12 _i,j ) of claim 2, wherein the power supply circuit (60) comprises a first branch connecting the third electrically conductive bonding pad (P_Row) and the first capacitor (C1), the first branch comprising only one or more Schottky diodes, diodes and/or transistors. A display pixel (12 _i,j ) according to any one of claims 1 to 3, wherein the power supply circuit (60) further comprises a second capacitor (C2), the voltage follower circuit (OAmp) being configured to charge the second capacitor (C2) with the supply voltage (Vdd). Display pixel (12 _i,j ) according to claim 4, wherein the voltage follower circuit (OAmp) is supplied by the first voltage (Vcc) through a switch (SW) and wherein the supply circuit (60) further comprises a trigger circuit (62) configured to control the switch (SW). Display pixel (12 _i,j ) according to claim 5, wherein the trigger circuit (62) is configured to control the switch (SW) based on the first binary signal (Com _i ). Display pixel (12 _i,j ) according to claim 6, wherein the trigger circuit (62) is configured to close the switch (SW), for a given duration (D), after each rising edge and/or each falling edge of the first binary signal (Com _i ). Display pixel (12 _i,j ) according to claim 4 or 5, wherein the second capacitor (C2) is also configured to be charged by the first binary signal (Com _i ). A display pixel (12 _i,j ) according to claims 2 and 8, wherein the power supply circuit (60) comprises a second branch connecting the third electrically conductive bonding pad (P_Row) and the second capacitor (C2), the second branch comprising only one or more Schottky diodes, diodes and/or transistors. A display pixel (12 _i,j ) according to any one of claims 4 to 9, wherein each of the first capacitor (C1) and second capacitor (C2) comprises an electrode connected to the second electrically conductive bonding pad (P_Gnd). Display pixel (12 _i,j ) according to any one of claims 1 to 10, wherein the display pixel (12 _i,j ) is intended to receive a second binary signal (Data _j ), and wherein the first capacitor (C1) is configured to be charged with the reference supply voltage (Vdd_Ref) from the first binary signal (Com _i ) and the second binary signal (Data _j ). Display pixel (12 _i,j ) according to claims 2 and 11, comprising at least one fourth electrically conductive bonding pad (P_Col), the second binary signal (Data _j ) being received on the fourth electrically conductive bonding pad (P_Col), the driver circuit (40) being configured to drive the light-emitting device (LED) from the first binary signal (Com _i ) received on the third electrically conductive bonding pad (P_Row) and the second binary signal (Data _j ) received on the fourth electrically conductive bonding pad (P_Col), the second binary signal (Data _j ) alternating between the second voltage and the third voltage (Gnd). A display pixel (12 _i,j ) according to claim 12, wherein the power supply circuit (60) comprises a third branch connecting the fourth electrically conductive bonding pad (P_Col) and the first capacitor (C1), the third branch comprising only one or more Schottky diodes, diodes and/or transistors. Display pixel (12 _i,j ) according to claims 4 and 11, wherein the second capacitor (C2) is also configured to be charged by the second binary signal (Data _j ). Display pixel (12 _i,j ) according to claims 12 and 14, wherein the power supply circuit (60) comprises a fourth branch connecting the fourth electrically conductive bonding pad (P_Col) and the second capacitor (C2), the fourth branch comprising only one or more Schottky diodes, diodes and/or transistors. Display pixel (12 _i,j ) according to any one of claims 11 to 15, wherein the driver circuit (40) is configured to determine a digital signal (R, G, B) from values of the second binary signal (Data _j ) received relative to the first pulses of the first binary signal (Com _i ) and to control the light emitting device (LED) on the basis of the digital signal. The display pixel (12 _i,j ) of claim 16, wherein the driver circuit (40) is configured to drive the light emitting device (LED) in pulse width modulation based on the digital signal (R, G, B). Display pixel (12 _i,j ) according to claim 17, wherein the driver circuit (40) is configured to turn off or on the light emitting device (LED) at the frequency of the second pulses of the first binary signal (Com _i ) at the second voltage (Vdd) or at the third voltage (Gnd). A display pixel (12 _i,j ) according to claim 12 or 13, comprising only the first, second, third and fourth electrically conductive bonding pads (36). A display pixel (12 _i,j ) according to any one of claims 11 to 19, wherein the first binary signal (Com _i ) is a first binary voltage and wherein the second binary signal (Data _j ) is a second binary voltage. A display pixel (12 _i,j ) according to any one of claims 1 to 20, wherein the voltage follower circuit (OAmp) comprises an operational amplifier (OAmp) having a non-inverting input (+), an inverting input (-), and an output, the non-inverting input (+) of the operational amplifier (OAmp) being connected to the first capacitor (C1), the output of the operational amplifier (OAmp) providing the supply voltage (Vdd), and the inverting input (-) of the operational amplifier (OAmp) being connected to the output of the operational amplifier (OAmp). A display screen (10) comprising a display pixel array (12 _i,j ) according to claim 12 or 13, the display screen further comprising circuitry (22, 24) for providing, for each display pixel, the first voltage (Vcc) between the first and second electrically conductive bonding pads (P_Vcc, P_Gnd), the first binary signal (Com _i ) on the third electrically conductive bonding pad (P_Row) and the second binary signal (Data _j ) on the fourth electrically conductive bonding pad (P_Col). A method of controlling a display screen (10) comprising a matrix of display pixels (12 _i,j ) according to claim 12 or 13, the method comprising providing, for each display pixel (12 _i,j ), the first voltage (Vcc) between the first and second electrically conductive connection pads (P_Vcc, P_Gnd), providing the first binary signal (Com _i ) on the third electrically conductive connection pad (P_Row) and providing the second binary signal (Data _j ) on the fourth electrically conductive connection pad (P_Col). A method according to claim 23, comprising providing the first binary signal (Com _i ) and the second binary signal (Data _j ) such that, in operation, the ratio of the average duration during which at least one of the first binary signal (Com _i ) and the second binary signal (Data _j ) is at the second voltage (Vdd) to the sum of the average duration during which the first binary signal (Com _i ) and the second binary signal (Data _j ) are at the third voltage (Gnd) and the average duration during which at least one of the first binary signal (Com _i ) and the second binary signal (Data _j ) is at the second voltage (Vdd) is greater than 75%. The method of claim 24, comprising providing the first binary signal (Com _i ) and the second binary signal (Data _j ) such that, at any time during operation, at least one of the first binary signal (Com _i ) and the second binary signal (Data _j ) is at the second voltage (Vdd). A method according to any one of claims 23 to 24, wherein the reference supply voltage (Vdd_Ref) is less than 10% lower than the second voltage (Gnd) and wherein the supply voltage (Vdd) is less than 10% lower than the second voltage (Gnd).