GB1262691A - Data processing system having current drive for transmission line - Google Patents
Data processing system having current drive for transmission lineInfo
- Publication number
- GB1262691A GB1262691A GB5316469A GB5316469A GB1262691A GB 1262691 A GB1262691 A GB 1262691A GB 5316469 A GB5316469 A GB 5316469A GB 5316469 A GB5316469 A GB 5316469A GB 1262691 A GB1262691 A GB 1262691A
- Authority
- GB
- United Kingdom
- Prior art keywords
- line
- current
- source
- transmitters
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
- H03K19/01825—Coupling arrangements, impedance matching circuits
- H03K19/01831—Coupling arrangements, impedance matching circuits with at least one differential stage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Mathematical Physics (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Dc Digital Transmission (AREA)
- Electronic Switches (AREA)
- Small-Scale Networks (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
1,262,691. Telegraphy. BURROUGHS CORP. 30 Oct., 1969 [12 Nov., 1968], No. 53164/69. Heading H4P. A high-speed transmission system includes a line connecting one or more receivers to one or more transmitters which have a digitally controlled current source of a high output impedance for applying current pulses to a line. It is stated that the system enables signals to approach the propagation time of the line more closely than systems employing voltage pulses. A line l1, Fig. 1, is terminated in impedances Zt and voltage sources Vte, Vtr and has a plurality of transmitters and receivers connected thereto which are synchronized by a pulse source 14. The period between pulses is equal to twice the propagation time of line. A current source I is connected to the line through a switch 18a controlled by a unit 20 synchronized with the source 14. An opening of switch 18a in unit lk causes current at terminal lk to drop which propagates along the line 12a towards terminal ri. At the same time switch 18a in unit ri is rendered conductive which applies a current pulse from the line, the two current pulses propagating towards each other causing a current change of twice that of one source. The current from terminal ri eventually reaches terminal lk and re-establishes the former level. A particular form of switch unit, Fig. 2, has an output transistor 22 of high output impedance and hence constant current characteristics connected to line 12a and controlled by transistor 24, 25 forming an AND gate, which receives input timing and control signals. An alternative form of transmitter giving negative signals is illustrated in Fig. 3 (not shown). The receiver 16 has an input transistor 82 normally non-conductive controlling differentially connected transistors 86, 88 connected to outputs through transistors 96, 98. On receipt of a negative current pulse transistors 82, 86 are biased conductively and 88 non-conductively hence transistor 96 will give a low output and 98 a high voltage output. It is essential that voltage swings on the line are not limited otherwise advantages of the system are lost. In a preferred arrangement only two transmitters are allowed to apply current to line 12a simultaneously. Multiple transmission lines with transmitters and receivers are envisaged by the Specification.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US77464568A | 1968-11-12 | 1968-11-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1262691A true GB1262691A (en) | 1972-02-02 |
Family
ID=25101838
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB5316469A Expired GB1262691A (en) | 1968-11-12 | 1969-10-30 | Data processing system having current drive for transmission line |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS5241604B1 (en) |
BE (1) | BE741528A (en) |
DE (1) | DE1956515C3 (en) |
FR (1) | FR2023120A1 (en) |
GB (1) | GB1262691A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1816570A2 (en) * | 1990-04-18 | 2007-08-08 | Rambus Inc. | Integrated circuit I/O using a high performance bus interface |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2074824B (en) * | 1980-04-04 | 1984-02-08 | Rolm Corp | High speed ribbon cable bus |
-
1969
- 1969-10-30 GB GB5316469A patent/GB1262691A/en not_active Expired
- 1969-11-10 BE BE741528D patent/BE741528A/xx not_active IP Right Cessation
- 1969-11-11 DE DE19691956515 patent/DE1956515C3/en not_active Expired
- 1969-11-12 FR FR6938816A patent/FR2023120A1/fr not_active Withdrawn
- 1969-11-12 JP JP9021869A patent/JPS5241604B1/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1816570A2 (en) * | 1990-04-18 | 2007-08-08 | Rambus Inc. | Integrated circuit I/O using a high performance bus interface |
EP1816570A3 (en) * | 1990-04-18 | 2007-08-15 | Rambus Inc. | Integrated circuit I/O using a high performance bus interface |
Also Published As
Publication number | Publication date |
---|---|
DE1956515C3 (en) | 1979-01-04 |
DE1956515A1 (en) | 1970-06-11 |
JPS5241604B1 (en) | 1977-10-19 |
BE741528A (en) | 1970-04-16 |
FR2023120A1 (en) | 1970-08-07 |
DE1956515B2 (en) | 1978-05-11 |
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