GB2103419A - Field effect transistor with metal source - Google Patents

Abstract

The metal source region 17 of a field effect transistor ohmically contacts the semiconductor region 13 within which the channel is induced in operation. A highly doped region may be diffused directly beneath the source electrode to improve the ohmic contact between source and semiconductor. The drain region 11, 12 forms a PN junction 14 with the region 13, and an insulated gate electrode 18, 19 overlies the surface of a V-groove and extends between the source electrode 17 and junction 14. In another embodiment an overall metal layer may be divided so that only part forms the gate electrode while the remainder forms the source electrode and extends, to form a field plate, over the outside edge of the mesa. In a further embodiment the metal source forms an ohmic contact with an underlying p-type diffused region in a flat n-type semiconductor body. A metal gate on an insulating layer overlies the channel region and the metal source. <IMAGE>

Description

SPECIFICATION Field effect transistor with metal source This invention relates generally to a field effect transistor and more particularly to a field effect transistor with a metal source and to methods of manufacturing the transistor.

In the manufacture of field effect transistors such as MOSFET and VMOSFET devices, a large number of masking and diffusion steps are required. The number of defects introduced during the manufacturing process increases with the number of steps.

Defects generally cause device failure and reduce yield, i.e. the number of acceptable devices formed on a wafer during the manufacturing process. This, of course, increases the cost of individual devices because a substantial portion of cost of devices are the semiconductor wafer in which the devices are formed.

Also, the number of steps increases the expense of processing by requiring additional equipment or longer use of the equipment and additional labor.

Diffusion requires expensive equipment. Thus, minimizing the number of diffusions will decrease the cost of the semiconductor devices.

Conventional VMOS devices include a source region forming a junction with the body which may act with the remaining regions to form a parasitictrans- istor. This introduces dvldt problems, safe operating problems and latching problems.

It is a general object of the present invention to provide a field effect transistor and method of manufacture which requires a minimum number of masking steps and in many embodiments no diffusion steps to manufacture the device thereby providing high yields and low labor and equipment costs.

It is another object of the present invention to provide a field effect transistor having a metal source which is also used as a mask during manufacture of the device.

It is another object of the present invention to provide a multiple cell (power) field effect transistor which accommodates mask defects.

The foregoing and other objects of the invention are achieved in a semiconductor device comprising a body of semiconductor material of one conductivity type with a drain forming at least a first rectifying junction with said body. A metal source in contact with said body on one side of and spaced from said junction. Said drain serving to collect carriers which flow through a channel induced in the body between the source and drain. An insulating layer over and between the source and junction covered by a gate electrode which induces an inversion layer or channel in the semiconductor body between said source and junction. The invention further relates to a method of making a field effect transistor which includes employing the metal source as a mask during manufacture of the field effect transistor.

The foregoing and other objects will be more clearly understood from the following description taken in connection with the accompanying drawings in which: Figure 1 is a perspective view partly in section of a field effecttransistorin accordance with one embodiment of the present invention.

Figures 2A-2N show the steps, in accordance with one embodiment of the invention, in forming the device of Figure 1.

Figure 3 is a sectional view of a field effect transistor in accordance with another embodiment of the present invention.

Figure 4 is a sectional view of a field effect transistor of the type shown in Figure 3 including a diffused region forming an improved source body contact.

Figure 5 is a sectional view of a field effect transistor such as shown in Figure 3 but having regions of opposite conductivity type.

Figures 6A-6F show another device and the steps in forming the device in accordance with another embodiment of the present invention.

Figure 7 is a sectional view of another device incorporating the present invention.

Figures 8A-D show the effect of defects in a multicell field effect transistor in accordance with the invention.

Figure 1 is a perspective view of a device in accordance with one embodiment of the invention. The device comprises a substrate 11 which in the illustrated embodiment is highly doped, p++ type, material. A lightly doped, p-, region 12 of the same conductivity type is on one surface of the substrate.

A lightly doped layer 13 of opposite conductivity type, n-, forms a junction 14 with the region 12. The body or substrate 11 serves to conduct carriers to the lower electrode 16. A metal source 17 is in intimate contact with the layer 13. The source 17 is a metal which provides an ohmic contact with the layer 13.

An insulating layer 18 overlies the entire upper such face of the device.

A conductive gate layer 19 is formed on the insulating layer to extend over the source 17 and the junction 14. The layer induces a conductive channel (inversion layer) in the n- region which ohmically connects the source metal 17 to the layer 12 when a gate voltage is applied. The device is protected against scratches and the like by protective layer 21.

A source electrode opening 22 is formed in the insulating material 21, gate 19 and insulating layer 18. This allows a conductive contact with the source 17. A gate opening 23 is formed in the insulating layer 21 to provide electrode connection to the gate layer 19. A drain contact 16 ohmically contacts the body 11.

The device operates by applying a voltage between the source and drain electrodes and controlling or gating the flow of carriers through the channel induced by varying the voltage on the gate 19 which forms a depletion channel in layer 13. It is to be noted that a channel is induced in the layer 13 at the groove as well as at the sloping sides. As will be clearly seen, the device differs from a conventional field effect transistor in that it only includes n- type and p- type regions of semiconductor material forming a single junction and a metal source. This is in contrast to the normal field effecttransistorwhich includes three regions and two junctions.

It is seen that the gate conductor extends on the sides of the mesa and forms a field plate which also functions to induce a channel. When the gate potential is at the same potention as the source it acts as a field plate. When it is brought negative, p- channel device, it acts as a MOS device with prescribed threshold and 1DS characteristics.

The field effect transistor overcomes various problems encountered with conventional field effect transistors. There is no emitter present to form a parasitic transistor. It has a much greater safe operating area. As will be presently described the number of processing steps is vastly reduced over conventional device fabrication.

Referring to Figures 2A-2N, and the following text the steps in forming the device shown in Figure 1 are illustrated and described. Referring to Figure 2A, the starting material is a silicon substrate 11. The silicon is oriented 100 and highly doped. The silicon wafer or substrate is designated p++. The doping material is preferably a slow diffusant. The dopant may be for example boron to a doping concentration of greater than 1#o. This heavy doping reduces the resistance of the device when it is turned on and aids in making an ohmic backside drain contact 16.

The next step in forming the device is to grow an epitaxial region 12, Figure 2B, on the upper surface of the substrate 11. The epitaxial region is grown with a low doping concentration to form a p- region. The region maye for example include boron as the dopantto a concentration of between 1014 and 1 a7. For devices where the resistance of the device is not of major importance, this layer may be eliminated by using a lightly doped substrate 11. For devices where the breakdown voltage is low, this layer is also unnecessary. Further, for very lightly doped epitaxial layers on very heavily doped substrate, there may be an intermediate layer of moderately heavier doping. These selections can be made by the designer knowing the operating characteristics of the device.Suffice it to say that in the device described, the substrate is highly doped with a lightly doped epitaxial layer. Next, a lightly doped layer 13 of opposite conductivity type, n-is grown by epitaxial growth or implanted or diffused into the expitaxial layer 12tofrom p-n junction 14, Figure 2C. The impurity concentration of doping in this layer determines the threshold and punch-through voltage and thus the minimum thickness to which the layer 13 must be grown. It is generally desirable to achieve the shortest channel iength-possible. In a grooved device, as shown, the channel length will be approximately 1.23 times the thickness of the layer.

The next step is to provideth source metal 17 in accordance with the present invention, Figure 2D.

The steps for forming the source are evaporating or otherwise forming metal layer 17 which adheres to the epitaxial layer 13 and forms an ohmic contact therewith. The metal is covered with photoresist layer 24, Figure 2E, which is processed to leave mask portions 26, Figure 2F, and then etched to remove the exposed metal and define the source electrodes 17 on the surface of layer 13, Figure 2G. This is the first masking step in the formation of the semiconductor device of Figure 1.

The next step is to subject the wafer to an etching solution which preferentially etches the silicon to form the flat bottomed V-groove and define the sides 27 of the mesa, Figure 2H. It is important to use an etch that will not attack the metal; therefore, organic etches are well suited for this purpose. The V-groove is etched deep enough to penetrate the p- epitaxial layer and is then stopped, Figure 2H. This step is followed by a washing step to remove the photoresist. A second metal etching step is then performed to round the source edges and provide the structure shown in Figure 21.

The next step in the process is to provide the gate oxide or insulator 18 as illustrated in Figure 2J. The gate insulator is deposited or grown at relatively low temperatures, below the eutectic point of the source metal and silicon. This insulator must be pin-hole free. Deposition can be preceded with an oxidation of the source metal if appropriate for good adhesion.

The next step is to provide the gate metal 19. This may be achieved by evaporating a metal layer over the entire surface as shown in Figure 2K. Another oxide or insulating layer 21 is then grown or deposited over the surface of the metal, Figure 2L. The surface is then masked and etched to form the gate electrode window 23, Figure 2M. Another masking and etching step forms a source window 22, Figure 2N.

The field effect transistor of Figure 3 is similar to that of Figures 1 and 2. However, after the first insulating layer 18 is deposited or grown it is masked and etched to provide a source contact window 31.

The metal gate layer 19 is then deposited on the surface masked and etched to define a gate 32 in the V-groove and a source contact and filed electrode 33.

A protective insulating layer 34 is then deposited or grown and windows 36 and 37 are formed to provide for connection of electrodes to the source and the gate. In fabrication the device requires three masking steps to form the source window 31, the sourcefield and gate metal and the windows 36 and 37.

When the n- region is lightly doped it may be desirable to provide an inset region of higher doping to make good ohmic contact between the source metal and semiconductor material. Figure 4 shows a device similar to that of Figure 3 with an inset region 38 of higher doping. This region may be formed by a diffusion step and thus requires an additional masking and diffusion step.

Referring to Figure 5, a device substantially identical to that of Figure 3 is illustrated. However, the device is of opposite conductivity type with the substrate or body being n- type and including a p- type epitaxial or diffused or implanted layer forming a junction therewith.

The present invention can also be used in a device of the type shown in Figure 6F. The device includes an n- type body 41 having a diffused p- type inset region 42 forming a junction 43. A metal source electrode 44 forms a contact with the underlying p- type region 42. An oxide layer 46 overlies the source electrode and extends over the region 47 in which the channel or inversion layer for the gated device is formed. The inversion layer in the region 47 is controlled by the gate electrode 48 formed in the oxide or insulating layer 46 to extend over the source electrode 44 and over the p-n junction 43 between the p- type and n- regions. Suitable contacts, not shown, are provided for source, drain and gate electrodes.

The device shown in Figure 6F may, for example, be formed by selecting an n- substrate 41, Figure 6A. Thereafter, the substrate is suitably masked with an insulating mask 49 and an inset p- diffusion region 42 is formed by known diffusion techniques, Figure 6B. The next step is to form an overlying metallic layer44 which makes ohmic contact with the ptype region and extends over the insulating layer 49, Figure 6C. Thereafter, by suitable masking and etching, the metal layer and underlying insulating layer is removed leaving the source contact 44, Figure 6D.

An insulating layer 46 is then grown or deposited at low temperature to overlie the surface of the device and the source. A metal gate layer 48 is formed on the insulation layer to overlie the channel region 47 and source metal 44.

Rather than a flat bottomed V-groove type device, by proper selection of the crystallographic orientation or etching technique, a U-channel can be formed during the etching operation. Such a U-channel device is shown in Figure 7. The reference numerals, corresponding to those of Figure 3.

Power field effect devices may include a number of cells. In conventional devices a defect in the photomask, or the photoresist process or contamination causes device failure. In the present invention defect or contamination does not cause device failure. This can be understood from Figures 8A-8D.

Figure 8A is a plan view of a two cell device including cells of the type described above. The numbered areas show possible defects or contamination. Figure 8B shows that defect 1 shorts the two gate areas and results in an increase in gate channel width. Figure 8C shows that defect 2 results in a reduction in gate channel width. Defect 3 results in an increase in gate channel width by adding a small gate in the field area, Figure 8D.

In each case the oxide will cover the defective area and each area will be covered by the gate. In each case the gate is etched to a prescribed depth (truncated V-grooves) to eliminate the possibility of wider V-grooves going deeper than the standard V-groove.

Thus, there has been provided a field effect transistor in which the source region is formed by a metal electrode which forms ohmic contact with the under- lying semiconductor material. A region of the semiconductor material is disposed between the barrier and an adjacent spaced rectifying junction. A gate electrode is carried over said region by an insulating layer and is adapted to provide an inversion layer to form a conducting channel or layer between the metal source electrode and the spaced junction.

Claims (12)

1. A field effect transistor device comprising a region of semiconductor material of one conductivity type, a region of opposite conductivity type forming a rectifying junction with said region, said junction extending to a surface of said region of one conductivity type, a source metal in contact with said region of opposite conductivity type spaced from said junction, a drain on the other side of said junction, an insulating layer extending between said source electrode and over said junction and a gate electrode carried by said insulating layer between said source electrode and over said junction adapted to induce a channel in said underlying region of opposite conductivity type.

2. A field effect transistor as in Claim 1 in which said region of opposite conductivity type comprises a layer forming a planarjunction with said region of one conductivity type, and groove extends through said region of oppositivity into said region of one conductivity type to form the surface to which said junction extends.

3. A field effect transistor as in Claim 1 in which said region of opposite conductivity type is an inset region and said junction extends to the upper surface.

4. Afield effecttransistorcomprising a drain region of semiconductor material of one conductivity type, a region of opposite conductivity type forming a planar junction with one surface of said drain region, a metal layer forming ohmic contact with said region of opposite conductivity type, a groove formed in said transistor and extending through said metal layer and said region of opposite conductivity type into said drain region to expose said junction, an insulating layer formed on said device to extend at least between said metal layer and said drain region and a gate electrode formed in said oxide layer and extending between said metal electrode and to said drain over said junction.

5. A field effect transistor as in Claim 4 in which said gate electrode is metal.

6. Afield effect transistor as in Claim Sin which said metal layer includes a gate portion and a field portion in ohmic contact with said source electrode and extending over said junction at the sides of the device.

7. The method of making a field effecttransistor comprising the steps of forming a rectifying junction which extends to a surface byforming a region of opposite conductivity type, forming a metal source in ohmic contact with said region of opposite conductivity type on one side of said junction spaced from said junction, forming a drain electrode on the other side of said junction, forming an insulating layer which extends over said source electrode and over said junction, forming a gate electrode comprising a conductive layer on said insulating layer to extend over said source electrode and said junction to induce an inversion channel between said source electrode and drain to provide a conductive path between said source and drain.

8. The method of Claim 7 in which said region of opposite conductivity type is formed by diffusion.

9. The method of claim 8 in which said region of opposite conductivity type is formed as an inset region.

10. The method of Claim 7 in which said region of opposite conductivity type forms a planar junction including the additional step of forming a groove which exposes said junction.

11. Afield effect transistor substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

12. A method of making a field effect transistor substantially as hereinbefore described with reference to the accompanying drawings.