GB2103420A - Gold-plated package for semiconductor devices - Google Patents

Gold-plated package for semiconductor devices Download PDF

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Publication number
GB2103420A
GB2103420A GB08217956A GB8217956A GB2103420A GB 2103420 A GB2103420 A GB 2103420A GB 08217956 A GB08217956 A GB 08217956A GB 8217956 A GB8217956 A GB 8217956A GB 2103420 A GB2103420 A GB 2103420A
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United Kingdom
Prior art keywords
package
gold
layer
area
rhodium
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Granted
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GB08217956A
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GB2103420B (en
Inventor
Shinichi Wakabayashi
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Publication of GB2103420A publication Critical patent/GB2103420A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/8506—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01—ELECTRIC ELEMENTS
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

A package for semiconductor devices, wherein at least part of the metal portion (3) of the package is plated with gold (2) and wherein a rhodium layer (1) is formed as an underplate for the gold layer. The metal portion is generally plated (5) with a metal such as nickel. The gold/rhodium combination is used as a package seal, a semiconductor mount, or a lead mount, to prevent unwanted diffusion and improve bonding. <IMAGE>

Description

SPECIFICATION Gold-plated package for semiconductor devices The present invention relates to gold-plated packages for semiconductor devices, which packages comprise metal portions, e.g., metal leads or metallized layers to be bonded with dies or wires or to be sealed with a metal lid.
Gold is widely used in the production of electronics devices because of its superior die-bonding, wire-bonding, and lid-sealing performance and its good heat and corrosion resistance. Silver is sometimes used in place of gold so as to reduce production costs, but the excellent performance of gold still makes it essential in electronics devices. To hold down costs, however, such gold that is used in the commercial production of semiconductor device packages is used as a thin plating only in restricted areas.
Now, in the production of packages for semiconductor devices, the bonding areas and a lid-sealing area on the substrate and also the outerlead areas of the lead frame are subjected to as high as 4000C to 4500C heat, e.g., when the die is bonded on the substrate. Such severe heating conditions tend to cause the thin gold layer to change in color due to the diffusion of underlying metal, e.g., nickel, iron, copper, through the gold and due to the oxidation of these metals.
In the case of a ceramic package, gold is usually plated on a nickel layer underplated on the metallized layer, so as to compensate for the uneveness and porosity of the metallized layer. However, the underplated nickel tends to oxidize due to oxygen entering through pinholes in the thin gold layer. This results in changes in color of the gold layers, uneven bonding of dies and wires, breaking-away of them from the substrate, and incomplete brazing of a metal lid.
To avoid such defects due to thermal treatment, the gold has had to be plated in a layer of at least 1.5 ijm thickness. With cer-dip type packages, the gold has had to be pasted in the die-bonding area in a layer of as much as 10 to 15 #m.
Attempts have been made to enable the reduction of the thickness of the gold layer by the joint use of metals cheaper than gold. Fred I. Novel et al, disclose a method of electrodeposited gold plating, in U.S Patent No. 3,963,455, wherein first a barrier layer, comprising an alloy of tungsten and cobalt or an alloy of tungsten and nickel, is electrodeposited on the base metal to a thickness of about 1 clam, then gold is electrodeposited on the barrier layer to a thickness of 1 to 1.27 ,am. However, a thickness of 1 ,am is still considered to be high for a gold layer.
T. Nagashima et al. assignee to Nihon Tokushu Togyo Co. Ltd. disclose gold plated electronics devices, in Japanese Patent Application Laid-Open No. 55-34692, wherein an alloy comprising nickel and cobalt is plated as an intermediate layer between gold and the base metal. The disclosure, however, is of a gold layer of 1.5 ym thickness plated on a 2 ,um layer of an alloy of nickel and cobalt. A 1.5 ,am thickness of gold is just the thickness usually applied directly on a nickel base.
While the above publications disclose the provision of an underplate for gold cheaper than gold, they do not disclose a sufficient reduction of the thickness of the gold layer. Further, no one has ever thought of producing a package for semiconductor devices by replacing part of a gold layer with a layer of metal costing nearly the same as gold in order to significantly reduce the total thickness of gold and the replaced metal.
It is an object of the present invention to provide a package for semiconductor devices, which has a gold-plated layer of minimum thickness but which does not suffer the diffusion of any underlying metal during production.
According to the present invention, a package for semiconductor devices has a metal portion, at least part of which portion is plated with gold, wherein a rhodium layer is formed as an underplate for the gold layer.
In order that the invention may be better understood, three embodiments of the invention are now described with reference to the accompanying drawings wherein: Figure 1 is a schematic sectional view of a multilayered ceramic type package; Figure 2 is a schematic sectional view of a ceramic type package; and Figure 3 is a schematic sectional view of a multilayered ceramic type package having a lighttransparent lid.
In each of these embodiments of the present invention, there is provided a package for semiconductor devices having a metal portion at least part of which portion is plated with gold, wherein a rhodium layer 1 is formed as a underplate for the gold layer 2.
It is convenient that said metal portion be a metallized layer 3 comprising tungsten, molybdenum, or a mixture of molybdenum and manganese or be a metallic lead 4 consisting of iron, or alloy of iron, and nickel or an alloy of iron, nickel, and cobalt. It is further convenient that said metallized layer 3 be plated with a metal 5, which may be nickel, copper, silver, gold, cobalt, or palladium.
The package shown in Figure 1 is a multilayered ceramic type wherein said rhodium layer 1 is formed in at least one of the die-bonding area D-B, the wire-bonding area W-B, and the lid-sealing area L-S on the substrate 6 of said package and the outerlead area O-L of the lead frame 4 of said package. A silicon die 7 is fixed on the gold layer 2 in the diebonding area D-B. The ends of an aluminum wire 12 are fixed on the gold layer 2 in the wire-bonding area W-B and on the die 7, respectively. The multilayered ceramic type package may comprise a dual-in-line type package, a leadless chip carrier, or a plug-in type package.
It is advisable that said package be a cer-dip type (Fig. 2) wherein said rhodium layer 1 is formed in at least one of the die-bonding area D-B on the substrate 6 of said package and the outerlead area O-L of the lead frame 4 of said package. The ends of the wire 12 are fixed on the die 7 and on an aluminum layer 13 deposited on the innerlead area ofthe lead frame 4, respectively.
Such bonding and sealing areas on the substrate and the outerlead area on the lead frame are subjected to as high as 4000C to 450 C heat, e.g., when the die 7 is fixed to the substrate 6 or when the metal lid 8 is brazed to the substrate 6 with an alloy 10 of gold and tin. A gold plating 2 having a rhodium underplate 1 according to the present invention can withstand such thermal treatment.
In the case of a multilayered ceramic package having a light-transparent lid 9 (Fig. 3), it is preferable that a rhodium layer 1 be formed in at least one of the die-bonding area D-B, the wire bonding area W-B on the substrate 6 of said package and the outerlead area O-L of the lead frame 4 of said package. Then, frit 11 can be fused beforehand on the ceramic substrate 6 without thermally affecting the bonding properties of the gold layer 2, and a light-transparent lid 9 can be sealed on the frit 11,so as to avoid previously fusing the frit 11 directly on the delicate optical lid 9. Thus, a glass cap for an image sensor can be produced without affecting its optical property.
When the metal lid has a transparent portion only in the center (not shown), of course, the metal lid may be brazed to the metallized layer plated with gold having a rhodium underplate according to the present invention, as shown in Fig. 1.
It is desirable that the thickness of said rhodium layer 1 be in the range of 0.1 to 1.0 clam. A 0.1 ,um thickness of rhodium can block the diffusion of the underlying metal. A rhodium layer of more than 1.0 ym is not desirable because rhodium itself is an expensive metal. A rhodium layer of 0.2 to 0.3 pm is preferable as the underplating metal for gold.
Thus, the thickness of the gold layer 2 can be reduced to about 0.5 jam, which is about one-third the conventional thickness where no rhodium layer is used. This thin gold layer is not damaged after a heating test of 4500C for 5 minutes.
In the multilayered ceramic type package of Figure 1, bonding areas D-B and W-B and sealing area S-L on the ceramic substrate 6 are metallised with tung sten 3 and rhodium 1 is plated on an underlying nic kel plating 5. However, the metallised layer3 may be molybdenum, tungsten, or a mixture of molyb denum and manganese and the underlying metal may be copper, silver, gold, cobalt, of palladium.
A sintered ceramic package of a 16 pin dual-in-line type was produced using a tungsten-matallized sub strate. A nickel layer 5 of 2.0 iim thickness was plated on the tungsten metallized layer 3 (Fig. 1). A rhodium layer 1 of 0.2 ,u m thickness was plated in a bath of "Rhodex" (available from Sel-Rex Ltd.), and a gold layer 2 of 0.5 > zm thickness was plated in a bath of "Temperex" 401 (avaiiable from Sel-Rex Ltd.).
Die-bonding was carried out by scribing a silicon die 7 on the gold layer 2 in the bonding area D-B in a nitrogen atmosphere at 430 C for 5 seconds. The obtained die-bonded package was subjected to a shear test, i.e., the silicon die 7 was peeled off by a knife edge and the bonding surface was visually examined. The opened bonding surface appeared to be wet with a eutectic crystal of gold and silicon, which occupied more than 90% of the binding sur face. Die-bonding did not deteriorate in the wetness of the eutectic crystal of gold and silicon or in the bonding strength, even after heating at 300"C for 30 hours.
A die-bonded package obtained as described above was heated at 3000C for 2 hours. Then, aluminum wires 12 of 30 ym diameter were fixed to the gold layer 2 in the wire-bonding area W-B by ultrasonic bonding. Bonding strength and wire breaking mode were investigated before and after thermal aging at 2000C for 50 hours. The wire bonding strength before and after the thermal aging are shown in Tables 1 and 2.
Table 1 Initial Wire-Bonding Strength (g) No. of No. of Sample pin t 2 3 4 5 6 7 8 9 10 13 7.3 7.5 5.1 8.5 5.0 5.8 5.6 6.5 5.7 6.7 14 6.0 7.6 7.5 5.9 9.8 8.9 7.6 7.8 9.4 6.6 15 4.6 6.7 8.0 7.1 4.0 5.1 8.3 6.5 7.1 6.1 16 7.2 7.0 6.1 8.2 7.3 5.5 8.0 7.8 7.0 6.9 1 6.3 7.3 6.2 4.0 7.4 5.8 10.0 6.5 5.7 6.1 2 6.3 8.3 4.7 6.1 8.4 7.2 8.1 6.2 6.5 6.8 3 8.4 6.4 6.0 8.7 8.8 6.9 8.4 5.5 4.0 6.8 4 8.3 5.9 6.1 4.9 8.3 7.6 6.8 5.6 4.0 6.9 mean 6.01 7.10 6.21 6.68 7.38 6.60 7.84 6.56 6.24 6.61 max 8.4 8.3 8.0 8.7 9.8 8.9 10.0 7.8 9.4 6.9 min 4.6 5.9 4.7 4.0 4.0 5.1 5.5 5.5 4.0 6.1 Table 2 Wire-Bonding Strength after thermal Aging (g) No. of No. of Sample pin t 2 3 4 5 6 7 8 9 10 5 5.2 5.2 4.8 5.6 4.1 6.1 5.6 5.7 5.3 5.7 6 4.8 5.5 3.6 5.7 6.2 5.8 5.8 4.7 5.4 5.6 7 2.1 4.6 6.8 6.0 6.2 2.8 5.6 5t1 3.2 5.7 8 5.0 2.0 6.3 2.7 5.9 4.5 3.8 5.6 2.1 6.4 9 5.0 3.3 6.4 5.1 4.8 2.7 4.8 6.2 5.4 6.5 10 4.1 5.2 4.0 4.1 4.9 5.6 5.5 5.2 5.8 5.5 11 6.1 6.5 6.6 4.8 6.4 5.0 4.9 5.7 5.2 5.7 12 6.0 6.1 4.5 5.9 4.2 3.8 5.4 4.5 6.3 3.4 mean 4.79 4.80 5.37 4.99 5.34 4.54 5.18 5.34 4.84 5.56 max 6.1 6.5 6.8 6.0 6.4 6.1 5.8 6.2 6.3 6.5 min 2.1 2.0 3.6 2.7 4.1 2.7 3.8 4.5 2.1 3.4 As can be seen from these tables, there is sufficient wire-bonding strength even after thermal aging.
Wire breaking appeared in the stem of the wires in most cases and in the neck of the wires only in a few cases. The bonded wire as a whole never peeled away from the gold plated area.
Thus, the reliability of bonding, using the present invention, is excellent.

Claims (11)

1. A package for semiconductor devices having a metal portion, at least part of which portion is plated with gold, wherein a rhodium layer is formed as an underplate for the gold layer.
2. A package according to claim 1, wherein said metal portion is a metallized layer comprising tungsten, molybdenum, or a mixture of molydbenum and manganese or is a metallic lead consisting of iron, an alloy of iron and nickel, or an alloy of iron, nickel, and cobalt.
3. A package according to claim 2, wherein said metallized layer is plated with nickel, copper, silver, gold, cobalt, or palladium.
4. A package according to claim 1, 2 or 3, wherein said package is a multilayered ceramic type having a structure such that said rhodium layer is formed in at least one of the die-bonding area, the wire-bonding area, and the lid-sealing area on the substrate of said package and the outerlead area of the lead frame of said package.
5. A package according to claim 1, 2 or 3, wherein said package is a cer-dip type having a structure such that said rhodium layer is formed in at least one of the die-bonding area on the substrate of said package and the outerlead area of the lead frame of said package.
6. A package according to claim 1, 2 or 3, wherein said package is a multilayered ceramic type having a structure such that the ceramic substrate is fritsealed with a light-transparent lid and that said rhodium layer is formed in at least one of the diebonding area, the wire-bonding area on the substrate of said package and the outerlead area of the lead frame of said package.
7. A package according to claim 1, 2 or 3, wherein said package is cer-dip type having a structure such that the ceramic substrate is frit-sealed with a lighttransparent lid and that said rhodium layer is formed in at least one of the die-bonding area on the substrate of said package and the outerlead area ofthe lead frame of said package.
8. A package according to any of claims 1 to 7, wherein the thickness of said rhodium layer is in the range of 0.1 to 1.0 pm.
9. A package according to claim 8, wherein the thickness of the rhodium layer is in the range 0.2 to 0.3 ,um.
10. A package according to claim 8 or 9, wherein the thickness of the gold plating is substantially 0.5 CLm
11. A package for semiconductor devices, a portion of which is gold-plated with an underplate of rhodium, substantially as described herein with reference to the accompanying drawings.
GB08217956A 1981-06-30 1982-06-21 Gold-plated package for semiconductor devices Expired GB2103420B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56102743A JPS584955A (en) 1981-06-30 1981-06-30 Package of gold-plated electronic parts

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GB2103420A true GB2103420A (en) 1983-02-16
GB2103420B GB2103420B (en) 1986-01-29

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EP0229850A1 (en) * 1985-07-16 1987-07-29 Nippon Telegraph and Telephone Corporation Connection terminals between substrates and method of producing the same
FR2610451A1 (en) * 1987-01-30 1988-08-05 Radiotechnique Compelec Opto-electronic device comprising at least one component mounted on a support
EP0278413A2 (en) * 1987-02-11 1988-08-17 Licentia Patent-Verwaltungs-GmbH Method for making a connection between a bonding wire and a contact pad in hybrid thick-film circuits
EP0562550A1 (en) * 1992-03-23 1993-09-29 Nec Corporation Chip carrier for optical device
FR2710783A1 (en) * 1993-09-29 1995-04-07 Mitsubishi Electric Corp Optical semiconductor device
FR2713401A1 (en) * 1993-09-29 1995-06-09 Mitsubishi Electric Corp Optical semiconductor device.
EP0660404A2 (en) * 1993-12-27 1995-06-28 Nec Corporation Element joining pad for semiconductor device mounting board

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EP0229850A1 (en) * 1985-07-16 1987-07-29 Nippon Telegraph and Telephone Corporation Connection terminals between substrates and method of producing the same
EP0229850A4 (en) * 1985-07-16 1987-10-08 Nippon Telegraph & Telephone Connection terminals between substrates and method of producing the same.
US4897918A (en) * 1985-07-16 1990-02-06 Nippon Telegraph And Telephone Method of manufacturing an interboard connection terminal
GB2181300A (en) * 1985-09-26 1987-04-15 Int Standard Electric Corp Semiconductor chip housing and method of manufacture
US4701573A (en) * 1985-09-26 1987-10-20 Itt Gallium Arsenide Technology Center Semiconductor chip housing
FR2610451A1 (en) * 1987-01-30 1988-08-05 Radiotechnique Compelec Opto-electronic device comprising at least one component mounted on a support
EP0278413A3 (en) * 1987-02-11 1989-03-29 Licentia Patent-Verwaltungs-GmbH Method for making a connection between a bonding wire and a contact pad in hybrid thick-film circuits
EP0278413A2 (en) * 1987-02-11 1988-08-17 Licentia Patent-Verwaltungs-GmbH Method for making a connection between a bonding wire and a contact pad in hybrid thick-film circuits
EP0562550A1 (en) * 1992-03-23 1993-09-29 Nec Corporation Chip carrier for optical device
FR2710783A1 (en) * 1993-09-29 1995-04-07 Mitsubishi Electric Corp Optical semiconductor device
FR2713401A1 (en) * 1993-09-29 1995-06-09 Mitsubishi Electric Corp Optical semiconductor device.
EP0660404A2 (en) * 1993-12-27 1995-06-28 Nec Corporation Element joining pad for semiconductor device mounting board
EP0660404A3 (en) * 1993-12-27 1996-03-27 Nec Corp Element joining pad for semiconductor device mounting board.

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Publication number Publication date
JPS584955A (en) 1983-01-12
GB2103420B (en) 1986-01-29
JPS6243343B2 (en) 1987-09-12

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