GB2431774A - Self-Biasing Transistor Structure and SRAM Cell - Google Patents

Self-Biasing Transistor Structure and SRAM Cell

Info

Publication number
GB2431774A
GB2431774A GB0702553A GB0702553A GB2431774A GB 2431774 A GB2431774 A GB 2431774A GB 0702553 A GB0702553 A GB 0702553A GB 0702553 A GB0702553 A GB 0702553A GB 2431774 A GB2431774 A GB 2431774A
Authority
GB
United Kingdom
Prior art keywords
self
sram cell
transistor structure
biasing transistor
biasing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0702553A
Other versions
GB2431774B (en
GB0702553D0 (en
Inventor
Friedrich Wirbeleit
Marianne Horstmann
Christian Hobert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE102004037087A external-priority patent/DE102004037087A1/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of GB0702553D0 publication Critical patent/GB0702553D0/en
Publication of GB2431774A publication Critical patent/GB2431774A/en
Application granted granted Critical
Publication of GB2431774B publication Critical patent/GB2431774B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H01L27/11—
    • H01L29/10—
    • H01L29/78—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/314—Channel regions of field-effect devices of FETs of IGFETs having vertical doping variations 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

By providing a self-biasing semiconductor switch, an SRAM cell (450) having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor (400) that allows the formation of an SRAM cell (450) with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.
GB0702553A 2004-07-30 2005-04-29 Self-biasing transistor structure and SRAM cell Active GB2431774B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102004037087A DE102004037087A1 (en) 2004-07-30 2004-07-30 Self-biasing transistor structure and SRAM cells with fewer than six transistors
US11/045,177 US7442971B2 (en) 2004-07-30 2005-01-28 Self-biasing transistor structure and an SRAM cell having less than six transistors
PCT/US2005/015294 WO2006022915A1 (en) 2004-07-30 2005-04-29 Self-biasing transistor structure and sram cell

Publications (3)

Publication Number Publication Date
GB0702553D0 GB0702553D0 (en) 2007-03-21
GB2431774A true GB2431774A (en) 2007-05-02
GB2431774B GB2431774B (en) 2009-04-01

Family

ID=34968873

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0702553A Active GB2431774B (en) 2004-07-30 2005-04-29 Self-biasing transistor structure and SRAM cell

Country Status (4)

Country Link
JP (1) JP2008508715A (en)
KR (1) KR101125825B1 (en)
GB (1) GB2431774B (en)
WO (1) WO2006022915A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008045037B4 (en) * 2008-08-29 2010-12-30 Advanced Micro Devices, Inc., Sunnyvale Static RAM cell structure and multiple contact scheme for connecting dual-channel transistors
FR2958779B1 (en) * 2010-04-07 2015-07-17 Centre Nat Rech Scient MEMORY POINT RAM HAS A TRANSISTOR

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4021835A (en) * 1974-01-25 1977-05-03 Hitachi, Ltd. Semiconductor device and a method for fabricating the same
US4145233A (en) * 1978-05-26 1979-03-20 Ncr Corporation Method for making narrow channel FET by masking and ion-implantation
US4276095A (en) * 1977-08-31 1981-06-30 International Business Machines Corporation Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations
US4350991A (en) * 1978-01-06 1982-09-21 International Business Machines Corp. Narrow channel length MOS field effect transistor with field protection region for reduced source-to-substrate capacitance
US4819043A (en) * 1985-11-29 1989-04-04 Hitachi, Ltd. MOSFET with reduced short channel effect
US5672536A (en) * 1995-06-21 1997-09-30 Micron Technology, Inc. Method of manufacturing a novel static memory cell having a tunnel diode
US6245607B1 (en) * 1998-12-28 2001-06-12 Industrial Technology Research Institute Buried channel quasi-unipolar transistor
US20030048657A1 (en) * 2001-08-28 2003-03-13 Leonard Forbes Four terminal memory cell, a two-transistor SRAM cell, a SRAM array, a computer system, a process for forming a SRAM cell, a process for turning a SRAM cell off, a process for writing a SRAM cell and a process for reading data from a SRAM cell

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6019152B2 (en) * 1977-08-31 1985-05-14 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン field effect transistor
US6282137B1 (en) * 1999-09-14 2001-08-28 Agere Systems Guardian Corp. SRAM method and apparatus

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4021835A (en) * 1974-01-25 1977-05-03 Hitachi, Ltd. Semiconductor device and a method for fabricating the same
US4276095A (en) * 1977-08-31 1981-06-30 International Business Machines Corporation Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations
US4350991A (en) * 1978-01-06 1982-09-21 International Business Machines Corp. Narrow channel length MOS field effect transistor with field protection region for reduced source-to-substrate capacitance
US4145233A (en) * 1978-05-26 1979-03-20 Ncr Corporation Method for making narrow channel FET by masking and ion-implantation
US4819043A (en) * 1985-11-29 1989-04-04 Hitachi, Ltd. MOSFET with reduced short channel effect
US5672536A (en) * 1995-06-21 1997-09-30 Micron Technology, Inc. Method of manufacturing a novel static memory cell having a tunnel diode
US6245607B1 (en) * 1998-12-28 2001-06-12 Industrial Technology Research Institute Buried channel quasi-unipolar transistor
US20030048657A1 (en) * 2001-08-28 2003-03-13 Leonard Forbes Four terminal memory cell, a two-transistor SRAM cell, a SRAM array, a computer system, a process for forming a SRAM cell, a process for turning a SRAM cell off, a process for writing a SRAM cell and a process for reading data from a SRAM cell

Also Published As

Publication number Publication date
KR101125825B1 (en) 2012-03-27
JP2008508715A (en) 2008-03-21
WO2006022915A1 (en) 2006-03-02
GB2431774B (en) 2009-04-01
KR20070046840A (en) 2007-05-03
GB0702553D0 (en) 2007-03-21

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