JP2509279B2 - Floating point number-fixed point number converter - Google Patents

Description

The present invention relates to a device for converting the format of a digital signal from floating-point number processing to fixed-point number processing, and converts an IEEE standard floating-point number into a fixed-point number by performing rounding processing and overflow processing. Therefore, in order to improve the calculation accuracy of the conversion, a two's complement signal of the IEEE standard floating point number is generated and stored in the accumulator in the first cycle, and the data in the accumulator is shifted in the second cycle. The barrel shifter circuit shifts only the number of shifts and the direction determined in step 3. If an overflow occurs during this shift, the clip is clipped by the clip part and stored again in the accumulator. In the third cycle, the barrel shifter circuit is carried in the second cycle. If it is detected, the carry bit is added to the data of the accumulator in the second cycle. Those There was configured to be stored in the appended with an accumulator as a final fixed point number.

[Industrial applications]

The present invention relates to a floating-point number-to-fixed-point number conversion device, and more particularly to a device for converting the format of a digital signal from floating-point number processing to fixed-point number processing.

Floating-point number processing is preferable to fixed-point number processing in terms of high precision of digital signal processing and wide dynamic range, but fixed-point number processing is often used in circuit control and the like. , It is necessary to convert the format from floating point number to fixed point number.

[Conventional technology]

The IEEE standard 32-bit floating point number has the representation format shown in FIG. 10, the exponent part e adopts a so-called “gettering” surface in which 127 is added to the true value, and the mantissa part f is from 1 to 2. The sign absolute value expression that expresses the number between is adopted. In the absolute value expression part f, the most significant bit (always 1 in the case of a normalized number)
The so-called "hidden" bit representation that omits is used.
Further, when the sign bit of the MSB is represented by S, the floating point number data X is represented by X = (− 1) ^s {2 ^e-127 } (1.f).

In this case, in the conventional floating-point number-to-fixed-point number conversion, the decimal point position of the fixed-point is at the least significant bit of the data, and the conversion is performed so as to substantially mean integer conversion.

[Problems to be Solved by the Invention]

Traditional floating-point-to-fixed-point number conversion is an IEEE standard
It did not deal with 32-bit floating point numbers, and the precision of bit conversion during the conversion was ignored, that is, it was truncated and rounding was not performed. Furthermore, overflow processing is not performed in the same manner, which may lead to a decrease in calculation accuracy.

Therefore, it is an object of the present invention to convert an IEEE standard floating point number into a fixed point number by performing rounding processing and overflow processing to improve the calculation accuracy.

[Means for solving the problem]

FIG. 1 is a conceptual diagram of a floating point number-fixed point number converter according to the present invention for achieving the above object.
In the figure, 1 is a conversion unit for converting the format of an IEEE standard floating point number stored in an accumulator 7 according to its sign bit, 2 is a 2's complemented signal by the output of the conversion unit 1 and the bit indicating the sign. An adder that generates 3 is a shift calculator that generates a shift number and a shift direction from an exponent part of the floating point number, 4 is a barrel shifter circuit that shifts the floating point number according to the shift number and the shift direction, and 5 is an adder. A selector for selecting the output of 2 or the output of the barrel shifter circuit 4, and 6 for clipping the output of the selector 5 only when the barrel shifter circuit 4 overflows.
And the clip section 8 gives a control signal to the conversion section 1 according to the sign bit of the floating point number in the first cycle and outputs the latched value of the shift calculation section 3 in the second cycle. The selector 5 is controlled to select the output of the adder 2 in the third cycle and the output of the barrel shifter circuit 4 in the second cycle, and when the barrel shifter circuit 4 detects a carry, the carry is detected in the third cycle. It is an arithmetic control unit that gives a rounding signal to the adder 2 based on the signal.

[Action]

The floating point number-fixed point number converter according to the present invention shown in FIG. 1 will be described below with reference to the bit state diagrams shown in FIGS. 2 to 4.

First, the IEEE standard floating-point number stored in the accumulator 7 as shown in FIG. 2 (1) or FIG. 3 (1) is sent to the conversion unit 1, and its exponent part is sent to the shift calculation unit 3. . Further, the sign bit of the floating point number is sent to the arithmetic control unit 8. In the arithmetic control unit 8, whether the input sign bit is "0" (positive decimal point number) or "1" (negative decimal point number)
Then, the control signal is sent to the conversion unit 1. The converter 1 converts the floating-point number into a format as shown in FIG. 4A or 4B by this control signal.
In this case, when the sign bit is "1", the mantissa part is also inverted as shown in FIG.

This format-converted floating point number is added by adder 2
In (2) and (3) in FIG. 2, a bit value represented in 2's complement representation is obtained by adding the values of the sign bits from the operation control unit 8, and the selector 5 Sent. The selector 5 is controlled by the arithmetic control unit 8 so that the output of the adder 2 is selected in the first cycle, and is stored in the accumulator 7 via the clip unit 6.

On the other hand, in the first cycle, the shift calculation unit 3 obtains the shift number and the shift direction from the exponent part of the floating point number of the accumulator 7 and latches them.

In the second cycle, the arithmetic control unit 8 outputs the number of shifts and the value in the shift direction latched by the shift calculation unit 3 to the barrel shifter circuit 4, and the barrel shifter circuit 4 outputs 1
At the second cycle, the bit values shown in FIG. 2 (2) or FIG. 3 (3) stored in the accumulator 7 are input as they are and shifted by the number of shifts in the designated shift direction. The shifted value is shown in FIG. 2 (3) or FIG. 3 (4). In the second cycle, the arithmetic control unit 8 controls the selector 5 to select the output of the barrel shifter circuit 4, so that this shifted value is sent to the clip unit 6. In the clip portion 6, in the above shift operation,
When the overflow is detected, the arithmetic control unit 8 controls the clipping unit 6 to clip the output of the selector 5 to the maximum positive or negative value and store it in the accumulator 7.

Then, in the third cycle, the adder 2 is generated by the signal when the barrel shifter circuit 4 detects the carry in the second cycle.
To the accumulator 7, the bit value of the second cycle output from the accumulator 7 passes through the conversion unit 1, the carry bit is added in the adder 2, and the final value is added to the accumulator 7 via the selector 5 and the clip unit 6. Will be stored as a fixed-point number.

〔Example〕

An embodiment of the floating point number-fixed point number conversion device according to the present invention will be described below.

FIG. 5 shows an embodiment of the floating point number-fixed point number converter according to the present invention.

In this embodiment, the conversion unit 1 is composed of selectors SEL1 to SEL3 to which the 32-bit signal from the accumulator ACC and the selection signals iNV and MASK signals from the operation control unit 8 are input, and one of the terminals of the selectors SEL1 and SEL2 is provided. Are provided with inverters 11 and 12, respectively. Shift calculator 3
Is an adder EA and an inversion unit iNVERT and an increment unit iNC that inverts and increments the addition result of the adder EA using the inverted signal of the carry signal EC of the adder EA as a control signal.
And a clip unit CLiP2 for clipping the output of the increment unit iNC, and a latch unit for latching the signal EC (a signal indicating the shift direction) and the output of the clip unit CLiP2 (a signal indicating the shift number) with a latch I and a latch II, respectively. LT
It consists of and. The barrel shifter circuit 4 includes a barrel shifter BS, a carry detection circuit CADET, and an overflow detection circuit OVDET. Further, the clip section 6 includes an AND gate G and a clip section CLiP1 controlled by this output.

Control signals iNV, MASK, CiN provided to these circuits,
LAEN, OPSE, and ACEN are signals output from the arithmetic control unit ACU that receives the arithmetic instruction, the most significant bit of the accumulator ACC (hereinafter referred to as bit AC31), and the output of the carry detection circuit CADET.

In the embodiment shown in FIG. 5, the adder 2, the selector 5, and the accumulator 7 shown in FIG.
It is described as D, the selector OPSEL, and the accumulator ACC.

 The operation of this embodiment will be described below.

First, an arithmetic instruction (floating point to fixed point conversion instruction) is input to the arithmetic control unit ACU, whereby the following arithmetic operation is started.

(1) First cycle Floating point data stored in the accumulator ACC composed of 32-bit registers as shown in FIG. 2 (1) or FIG. 3 (1) is the 8-bit adder EA, and Two
Input to alternative selectors SEL1, SEL2, SEL3.

The lower 23 bits (mantissa part) of the accumulator ACC are input to the selector SEL1, and when the select signal iNV from the arithmetic control unit ACU is “0”, it passes through, and when it is “1”, it is inverted. Output from selector SEL1. This select signal iNV is "1" when the most significant bit (MSB) (hereinafter referred to as bit AC31) of the accumulator ACC which is a sign bit is "0" in the first cycle, that is, when the number is a positive decimal point. When the bit AC31 is "0" and the bit AC31 is "1", that is, when the decimal point number is negative, the arithmetic control unit ACU outputs "1".

Further, the selector SEL2 receives the 24th bit from the lower order of the accumulator ACC, so-called "hidden bit" (hereinafter referred to as bit AC23), but the select signal MASK from the arithmetic control unit ACU is the first cycle. Is "1", an inverted signal of the select signal iNV is output.

That is, when the select signal iNV is "1" (negative number), "0" is output, and when the select signal iNV is "0" (positive number), "1" is output (Fig. 2 (2) or See FIG. 3 (2)).

For selector SEL3, 8 from the top of accumulator ACC
Although the bit is input, the select signal iNV is output as it is because the select signal MASK is "1" in the first cycle. That is, when the select signal iNV is "1" (when a negative number), the upper 8 bits are all "1", and when the select signal iNV is "0" (when a positive number), all "0" are output ((2) in FIG. 2). , FIG. 3 (2)).

The 32-bit format converted in this way is
Input to 32-bit adder ADD. Incidentally, the one-side input of the adder ADD is "0" at the time of the conversion instruction.

The carry-in signal CiN is bit A in the first cycle.
When the value of C31 is "1" (when it is a negative number), "1" is given to it, and when it is "0" (when it is a positive number), "0" is given to the adder ADD. 32-bit adder input LSB
Is added to. Therefore, the first cycle data is two's complemented as shown in FIG. 2 (2) or FIG. 3 (3).

After that, in the alternative selector OPSEL, the arithmetic control unit ACU
The select signal OPSE from is 0, and the adder AD
Select the output of D. The clip part CLiP1 is
Since OVCL is "0", the value of adder ADD is output as it is.

By the above-mentioned operation, the 2's complemented data is stored in the accumulator ACC. The signal ACEN is an enable signal for each cycle from the arithmetic and control unit ACU, and the signal CLK is a clock.

On the other hand, the accumulator ACC bit AC3
Since 8 bits (exponent part) are input from the upper bits except 1 to calculate the shift number, add 88 _(HEX) . Since this is calculated using an adder, when the exponent is 78 _(HEX) in the 8-bit shift conversion from the floating point position to the fixed point position in Figs. 2 and 3, the shift number is "zero". This is because -78 _(HEX) is a value obtained by complementing two, that is, 88 _(HEX) is added. Since the added value is a two's complement expression, it is necessary to convert the data into an absolute value thereafter. Therefore, the inverted signal of the carry signal EC in the 8-bit addition in the adder EA becomes a sign bit, and when the signal EC is "0", it is inverted and becomes "1", indicating a negative number. iNVERT inverts the output of the adder EA, and the increment unit iNC increments (adds 1). When the signal EC is "1", it is a positive number, and the inverter iNVERT and increment unit iNC
Is output as is. In this way, it is converted into an absolute value.

In addition, since the shift number is up to 31 bits, the shift number signal is sufficient to be 5 bits, and the number more than that needs to be clipped to the maximum shift number value. If the bit has "1", set the maximum value to IF _(HEX) in the clip part CLiP2. Otherwise,
5 bits are directly latched in the latch unit LT without clipping.

Further, in order to control the shift direction (right shift or left shift), the value of the carry signal EC is latched by the latch unit LT, and when the signal EC is “0”, it is inverted and becomes a negative number which becomes “1”. As shown, shift to the right, and conversely, if "1", shift to the left.
That is, in the case of FIG. 2 or 3, (70 + 88) _(HEX) = F8
_The carry signal EC becomes "0" at _(HEX) .

LAEN is a latch enable signal for the first cycle from the arithmetic control unit ACU.

(2) Second cycle Data is shifted from the result obtained in the first cycle.

First, the 32-bit data represented by 2's complement stored in the accumulator ACC is input to the selectors SEL1, SEL2.

In the second cycle, the select signals iNV and MASK are set to "0" by the arithmetic control unit ACU, and the selectors SEL1 and
Both 2 and 3 output the value of the accumulator ACC as it is. Then, the data is input to the barrel shifter BS, and the 5-bit data latched in the latch I of the latch unit LT shifts the data. Only the least significant bit (hereinafter referred to as bit LA0) of the output data of latch I is "1"
In this case, 1 bit is used, and when only bit LA1 is "1", 2 bits are used. In the following, a maximum of 31 bits can be shifted by combining 5 bits.

Also, the output LR of the latch II is a barrel shifter when it is "1".
This signal is latched in the first cycle in order to shift BS to the left and shift it to the right when it is "0". In addition, the carry detection unit CA
Detected by DET, output as signal C _OUT and calculation control unit ACU
To a register (not shown). Further, the overflow detection unit OVDET detects an overflow that occurs during left shift.

The shifted result is output from the barrel shifter BS and input to the selector OPSEL. In the second cycle, the select signal OPSE becomes "1", and the selector OPSEL selects and outputs the output of the barrel shifter BS.

After that, if there is an overflow due to a left shift during the shift, the clipping unit CLiP1 clips the data to the maximum positive value or the maximum negative value.

When no overflow occurs, the output OVCL of the AND gate G becomes "0", and the output of the selector OPSEL is output as it is.

After that, it is stored in the accumulator ACC (see FIG. 2 (3) or FIG. 3 (4)).

(3) Third Cycle In the third cycle, the signal C _OUT obtained by the carry detection unit CADET is added to the data of the accumulator ACC obtained by the shift operation of the second cycle by the adder ADD.

That is, first, the shifted data stored in the accumulator ACC is input to the selectors SEL1, SEL2.
Then, the select signals iNV and MASK are set to "0", and the values of the accumulator ACC are output as they are to the selectors SEL1, SEL2.

 The data is input to the adder ADD.

The carry-in signal CiN is a signal obtained by directly outputting the value of the signal C _OUT stored in the register of the arithmetic control unit ACU as a rounding signal and input to the adder ADD.

Then, it is added to the shifted data and rounded (see FIG. 2 (4) or FIG. 3 (5)).

In the second cycle, if the shift is to the left, the signal CiN
Becomes "0". This is because there is no precision loss bit.

After that, the select signal OPSE is set to "0", and the selector OPSE
Select the output of the adder ADD with L, and clip part CLiP1
Also, since the signal OVCL is "0", the input signal is output as it is, the final result is stored in the accumulator ACC, and the conversion ends (see FIG. 2 (4) or FIG. 3 (5)).

FIG. 7 shows a time chart of input / output signals of the arithmetic control unit ACU.

The operation of the barrel shifter circuit 4 is already known, but will now be briefly described with reference to FIGS. 8 and 9.

First, when performing an arithmetic left shift, the MSB (sign bit) is left unshifted and shifted, the logical sum of the lost bits is detected by the overflow detection circuit OVDET in FIG. 5, and the sign of the MSB is added to the lost bits. If there is a mismatch, the clip portion CLiP clips the positive or negative maximum value.

For example, based on -17 of the two's complement representation shown in FIG. 8 (a), a left shift of 1 bit results in a doubled value of -34 as shown in FIG. 8 (b), and a left shift of 2 bits results in the same figure. (C)
As shown in (4), the value must be -68, which is a quadruple value, and it must be -136 when left-shifted by 3 bits, but it overflows beyond the negative maximum value of -128. In this case, (d) in the figure.
It becomes -8 as shown in.

The detection of this overflow is detected by the disagreement of the logical sum or the logical product of the sign bit (MSB) and the erasure bit, and is clipped to the maximum positive or negative value.

When arithmetically shifting to the right, MSB is inserted after shifting by -bit of -66 of 2's complement representation shown in (1) (a) of FIG. As shown, the intermediate result is -3.

At this time, the guard bit becomes 1 as shown in (1) and (c) of the same figure, and the sticky bit becomes 1 of the logical sum of the values shown in (d) of the figure. These are performed in the carry detection circuit CADET.

Here, if -66 is right-shifted by 5 bits, -66 x 2 ^-5
= -2.0625, and rounding the value after the decimal point gives -2 or -3.

In this case, rounding of the precision loss bit is performed by adding the value of R shown below to the intermediate result, the latest value obtained, the plus direction,
Four methods of setting the minus direction and the zero direction are defined by the IEEE standard.

R = × + × R = + R = 0 R = [+] × S where LSB is a guard bit, is a sticky bit, S is a sign bit (MSB), + is a logical sum, and x is a logical product.

When the values of R are added respectively, as shown in FIG. 9 (2), the nearest value rounding and the plus rounding become -2, the minus rounding become -3, and the zero rounding becomes -2. Therefore, in the case of -2, carry detection circuit CADET
"1" is output from the output terminal, and when it is set to -3, "0" is output and the above rounding operation is performed by the adder ADD.

〔The invention's effect〕

As described above, according to the floating point number-fixed point number conversion device of the present invention, the two's complement signal of the IEEE standard floating point number is generated in the first cycle, stored in the accumulator, and stored in the accumulator in the second cycle. The data of the accumulator is shifted by the barrel shifter circuit by the number of shifts and the direction obtained by the shift calculator, and when an overflow occurs during this shift, it is clipped by the clip unit and stored again in the accumulator, and in the third cycle, When the barrel shifter circuit detects a carry in the second cycle, the carry bit is added to the data of the accumulator in the second cycle and the final fixed-point number is stored in the accumulator. Floating point numbers can be converted to fixed point numbers, including overflow and rounding. It is possible to improve the accuracy.

[Brief description of drawings]

FIG. 1 is a diagram conceptually showing a floating-point-to-fixed-point number conversion apparatus according to the present invention, and FIGS. 2 and 3 explain the operation of the floating-point-to-fixed-point number conversion apparatus according to the present invention. 4 is a state transition diagram for performing the conversion, FIG. 4 is a format conversion diagram in the conversion unit used in the floating point number-fixed point number conversion device according to the present invention, and FIG. 5 is a floating point number-fixed point number conversion according to the present invention. FIG. 6 is a circuit diagram showing an embodiment of the device, FIG. 6 is a diagram showing input / output signals of an arithmetic control unit used in the floating point number-fixed point number conversion device according to the present invention, and FIG. 7 is a floating point number according to the present invention. A time chart diagram of an embodiment of the number-fixed point number converter, FIGS. 8 and 9 are diagrams for explaining the operation of the barrel shifter circuit used in the floating point number-fixed point number converter according to the present invention, Figure 10 shows IEEE floating point numbers It is the figure which showed the expression. In FIG. 1, 1 ... conversion unit, 2 ... adder, 3 ...
Shift calculation unit, 4 ... Barrel shifter circuit, 5 ... Selector, 6 ... Clip unit, 7 ... Accumulator, 8 ...
Arithmetic control unit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. An accumulator (7) for storing an IEEE standard floating point number, a converter (1) for converting the format of the floating point number according to its sign bit, and an output of the converter (1). An adder (2) for generating a two's complement signal by a bit indicating the sign, a shift calculator (3) for generating and latching a shift number and a shift direction from the exponent part of the floating point number, and the shift A barrel shifter circuit (4) for shifting the floating point number according to a number and a shift direction, a selector (5) for selecting the output of the adder (2) or the output of the barrel shifter circuit (4), and the barrel shifter circuit ( 4) according to the clip part (6) which clips the output of the selector (5) and gives it to the accumulator (7) only when it overflows, and the sign bit of the floating point number in the first cycle. A control signal is given to the conversion unit (1), the latched value of the shift calculation unit (3) is output in the second cycle, and the output of the adder (2) is output in the first cycle and the third cycle. In the second cycle, when the barrel shifter circuit (4) controls the selector (5) so as to select the output of the barrel shifter circuit (4), the third cycle detects the carry signal. A floating point number-fixed point number conversion device comprising: an arithmetic control unit (8) for giving a rounding signal to an adder (2).