JP2533953B2 - Active matrix substrate - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an active matrix substrate used for a display device using liquid crystal or the like, and more particularly to an active matrix substrate having an additional capacitance.

(Prior Art) Conventionally, in a liquid crystal display device, an EL display device, a plasma display device, and the like, pixel electrodes arranged in a matrix are selectively driven to form a display pattern on a screen.
A voltage is applied between the selected pixel electrode and a counter electrode facing the pixel electrode, and the display medium interposed therebetween is optically modulated. This optical modulation is visually recognized as a display pattern. As a driving method of the picture element electrodes, an active matrix driving method is known in which individual picture element electrodes are arranged and a non-linear element is connected to each of the picture element electrodes for driving. As a non-linear element for selectively driving the pixel electrode, a TFT (thin film transistor) element, a MIM (metal-insulating layer-metal) element, a MOS transistor element, a diode, a varistor, etc. are generally known.

In an active matrix substrate using a TFT as a non-linear element, a gate bus line that functions as a scanning line and a source bus line that functions as a signal line are provided to drive the TFT. A gate-on signal is applied to the gate bus line, and a video signal is applied to the pixel electrode from the source bus line through the TFT. Further, in order to hold the video signal applied to the pixel electrode for one cycle until the next video signal is applied, an additional capacitance electrode is often provided facing the pixel electrode. Each additional capacitance electrode is connected to the additional capacitance wiring, and each additional capacitance wiring is connected to the additional capacitance common wiring.

5 and 6 schematically show a conventional active matrix substrate using a TFT as a non-linear element, in which a gate bus line and an additional capacitance line are provided.
In the substrate of FIG. 5, the gate bus lines 1 are provided in parallel, and the additional capacitance lines 2 are provided in parallel between the gate bus lines 1. The portion of the additional capacitance line 2 that faces the pixel electrode (not shown) functions as an additional capacitance electrode. The gate bus wiring 1 is drawn out in one of the extending directions, and the connection terminals 11 are provided at the ends of the drawn lines. The additional capacitance wiring 2 is drawn out to the side opposite to the gate bus wiring 1 and is electrically connected to the additional capacitance common wiring 3.

In the active matrix substrate of FIG. 6, the gate bus wiring 1 is composed of a gate bus wiring 1a extending in one direction of the extending direction and a gate bus wiring 1b extending in the other direction. Similarly, the additional capacitance line 2 includes an additional capacitance line 2a extending in one of the extending directions and an additional capacitance line 2b extending in the other direction. The portions of the additional capacitance wirings 2a and 2b facing the picture element electrodes (not shown) function as additional capacitance electrodes. The gate bus lines 1a and 1b are provided with connection terminals 11a and 11b at their ends on the pull-out side. Similarly, additional capacitance wiring
2a and 2b are provided with additional capacitance terminals 12a and 12b at their respective ends in the drawing direction. Therefore, in the substrate of FIG. 6, unlike the substrate of FIG. 5, the gate bus wiring 1 and the additional capacitance wiring 2 are drawn out from both sides of the substrate. Although omitted in FIGS. 5 and 6, source bus lines and the like are further formed on these substrates.

(Problems to be Solved by the Invention) When the active matrix substrate provided with the additional capacitance is used in the display device as described above, the additional capacitance wiring is made of a metal film, so that the aperture ratio of the display device is reduced. In order to reduce the decrease in aperture ratio, the additional capacitance wiring must be formed as thin as possible. When the additional capacitance wiring is thin, a signal is likely to be delayed on the additional capacitance wiring corresponding to the video signal applied to the pixel electrode. Due to this signal delay, when a display device is assembled using this substrate, the image quality of the display device is degraded. Further, if the additional capacitance wiring becomes thin, disconnection failure is likely to occur in the additional capacitance wiring when forming the pattern of the additional capacitance wiring. When the disconnection failure of the additional capacitance wiring occurs, the image signal applied to the picture element electrode is not sufficiently retained, and the image quality of the display device deteriorates.

Further, in order to ensure insulation between the additional capacitance wiring and the pixel electrode, an anodic oxide film obtained by anodizing the upper surface of the additional capacitance wiring is often provided on the additional capacitance wiring.
When the disconnection of the additional capacitance wiring occurs as described above, the anodic oxide film is not formed in the portion of the additional capacitance wiring beyond the disconnection portion. In the portion of the additional capacitance wiring where the anodic oxide film is not formed, insulation failure is likely to occur with the pixel electrode. Such insulation failure also deteriorates the image quality of the display device and is not preferable.

Furthermore, in an active matrix substrate used for a display device that performs high-definition display, the number of gate bus wirings and additional capacitance wirings is enormous, and the spacing between terminals provided at the ends of the gate bus wirings and additional capacitance wirings is extremely large. Get smaller. Therefore, when these terminals on the substrate and the terminals on the film carrier are connected, a leak current easily occurs between the terminals other than the terminals to be connected.

The present invention solves the above-mentioned problems, and an object of the present invention is to provide an active matrix substrate in which signal delay on the additional capacitance wiring does not occur. Another object of the present invention is to provide an active matrix substrate which does not deteriorate the image quality when used in a display device even if a disconnection defect occurs in the additional capacitance wiring. Still another object of the present invention is to provide an active matrix substrate in which leak current does not occur between terminals other than terminals to be connected on the film carrier.

(Means for Solving the Problems) An active matrix substrate of the present invention is an insulating substrate, scanning lines parallel to the insulating substrate, and additional capacitances formed in parallel between the scanning lines. Wiring, the scanning line having a connection terminal provided on one side in the extending direction of the scanning line, and the scanning line having a connection terminal provided on the other side are provided alternately. Each of the additional capacitance wirings adjacent to each other is electrically connected to each other on the side opposite to the connection terminal of the scanning line between the adjacent additional capacitance wirings, and a lead line drawn from the connected portion. And an additional capacitance terminal provided at the end of the lead wire, thereby achieving the above object.

Further, an additional capacitance common wiring that intersects the scanning line and the additional capacitance wiring and is electrically connected to each of the additional capacitance wiring is formed, and the additional capacitance common wiring and the scanning line are interposed by an insulating film. It is also possible to have a configuration in which they intersect.

Further, the additional capacitance terminal may be covered with an insulating film.

It is also possible to adopt a configuration in which an anodic oxide film is formed on the additional capacitance wiring.

(Operation) In the active matrix substrate of the present invention, since the adjacent additional capacitance lines are electrically connected to each other and the lead lines are provided from the connection portions at both ends of each additional capacitance line, No signal delay occurs. Further, even if a disconnection defect occurs at one place on the additional capacitance wiring, the additional capacitance wiring can function normally. Further, even if a disconnection defect occurs at one place on the additional capacitance wiring during the anodic oxidation, there is no portion where the anodic oxide film is not formed on the additional capacitance wiring. Therefore, in the display device using this active matrix substrate, the image quality does not deteriorate.

Further, in the active matrix substrate of the present invention, the additional capacitance common line connected to the additional capacitance line is provided. The signal supplied to the additional capacitance wiring corresponding to the video signal applied to the pixel electrode may be supplied by the additional capacitance common wiring. Further, an insulating film may be formed on the additional capacitance terminal provided at the end of the lead-out line of the additional capacitance wiring. With this configuration, no leak current is generated between the terminal on the film carrier corresponding to the connection terminal provided at the end of the gate bus wiring and the additional capacitance terminal.

(Examples) The present invention will be described below with reference to Examples. FIG. 1 shows a schematic diagram of an active matrix substrate of the present invention.
In FIG. 1, gate bus lines 1a and 1b, additional capacitance line 2,
Also, only the additional capacitance common wirings 3a and 3b are shown, and the description of the pixel electrodes, source bus wirings, etc. is omitted. In the active matrix substrate of the present embodiment, the gate bus wirings 1a and 1b are provided in parallel, the leader line 21a extends from one end of the gate bus wiring 1a, and the end portion thereof has a connection wider than the leader line 21a. A terminal 11a is provided. Similarly,
A lead wire 21b extends from one end of the gate bus wire 1b, and a connection terminal 11b having a width larger than that of the lead wire 21b is provided at the end of the lead wire 21b. The lead lines 21a and 21b are drawn from opposite sides.

The additional capacitance line 2 is formed between the gate bus lines 1a and 1b. The additional capacitance lines 2 adjacent to each other are connected on the side where the lead lines 21a and 21b of the gate bus lines 1a and 1b located between them are not provided. The lead lines 22a and 22b are led out from the connection portion, and the additional capacitance terminals 12a and 12b having a width larger than the lead lines 22a and 22b are provided at the ends thereof. Lead wire 22a
The additional capacitance terminal 12a is provided on the same side as the side where the lead wire 21a and the connection terminal 11a of the gate bus line 1a are provided. Similarly, the lead wire 22b and the additional capacitance terminal 12b are connected to the lead wire 21b and the connection terminal of the gate bus wiring 1b.
It is provided on the same side as the side on which 11b is provided. Orthogonal to the gate bus lines 1a and 1b and the additional capacitance line 2,
Additional capacitance common wirings 3a and 3b are formed. The additional capacitance common wirings 3a and 3b are electrically connected to the respective additional capacitance wirings 2. Further, the additional capacitance common wirings 3a and 3b intersect with the gate bus wirings 1a and 1b with the Ta ₂ O ₅ , SiN _x film, a-Si semiconductor layer, SiN _x film and n ⁺ type a-Si film described later interposed therebetween. are doing.

2 to 4 show a manufacturing process of the active matrix substrate of FIG. A Ta metal film was formed on the entire surface of the glass substrate by sputtering. This Ta metal film is subjected to photolithography and etching by the gate bus lines 1a and 1b, the additional capacitance line 2 and the lead lines 21a and 2 having the shapes shown in FIG.
1b, 22a, 22b, connection terminals 11a, 11b, and terminals for additional capacitance
12a and 12b were patterned. Next, the connection terminals 11a, 11
Anodization was performed using b and the additional capacitance terminals 12a and 12b. By this anodic oxidation, the gate bus wiring 1a in the area A of FIG. 2 is formed on the gate bus wirings 1a and 1b, the additional capacitance wiring 2, and the additional capacitance common wirings 3a and 3b are formed. , 1b on which an anodic oxide film was formed. Since the two additional capacitance terminals 12a and 12b are connected to each additional capacitance line 2, even if one disconnection occurs on the additional capacitance line 2, an anodic oxide film is formed on the additional capacitance line 2. The part which is not done does not occur.

Next, in order to form a TFT (not shown) which is a non-linear element, a SiN _X film and amorphous Si (hereinafter referred to as “a-Si”) are formed.
A semiconductor layer), and a SiN _x film are continuously deposited on the entire surface of this substrate. The uppermost SiN _X film was patterned, and an etching stopper was formed on the upper surface of the portion that will be the semiconductor layer of the TFT. Next, an n ^{+ -type} a-Si film is deposited on the entire surface of this substrate, and the a-Si semiconductor layer and the n ⁺ -type a-Si film described above are deposited.
The Si film was patterned to form a TFT semiconductor layer and a contact layer. Further, the contact layer is later divided into two parts below the source electrode and the drain electrode of the TFT.

Next, on the intersection with the additional capacitance common wirings 3a and 3b formed together with the additional capacitance wiring 2, and the gate bus wiring 1a.
The SiN _X films on the connection terminals 11a and 11b connected to the terminals 1 and 1b were removed. Next, a Ti metal layer is formed on the entire surface by sputtering, and the additional capacitor common wirings 3a and 3 and the source bus wiring 4 are formed.
Patterns a and 4b were formed (Fig. 3). Additional capacity common line 3
The a and 3b are formed by being electrically connected to the respective additional capacitance wirings 2. Next, an ITO film is formed on the entire surface of this substrate,
Patterning was performed to form a pixel electrode (not shown). Next, a SiN _x film to be the protective film 5 was formed on the entire surface of this substrate. Connection terminals connected to gate bus wiring 1a and 1b
The protective film formed on the portions 11a and 11b, the end portions of the source bus wirings 4a and 4b, and the end portions of the additional capacitance common wirings 3a and 3b is removed, and the active matrix substrate shown in FIG. Got

In the active matrix substrate of this embodiment, the signals corresponding to the video signals applied to the pixel electrodes are supplied from both ends of the additional capacitance wiring 2 through the additional capacitance common wirings 3a and 3b. The signal delay above is reduced. Further, even if a disconnection defect occurs at one place on the additional capacitance wiring 2, the additional capacitance wiring 2 can function normally. Further, since the protective film is formed on the additional capacitance terminals 12a and 12b, the connection terminals connected to the gate bus wirings 1a and 1b.
When connecting the terminals 11a and 11b to the terminals on the film carrier, the additional capacitance terminals 12a and 12b do not come into contact with the terminals on the film carrier.

(Effects of the Invention) In the active matrix substrate of the present invention, the signal delay on the additional capacitance wiring is reduced, so that if this substrate is used for a display device, a display device having high image quality can be obtained. Further, even if a disconnection occurs in the additional capacitance wiring, it can function normally, so that the yield of the display device is improved. Furthermore, the connection between the connection terminal of the gate bus wiring and the terminal on the film carrier becomes easy, which also improves the yield of the display device.

[Brief description of drawings]

FIG. 1 is a schematic plan view of an active matrix substrate of the present invention, FIGS. 2 to 4 are diagrams showing manufacturing steps of the active matrix substrate of FIG. 1, and FIGS. 5 and 6 are conventional active matrix substrates. FIG. 1a, 1b …… Gate bus wiring, 2 …… Additional capacitance wiring, 3a, 3b
...... Additional capacitance common wiring, 4a, 4b ...... Source bus wiring, 5
...... Protective film, 11a, 11b ...... Connection terminal, 12a, 12b …… Additional capacitance terminal, 21a, 21b, 22a, 22b …… Lead wire.

Claims (4)

(57) [Claims] 1. An insulating substrate, a scanning line parallel to the insulating substrate, and an additional capacitance line formed in parallel between the scanning lines, the extension of the scanning line. The scanning lines having contact terminals provided on one side in the installation direction and the scanning lines having connection terminals provided on the other side are alternately provided, and each of the additional capacitance lines adjacent to each other is Lead lines that are electrically connected to each other on the side opposite to the connection terminals of the scanning lines between adjacent additional capacitance lines and that are provided at the ends of the lead lines and the lead lines. An active matrix substrate having a terminal for additional capacitance. 2. An additional capacitance common line that intersects with the scanning line and the additional capacitance line and is electrically connected to each of the additional capacitance lines is formed, and the additional capacitance common line is insulated from the scanning line. The active matrix substrate according to claim 1, wherein the active matrix substrates intersect with each other through a film. 3. The active matrix substrate according to claim 2, wherein the additional capacitance terminal is covered with an insulating film. 4. The active matrix substrate according to claim 1, wherein an anodic oxide film is formed on the additional capacitance wiring.