JP2561810B2 - Hardware-assisted pixel reformatting during bit boundary block transfers - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to the conversion of pixels from one color format to another, and more particularly to hardware-assisted pixel reformatting during bit boundary transfers. Regarding the method.

[0002]

The image displayed on the monitor of a personal computer or workstation is usually stored in system memory as a bitmap file, in which the pixel colors are a plurality of pixel colors of a particular format. Represented by bits. For example, in the case of 16-bit RGB format, the color of each pixel is represented by 16-bit pixel data, the least significant 5 bits of which represent the luminance of the blue color component, and the next 5 bits are the red color component. , And the remaining 6 bits represent the brightness of the green color component. Also, in the 24-bit BGR format, the pixel color is represented by a 24-bit word, the least significant byte of which represents the intensity of the red color component, the next byte represents the intensity of the green color component, and the most significant byte. The byte represents the brightness of the blue color component.

Pixels can be represented using multiple different pixel color formats within a single computer or workstation, and the more bits that are used to represent a single pixel, the better the representation. It is well known that the range of colors that can be made is wide. For example, the image is C
An external storage device such as a D-ROM can store 24 bits per pixel (bpp), while the same image is displayed on the monitor in the 32 bpp format. Therefore, the computer would be 24 bpp in the above example.
It is necessary to be able to efficiently convert the pixel data from the source format, which is 32.

Currently, the ability to convert pixel data from one color format to another using hardware support is very limited, typically each pixel source format to destination format. The conversion is performed on a pixel-by-pixel basis using software. This process takes from a few microseconds to a few tens of microseconds per pixel, and it takes a considerable amount of processing time to convert all the pixels of a single image.

On the other hand, hardware can only be used for reformatting a particular set of pixels, ie converting from one color format to another. For example, the above conversion from a 24 bit per pixel format to a 32 bit per pixel format can be hardwired into the system. Unfortunately, this technique also suffers a great deal of tradeoff flexibility in exchange for a minimal increase in overall conversion speed.
Incomplete.

Another technique currently in use is 1
A color expansion technique used with character data stored in a bit-by-pixel format. In the 1-bit-per-pixel format, "0" represents the background pixel,
"1" represents the foreground pixel. The foreground and background colors are stored in the foreground and background registers, and each "1" of the source data causes the display of the color corresponding to the value of the foreground register at the corresponding pixel position, and each "0". ,
Causes the display of the color corresponding to the value of the background register at the corresponding pixel location. This technique is also imperfect as it is limited to the 1 bpp format and limited to selecting from two colors.

OS / 2 from IBM and Wi from Microsoft in the personal computer (PC) industry.
Increasing use of operating systems with windowing capabilities such as Windows and the trend towards graphics adapters with direct color modes has resulted in faster pixel reformatting operations and the ability to achieve multiple different source formats. Is a rationale for the need to enable the conversion of multiple different destination formats.
Another rationale for this need is the fact that the industry is increasingly focusing on the performance of PC graphics. This is one of the main selling points of graphics accelerator display adapters.
MARK "value, that is, the fact that it is a benchmark number assigned to a computer component based on various performance criteria. Future WI
It is very likely that the NMARK value will take into account the speed of the memory-to-screen copy operation when the source and destination formats are different.

The available techniques for converting between pixel formats serve that purpose, but especially in view of the recent demand for graphics subsystems.
Very slow. This conversion process may be somewhat faster by hard-wiring a particular conversion, but such a hard-wiring solution provides the flexibility needed to allow conversion between multiple different pixel formats. Cannot provide sex.

[0009]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to reformat pixels encoded in a first or source format to a second or destination format in a fast and efficient manner. Is to provide an arrangement.

[0010]

SUMMARY OF THE INVENTION The solution to the above problems and the achievement of technological advances have been made possible by hardware-assisted pixel reconfiguration during a bit boundary block transfer (BITBLT) from a source memory location to a destination memory location. A method and apparatus for formatting is provided. Unlike the prior art, dedicated hardware, referred to herein as reformatting logic, is incorporated into the computer to transfer pixel data encoded in the m bit per pixel (bpp) source format during, for example, screen refresh. , N bpp
Automatically reformat to the destination format of.

In the preferred embodiment, the reformatting logic is the otherwise normal BITB of the system.
Implemented in the LT engine, during each BITBLT from the source memory location to the destination memory location, each of the m-bit source pixel data words in the block pixel data transferred is routed through m input lines. Input to the reformatting logic. The reformatting logic converts the pixel data from the m-bit source format to the n-bit destination format and outputs the reformatted pixel data to the destination memory location via n output lines.
The reformatting logic includes m-bit source pixel data
A look-up table for mapping each bit of pixel data from the first bit position in the word to the second bit position in the n-bit destination pixel data word and m inputs of the reformatting logic according to the instructions in the look-up table. From one of the reformatting logic's n outputs to one or more of the n outputs of the reformatting logic is physically connected to a look-up table and controlled by the look-up table. Format engine and. Thus, each bit of the pixel data word can be mapped from one bit position in the m bpp source bitmap to a second bit position in the n bpp destination bitmap, thereby programming the appropriate entry in the lookup table. Only then can the pixel data be reformatted.

In one embodiment, the look-up table contains n entries, one for each bit position of the destination pixel data word or one for each pit plane of the destination bitmap. For example, if the destination format is 32 bpp, the look-up table contains 0 through 3 corresponding to bits 0 through 31 of the destination pixel data word, respectively.
It contains 32 table entries numbered 1 through 1. For the most significant 2 bits or more of each table item, the value of the source bit position indexed by the remaining bits of the table item that make up the "source index" is set to the destination bit indexed by that table item number. Function code to map to position,
A function code is included which causes a binary 0 or 1 to be written to the indexed destination bit position, regardless of the value of the source index. The remaining bits of each table entry constitute the index of the bit position of the source bit that maps to the corresponding destination bit position and are therefore referred to as the source bit position index. For example, if the source bit position index of table entry 0 is 4
For h, bit 4 of the source pixel data word is mapped to bit 0 of the destination pixel data word. In other words, bit plane 4 of the source bitmap is mapped to bit plane 0 of the destination bitmap. The lookup table arrangement shown above allows multiple planes in the source bitmap to be mapped to a single plane in the destination bitmap.

In an alternative embodiment, the look-up table contains m table entries, one for each bit position in the source pixel data word or one for each bit plane in the source bitmap. Assuming that the format of the source bitmap is 24 bpp, this look-up table contains 24 individual numbered numbers 0 to 23, each corresponding to bit 0 to bit 23 of the source pixel data word. Items are included. Again, the most significant 2 bits of each table entry contain a function code similar to the above, with the remaining bits making up the destination index rather than the source index. Thus, if the index of table entry 0 is 4h, then bit 0 of the source pixel data word is mapped to bit 4 of the destination pixel data word. In other words, bit plane 0 of the source bitmap is mapped to bit plane 4 of the destination bitmap.

The steering logic has m inputs to the reformatting logic to route each bit of the source pixel data to the appropriate destination bit position or bit plane as specified by the values in the look-up table. n
Appropriate logic gates and other hardware components are included to provide the appropriate physical connections to one or more of the outputs.

A technical advantage achieved by the present invention is that it can be used to reformat pixel data to present images of arbitrary size.

Another technical advantage achieved by the present invention is improved performance over conventional software reformatting techniques.

Another technical advantage achieved by the present invention is the flexibility to convert any direct color format to any other direct color format. .
Further, the present invention is flexible enough to perform color compare, extend, transform and select operations in a single embodiment.

[0018]

1 illustrates a computer 10 embodying features of the present invention. Computer 10 includes a host 10a to the left of dashed line 11 and a video subsystem 10b to the right of dashed line 11. The host 10a has a system
A CPU 12, a system memory 14, a hard disk and a CD-RO interconnected via a bus 18.
An external storage device 16 such as M is included. The image displayed on the display device 20 of the video subsystem 10b can be stored in the external storage device 16, as described below.

In addition to the display device 20, the video subsystem 10b includes a bus interface 22 for interfacing the video subsystem 10b to the host 10a. Graphics coprocessor 24 allows bus interface 22 via bus 25
Connected to a video RAM (VRAM) 26 or "frame buffer" and a RAMDAC 28
It is connected to the bus interface 22 via the bus 23. The display device 20 is connected to the output of the RAMDAC 28.

Bit boundary block transfer (BITBLT)
Engine 30 is implemented in graphics coprocessor 24 in this figure. However, the BITBLT engine 30 is independently addressable by the CPU 12 and may be on the video bus 23 or the system bus 18
It should be appreciated that it may exist directly above. BITBL
The main function of the T-Engine 30 is to transfer a rectangular block of data from the source memory location to the destination memory location. For example, using the BITBLT engine 30,
From system memory 14 to VRAM 26, VRAM 2
6 to system memory 14, system memory 14
From one location in the system memory to another location in the system memory 14,
Alternatively, a block of data can be moved from one location in VRAM 26 to another location in VRAM 26. In all cases, it is understood that in this context the term "source" refers to the memory location from which the block of data was transferred and "destination" refers to the memory location to which the block of data is transferred. I want to.

As shown previously, the digital pixel data of the image displayed on the display device 20 is stored in the external storage device 16.
Can be stored in. During normal display operation, the pixel data is read from the external storage device 16 into the system memory 14 and then transferred to the VRAM 26 by the BITBLT engine 30. Thereafter, the digital pixel data is output from the VRAM 26 to the RAMDAC 28. RAMDAC 28 converts the digital data into analog red, green and blue signals for driving display 20. Display device 20 typically includes a CRT with red, green and blue electron guns, the intensity of which is controlled by the signal of RAMDAC 28.

Moving blocks of pixel data from system memory to VRAM using the BITBLT engine and converting digital pixel data output from the VRAM to analog red, green and blue signals using RAMDAC. However, driving a CRT display is a concept well known in the art and will not be described further.
However, the source memory, in this case the system memory 14
A problem arises when the format of the pixel data stored in is different from the format of the pixel data stored in the destination memory, which in this case is VRAM 26. For example, the pixels that make up the image are stored in the system memory 14
Although it is stored in the 24 bpp format in the display device 20, it is displayed in the 32 bpp format on the display device 20, and thus may be stored in the 32 bpp format in the VRAM 26. Therefore, at some point before the pixel can be displayed, the pixel data must be converted from the source pixel data format (ie 24 bpp) to the destination pixel data format (ie 32 bpp). As will be explained in more detail below, in the present technique, this reformatting problem causes each BITBLT of pixel data from system memory 14 to VRAM 26.
It is solved by providing reformatting logic within BITBLT engine 30 that is capable of performing one or more types of reformatting operations during.

FIG. 2 is a block diagram of the BITBLT engine 30. As can be seen, BITBLT engine 30 includes reformatting logic 200 having m inputs and n outputs for converting pixel data from an m-bit source format to an n-bit destination format during BITBLT. Throughout this specification, "m" represents the number of pixels per bit in the source pixel data format,
It should be appreciated that "n" represents the number of pixels per bit in the destination pixel data format. Pixel data is input to the reformatting logic 200 from the source memory location via m input lines, one m-bit pixel data word at a time, as further described in connection with FIG. Sometimes one n-bit pixel data word is output from reformatting logic 200 to the destination memory via n output lines.

FIG. 3 illustrates the reformatting logic 2 of FIG.
00 is a more detailed block diagram of 00. As can be seen, reformatting logic 200 includes control lines 304.
A lookup table 300 is included that is connected to the reformatting engine 302 via the.

The function of look-up table 300 is to map each bit of pixel data from a first position in the source pixel data word to a second bit position in the destination pixel data word. The lookup table 300 can also be described as mapping each bit of the first bit plane of the source bitmap to the second bit plane of the destination bitmap. The reformatting engine 302 performs each reformatting operation as specified by the entry in the lookup table 300, so that each bit of pixel data is appropriately transferred from the source bit position (or bit plane) to the destination bit position (or bit plane). To provide a physical connection between m inputs and n outputs. One input bit can be connected to one or more output bits.

In one embodiment, the lookup table 300 contains n
Table entries, each entry being a 1-bit position in the destination pixel data word or 1 of the destination bitmap.
Corresponds to the bit plane. Therefore, assuming the destination format is 32 bpp, there are 32 entries in the lookup table 300, table entry 0 indicates the binary value mapped to destination bit position 0, and table entry 1 is the destination bit position. It shows a binary value mapped to 1, and the same applies to the table item n-1. Function code that maps the value at the source bit position indexed by the remaining bits that make up the "source index" to the destination bit position indexed by the table item number, in the two or more most significant bits of each table entry. , A function code that causes a binary 1 or 0 to be written to the indexed destination bit position, regardless of the source index. A list of specific 3-bit function codes and their corresponding operations is shown in Table 1 below.

[Table 1] Code Action 000 2 for indexed destination bits
Write base 0 001 2 in destination bit indexed
Write base 1 010 Map indexed source bits to indexed destination bits 011 Invert source bits 100-111 Reserved

An example is given below to show the usage of the above function code. If the table entry 0 function code is 000, a binary 0 is written to bit 0 of the destination pixel data word regardless of the value of the bit indexed by the source index. Function code of table item 0 is 0
01, bit 0 of the destination pixel data word, regardless of the value of the bit indexed by the source index.
A binary 1 is written in. If the table entry 0 function code is 010, the value of the bit indexed by the source index is unaltered mapped to bit 0 of the destination pixel data word. If the table entry 0 function code is 011 then the inverted value of the bit indexed by the source index is mapped to bit 0 of the destination pixel data word.

As indicated above, as long as the function code of a particular table entry is 10, the corresponding source index is mapped to a bit in the destination pixel data word indexed by the table entry number. Used for indexing bits within a pixel data word. For example, suppose the value of the source index of table entry 0 is 4h and the corresponding function code is 10, then each bit 4 of the source pixel data is
Maps to bit 0 of each of the destination pixel data words. In other words, the source bitmap bit
Plane 4 is bit plane 0 of the destination bitmap
Is mapped to. Reference table 3 in the form described above
Indexing 00 allows multiple source bit planes to be mapped to a single destination bit plane. This may be desirable for certain color expansion operations known in the art. Also, it should be understood that the number x of bits forming the source index in the lookup table is m = 2 ^x . For example, for a 32 bpp source format, the number of bits that make up the source index is 5 and 1
The remaining 3 bits of the table entry of bytes can be used as a function code.

In an alternative embodiment, the lookup table 300 contains
There are m entries corresponding to each of the m bits of the source pixel data word. Therefore, each table entry contains a destination index and a function code rather than a source index.
Similar to the function of the source index, the destination index indexes the bits within the destination pixel data word to which the bits of the source pixel data word indexed by the table entry number are mapped. In this alternative embodiment, assuming that the destination index for table entry 0 is 4h and the corresponding function code is 10, each bit 0 of the source pixel data word is the destination pixel data. Mapped to bit 4 of each of the words, which effectively remaps plane 0 of the m bpp source bitmap to plane 4 of the n bpp destination bitmap.

The table items in the reference table 300 are:
Initially set by software, this software can be stored in system memory 14 and executed by CPU 12 in response to the particular reformatting operation being performed. Once the look-up table 300 has been initialized, it is used to set the reformatting engine 302 so that each source pixel data word, as described further with reference to FIGS. Of each of the m bits of R is correctly routed to one or more of the n bit positions of the destination pixel data word.

FIGS. 4-6 are diagrams illustrating the operation of reformatting logic 200 of the present invention. It should be noted that the reformatting operations shown in FIGS. 4-6 are merely examples illustrating the flexibility of the present invention and should not be construed as indicating a particular desired type of formatting operation.

Referring to FIG. 4, reference numeral 400 indicates that
Source pixel data encoded in the 4 bpp source format
Reformatting logic is shown for reformatting word 400a into destination pixel data word 400b encoded in the 8bpp destination format.
The initialized look-up table 402 contains eight table entries 0 through 7, connected to a reformatting engine 404 with input-output connections set according to the table entries in the look-up table 402, as described below. Has been done.

Referring to the lookup table 402, table entry 0 contains a function code 00 corresponding to the "write a binary 0" operation. As a result, the source index is ignored and reformatting engine 404 makes an electrical connection between output 0 and logic 0, as indicated by line 406, where the binary 0 is the destination pixel data word. Four
It is output to bit 0 of 00b. Table item 1 contains
Function code 0 corresponding to the operation of "writing a binary 1"
1 is included. As a result, the source indicator is ignored and reformatting engine 404 creates an electrical connection between output 1 and logic 1 as indicated by line 408, 2
The base 1 is output on bit 1 of the destination pixel data word 400b. Table entry 2 contains a function code 10 corresponding to the operation "Map Indexed Source Bits" and a source index 01. As a result, reformatting engine 404 creates an electrical connection between output 2 and input 1 as indicated by line 410, which is the binary value of bit 1 of source pixel data word 400a, in this case 1 is the destination pixel data word 400b
Is mapped to bit 3 of Table item 3 contains
A function code 10 and a source index 00 are included. As a result, reformatting engine 404 creates an electrical connection between output 3 and input 0, as indicated by line 412, which is the binary value of bit 0 of source pixel data word 400a, in this case 1 is the destination pixel data word 400b
Is mapped to bit 3 of In a similar fashion, reformatting engine 404 uses lines 414, 416, 418.
And 420, output 4 and input 3, output 5 and input 2, output 6 and input 1, output 7 and input 0.
An electrical connection between the source pixel data word 40 and
The binary value of bits 3, 2, 1 and 0 of 0a (0, 1, 0 and 1 respectively) are stored in the destination pixel data word 400b.
Are mapped to bits 4, 5, 6, and 7.

5 and 6 illustrate the 8 bpp destination bitmap 412 resulting from the operations described above.
4 bpp source bitmap 4 to 8 bit planes
It is a figure which shows the mapping of 10 4 planes. For simplicity of illustration, the function codes of the lookup table 402 are not shown in FIG. 5 and each of the source indices is shown as a decimal value. Due to the effect of the function codes of table items 0 and 1 (FIG. 4), all bits of plane 0 of destination bitmap 412 are 0, and all bits of plane 1 are 1. Further, bit plane 1 of source bitmap 410 is mapped to bit planes 2 and 6 of destination bitmap 412, and bit plane 0 of source bitmap 410 is bit planes 3 and 7 of destination bitmap 412. , And the bit plane 3 of the source bitmap 410 is mapped to the bit plane 4 of the destination bitmap 412.
Bit plane 2 of 0 is mapped to bit plane 5 of destination bitmap 412. The above mapping is illustrated more clearly in FIG.

FIG. 7 is a partial schematic block diagram of a preferred embodiment of reformatting engine 302 for performing the reformatting operations shown in FIGS. 4-6. As can be seen in FIG. 7, the source pixel data word 40
The source bit of 0a (FIG. 4) is the multiple bits of the multiplexer (M
UX) 504a through 504d applied to inputs 0 through 3. Table item number 0 of the reference table 402
2 to 3 of the 2-bit source index are respectively MUX504
a to 504d select inputs S0 or S1 are applied to select the source bit output from each MUX 504a to 504d. The outputs of MUXs 504a through 504d are applied to inputs 2 and 3 of MUXs 508a through 508d, respectively. MUX 508a through 508
Input 0 of d is connected to logic 0 and input 1 is connected to logic 1. The 2-bit function codes of the table item numbers 0 to 3 in the reference table 402 are respectively MUXs.
The destination pixel data word 400b from each MUX is applied to the select input S0 or S1 of 508a through 508d.
Each MU output to bit positions 0 to 3 of (FIG. 4)
Select the X input.

For example, the function code 0 of table item 0
0b is applied to the select input of MUX 508a and the bit 0 applied to that input 0 is assigned to the destination bit position 0.
Output. Similarly, function code 0 of table item 1
A 1 is applied to the select input of MUX 508b, causing the bit applied to that input 1 to be output at destination bit position 1. Referring to MUX 504c and 508c, the source index 01b of table item 2 is MUX 504c.
, Which is applied to its select input and is applied to its input 2, causes the MUX 504c to output to inputs 2 and 3 of MUX 508c. The function code 10b of table entry 2 is applied to the control input of MUX 508c and the bit 1 applied to its input 2 is set to MUX 508c.
Output to destination bit position 2. Finally, MUX5
04d and 508d, source index 00b of table entry 3 is applied to the select input of MUX 504d and the bit 1 applied to its input 0 is MUX.
Output from inputs 504d to inputs 2 and 3 of MUX 508d. Function code 10b of table item 3 is MUX5
The bit that is applied to the control input of 08d and that is applied to its input 2, 1 is output from MUX 508d to destination bit position 3.

Although not shown, an additional MUX connected in a similar fashion is the destination pixel data word 400b.
It is to be understood that the destination bits 4-7 of (FIG. 4) are provided in the reformatting engine.
It should also be appreciated that the circuit shown in FIG. 7 is for illustrative purposes only and that any number of known logic techniques and components may be used to implement reformatting engine 302. .

In a specific method using the above invention,
Each of the source color components is copied to the corresponding destination color component. In other words, the source red component is copied to the destination red component, the source green component is copied to the destination green component,
The source blue component is copied to the destination blue component. When the number of bits forming the destination color component is smaller than the number of bits forming the corresponding source color component (that is, m> n), the least significant bit of the source color component is ignored and the truncation operation is executed. This truncation considers the value of the discarded most significant bits of the source color component (via the rounding operation) and, as a result,
It is preferable that the remaining value is rounded up or down as appropriate.

Conversely, the number of bits of the destination color component is greater than the number of bits of the corresponding source color component (ie m <
n), the upper bits of the source color component are repeated with the lower bits of the destination color component to get the best approximation.

Below are four examples of the method described above. Color extension from 16-bit RGB source format (red 5 bits, green 6 bits, blue 5 bits) to 32-bit XRGB destination format (red 8 bits, green 8 bits, blue 8 bits). 2. Color conversion from 24-bit RGB source format (8-bit red, 8-bit green, 8-bit blue) to 24-bit BGR (8-bit blue, 8-bit green, 8-bit red). 3. Color compression from 24-bit RGB source format (red 8 bits, green 8 bits, blue 8 bits) to 16-bit RGB destination format (red 5 bits, green 6 bits, blue 5 bits). 4.8 Color selection, extracting plane 0 and plane 4 from an 8-bit source bitmap to create a 2-bit destination bitmap.

Example 4, perhaps somewhat esoteric, illustrates the flexibility of the present invention. In the form described above, the lookup table 300 of FIG. 3 is used, as described above, with the appropriate function code and index values to cause the reformatting engine 302 to make the appropriate input-output connections.
The following types of reformatting operations can be easily performed using the apparatus and method of the present invention by simply programming 1. Color extension Converting from m-bit pixel to n-bit pixel when m <n. 2. Color conversion Converting an m-bit pixel of one format to an n-bit pixel of another format when m = n. 3. Color compression Converting m-bit pixels to n-bit pixels when m> n. 4. Color selection Pixel conversion by copying the selected plane.

In operation, the lookup table 402 entry is initially set by software. In this manner, reformatting logic 200 can be programmed to perform any one of the reformatting operations of the type described above. Pixel data representing an image displayed on the display device 20 is copied from the external storage device 16 to the system memory 14. This data is m
It is stored as a bpp bitmap. BITBL
A rectangular block of pixel data retrieved from the system memory 14 by the T-Engine 30 is sent via m input lines, one m-bit pixel data word at a time,
Input to the reformatting engine 302, where the reformatting engine connects each of the m input lines to one or more of the n output lines as specified in the lookup table 300 to obtain an n-bit destination pixel. Reformatted into data words.

It should be appreciated that the present invention can employ numerous forms and embodiments. It is to be understood that the examples provided herein are for the purpose of illustration, not limitation of the invention, and that variations may be made without departing from the spirit or scope of the invention. For example, BI
Rather than being implemented in the TBLT engine 30, the reformatting logic 200 resides directly on the system bus 18 or video bus 23, where the data resides, for example when the CPU MOV instruction is executed. Is written to another location, the operation is BITBLT.
Reformatting can always be performed regardless of whether it is performed as BITBLT by the engine 30. Further, reformatting engine 302 may include any number of known combinations of logic elements and circuits. Further, the reference table 30
0 can be comprised of any of a number of different storage devices, and display device 20 can include any type of display device other than a CRT, such as a liquid crystal display (LCD).

While illustrative embodiments of the present invention have been illustrated and described, the foregoing disclosure is intended to cover a wide range of modifications, changes and substitutions, and in some cases only some of the features of the present invention. It can be used without the corresponding other features. Therefore, it is appropriate that the claims be construed broadly in a manner consistent with the scope of the present invention.

In summary, the following is disclosed regarding the configuration of the present invention.

(1) The pixels stored as m-bit words in the first memory location are stored in the second memory location n.
A device for converting to a bit word, electrically connected to the first memory location for receiving the m-bit word from the first memory location, and outputting the n-bit word to the second memory location A reformatting engine electrically connected to the second memory location for connecting to the second memory location, and at least electrically associated with the reformatting engine and associated with a bit location of the n-bit word to indicate a bit source. Contains one table entry,
A reformatting engine, so that a bit provided by the indicated bit source is output to the associated n-bit word bit position. And the related n
A device characterized by making an electrical connection between a bit, a word and a bit position. (2) The at least one table entry includes a source index for indexing bit positions of the m-bit word, and the indicated bit source includes the indexed m-bit word bit positions. , The bit provided by the indicated bit source is
Apparatus according to claim (1), characterized in that it comprises a binary value stored in the indexed m-bit word bit position. (3) The at least one table entry includes a "write binary 1" function code, the indicated bit source includes a + 5V source, and the bit provided by the indicated bit source. Includes the binary number 1. The apparatus according to (1) above. (4) The at least one table entry includes a "write binary 0" function code, the indicated bit source includes electrical ground, and the bit provided by the indicated bit source. Includes a binary number 0, the apparatus according to (1) above. (5) The device according to (1) above, wherein m and n are positive integers, and m is larger than n. (6) The device according to (1) above, wherein m and n are positive integers, and m is smaller than n. (7) The device according to (1) above, wherein m and n are positive integers, and m and n are equal. (8) The apparatus according to (1) above, wherein the reformatting engine includes at least one logical element whose state is controlled by the at least one table entry. (9) The conversion is a bit boundary block transfer (B) of pixel data from the first memory location to the second memory location.
It occurs during ITBLT), The device according to (1) above. (10) Each table entry is associated with a bit plane of the second bitmap and includes an index for indexing the bit plane of the first bitmap, each table entry including a plurality of said table entries each indicating a bit source. , A lookup table and a second bit associated with the indicated bit source for mapping bits from the indicated bit source to the associated second bitmap bit plane for each of the table entries. map·
Reformatting engine connected to the look-up table to create an electrical connection to and from a bit plane and reformatting pixel data from the format of the first bitmap to the format of the second bitmap. Device for doing. (11) The apparatus according to (10) above, wherein the indicated bit source constitutes the indexed first bitmap bit plane. (12) At least one of the table items is
In addition, including the function code "write binary 1",
Apparatus according to claim (10), characterized in that the bit source indexed by the at least one of the table entries comprises a + 5V source. (13) At least one of the table items is
In addition, including the function code "write binary 0",
The apparatus according to (10) above, wherein the bit source indexed by the at least one of the table entries comprises electrical ground. (14) The apparatus according to (10) above, wherein the reformatting engine includes a hardware logic element whose logic state is controlled by the plurality of table entries. (15) transferring the pixel data during a bit boundary block transfer (BITBLT) of the pixel data from a source memory location where the pixel data is stored in a source format to a destination memory location where the pixel data is stored in a destination format. A bit boundary block transfer engine for converting from the source format to the destination format,
Outputting destination format pixel data to the destination memory location having a plurality of inputs coupled to the source memory location and electrically coupled to the source memory location for receiving source format pixel data from the source memory location. A reformatting engine and each table entry electrically connected to the destination memory location with multiple outputs for
A source index associated with a bit position of the destination format pixel data word, each mapping to a source index for indexing a bit position of the source format pixel data word, and the associated destination format pixel data word bit position. A reference table connected to the reformatting engine, the table entry including a function code for indicating a bit to be associated with, and the associated destination format when the function code includes a first value. A bit boundary block transfer engine, wherein the bits mapped to locations include bits at the indexed bit locations of the source format pixel data word. (16) When the function code includes a second value, the bit mapped to the associated destination format pixel data word bit position includes a binary 1 (15). Bit boundary block transfer engine described in. (17) In response to the function code including a third value, the bit mapped to the associated destination format pixel data word bit position includes a binary 0. 15) A bit boundary block transfer engine according to 15). (18) The source format is a pixel for every m bits, and the destination format is a pixel for every n bits,
The bit boundary block transfer engine according to (15) above, wherein m and n are positive integers, and the reference table includes n table entries. (19) The reformatting engine has m inputs and n outputs, (18)
Bit boundary block transfer engine described in. (20) m is n or less, the above (1)
8) A bit boundary block transfer engine described in 8). (21) The above (1), characterized in that m is larger than n.
8) A bit boundary block transfer engine described in 8). (22) An apparatus for converting a pixel stored as an m-bit word in a first memory location into an n-bit word stored in a second memory location, the apparatus comprising: A reformatting engine electrically coupled to the first memory location for receiving a word and electrically coupled to the second memory location for outputting the n-bit word to the second memory location;
Electrically to the reformatting engine including a destination index and a function code for indexing a bit position of the n-bit word and including at least one table entry associated with the bit position of the m-bit word. A connected look-up table, the associated m-bit word, when the function code is a first value.
The binary value at the bit position is the indexed n
The reformatting engine creates an electrical connection between the associated m-bit word bit position and the indexed n-bit word bit position so that it is written to a bit word position. A device characterized by. (23) The reformatting engine is indexed with a + 5V supply so that a binary one is written to the indexed n-bit word bit position when the function code is a second value. N
Device according to (22) above, characterized in that it makes an electrical connection with the bit word bit position. (24) The reformatting engine is indexed to electrical ground so that a binary 0 is written to the indexed n-bit word bit position when the function code is a third value. An apparatus as set forth in (22) above, characterized in that an electrical connection is made to the n-bit word-bit position. (25) A method of converting the pixel data from a pixel format for every m bits to a pixel format for every n bits during a bit boundary block transfer (BITBLT) of pixel data from a source bitmap to a destination bitmap, each of which is described above. A lookup table containing n table entries associated with destination bit planes of a destination bitmap, each of the n table entries indicating a source of bits mapped to the associated destination bit plane; Initializing, and for each table entry, using a reformatting engine to create an electrical connection between the associated destination bit plane and the indicated bit source; and BITB.
Retrieving the block of pixel data from the source bitmap using the LT engine;
One bit word at a time, the searched pixel data
Inputting a block to the reformatting engine and outputting the block of data from the reformatting engine to the destination bitmap, one n-bit word at a time. (26) Each of the n table items includes a source index, and for each of the n table items, the step of initializing includes the destination bit plane to which the source index is associated. Further comprising initializing a source bit plane mapped to an indexed source bit plane, the step of creating the electrical connection between the indexed source bit plane and the associated destination bit plane. The method according to (25) above, further comprising the step of: (27) At least one of the n table items
Wherein each of the at least one of the n table entries includes a step of setting the function code to a first value. The method of (25) above, wherein the step of creating further comprises creating an electrical connection between a + 5V source and the associated destination bit plane. (28) At least one of the n table items
Wherein each of said at least one of said n number of table entries, said initializing step further comprises the step of setting said function code to a second value. The method of claim 25, wherein the creating step further comprises creating an electrical connection between an electrical ground and the associated destination bit plane.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a computer system that implements features of the present invention.

2 is the computer of FIG. 1 embodying features of the present invention;
FIG. 3 is a block diagram of a bit block transfer engine of the system.

FIG. 3 is a block diagram of reformatting logic for implementing the present invention.

4 illustrates an example of reformatting operations performed using the reformatting logic of FIG.

5 illustrates an example of reformatting operations performed using the reformatting logic of FIG.

6 illustrates an example of reformatting operations performed using the reformatting logic of FIG.

7 is a schematic block diagram of a possible implementation of the reformatting engine of the reformatting logic of FIG.

[Explanation of symbols]

10 Computer 10a Host 10b Video Subsystem 12 CPU 14 System Memory 16 External Storage Device 18 System Bus 20 Display Device 22 Bus Interface 23 Video Bus 24 Graphics Auxiliary Processor 25 Bus 26 Video RAM (VRAM) 28 RAMDAC 30 Bit Boundary Block Transfer (BITBLT) Engine 200 Reformatting Logic 300 Lookup Table 302 Reformatting Engine 304 Control Line 400a Source Pixel Data Word 400b Destination Pixel Data Word 402 Lookup Table 404 Reformat Engine 410 Source Bitmap 412 Destination Bitmap 504a-504d Multiplexer (MUX) 508a-508d MUX

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Jay P. Michael O'Hara United States 33433 Boca Raton, Florida Arbor Club Way 557606

Claims (28)

(57) [Claims] 1. An apparatus for converting a pixel stored as an m-bit word in a first memory location into an n-bit word stored in a second memory location, the m-bit word from the first memory location. A reformatting engine electrically coupled to the first memory location for receiving a word and electrically coupled to the second memory location for outputting the n-bit word to the second memory location; A lookup table electrically connected to the reformatting engine and including at least one table entry associated with a bit position of the n-bit word to indicate a bit source, provided by the indicated bit source. 1 bit is
The reformatting engine creates an electrical connection between the indicated bit source and the associated n-bit word bit position for output to the associated n-bit word bit position. A device characterized by: 2. The at least one table entry includes a source index for indexing bit positions of the m-bit word, the indicated bit source being the indexed m-bit word bit position. And the bit provided by the indicated bit source comprises a binary value stored in the indexed m-bit word bit position.
The device according to claim 1. 3. The at least one table entry is
A "binary 1's" function code is included, wherein the indicated bit source includes a + 5V source, and the bit provided by the indicated bit source includes a binary 1; The device according to claim 1, wherein 4. The at least one table entry is
Including a "write binary 0" function code, wherein the indicated bit source comprises electrical ground, and the bit provided by the indicated bit source comprises a binary 0. The device according to claim 1, wherein 5. A device according to claim 1, characterized in that m and n are positive integers and m is greater than n. 6. The apparatus of claim 1, wherein m and n are positive integers and m is less than n. 7. The apparatus of claim 1, wherein m and n are positive integers and m and n are equal. 8. The apparatus of claim 1, wherein the reformatting engine includes at least one logical element whose state is controlled by the at least one table entry. 9. The apparatus of claim 1, wherein the conversion occurs during a bit boundary block transfer (BITBLT) of pixel data from the first memory location to the second memory location. 10. A plurality of said table entries, each table entry being associated with a bit plane of a second bitmap and including an index for indexing the bit plane of the first bitmap, each indicating a bit source. A lookup table, and for each of the table entries, mapping a bit from the indicated bit source to the associated second bitmap bit plane to associate the indicated bit source with the associated first bit. A pixel from the format of the first bitmap to the format of the second bitmap, including a reformatting engine connected to the look-up table to create an electrical connection to and from a two-bitmap bitplane. A device for reformatting data. 11. The apparatus of claim 10, wherein the indicated bit source comprises the indexed first bitmap bit plane. 12. At least one of said table entries
11. One further comprises a "write a binary one" function code, wherein the bit source indexed by the at least one of the table entries comprises a + 5V supply. The device according to. 13. At least one of said table entries
11. One further comprises a "write a binary zero" function code and the bit source indexed by the at least one of the table entries comprises an electrical ground. The device according to. 14. The reformatting engine includes hardware logic elements whose logic states are controlled by the plurality of table entries.
An apparatus according to claim 1. 15. The pixel during a bit boundary block transfer (BITBLT) of the pixel data from a source memory location where pixel data is stored in a source format to a destination memory location where the pixel data is stored in a destination format. A bit boundary block transfer engine for converting data from the source format to the destination format, the bit boundary block transfer engine electrically connected to the source memory location to electrically receive the source format pixel data from the source memory location. A reformatting engine having a plurality of inputs connected to the destination memory location and electrically connected to the destination memory location at a plurality of outputs for outputting destination format pixel data to the destination memory location; , The destination format pixel data
Associated with a bit position of a word, each indicating a source index for indexing a bit position of the source format pixel data word and a bit mapped to the associated destination format pixel data word bit position. And a lookup table connected to the reformatting engine, the table entry including a function code of the function code and a lookup table that is mapped to the associated destination format location when the function code includes a first value. A bit boundary block transfer engine, characterized in that bits include bits in the indexed bit position of the source format pixel data word. 16. The bit mapped to the associated destination format pixel data word bit position when the function code comprises a second value comprises a binary one. 15. A bit boundary block transfer engine according to 15. 17. The bit mapped to the associated destination format pixel data word bit position in response to the function code containing a third value comprises a binary zero. The bit boundary block transfer engine of claim 15. 18. The source format is m bits per pixel, the destination format is n bits per pixel, m and n are positive integers, and the lookup table is n.
16. Includes 15 table entries.
Bit boundary block transfer engine described in. 19. The bit boundary block transfer engine of claim 18, wherein the reformatting engine has m inputs and n outputs. 20. The bit boundary block transfer engine of claim 18, wherein m is less than or equal to n. 21. The bit boundary block transfer engine of claim 18, wherein m is greater than n. 22. An apparatus for converting a pixel stored as an m-bit word in a first memory location into an n-bit word stored in a second memory location, the apparatus comprising: A reformatting engine electrically connected to the first memory location for receiving a bit word and electrically connected to the second memory location for outputting the n-bit word to the second memory location. And a destination index for indexing bit positions of the n-bit word and a function code, and at least one table entry associated with the bit position of the m-bit word. And a reference table connected to each other, the associated m-bit word bit position when the function code is a first value. m 2 binary values, said to be written to the indexed n-bit word position, said reformatting engine and the associated at
An apparatus for making an electrical connection between a bit word bit position and the indexed n-bit word bit position. 23. When the function code has a second value, 2
The reformatting engine electrically connects between a + 5V supply and the indexed n-bit word bit position such that a binary one is written to the indexed n-bit word bit position. 23. The device according to claim 22, characterized in that 24. When the function code has a third value, 2
The reformatting engine makes an electrical connection between electrical ground and the indexed n-bit word bit position such that a binary zero is written to the indexed n-bit word bit position. 23. The device according to claim 22, characterized in that 25. A bit boundary block transfer (BITBL) of pixel data from a source bitmap to a destination bitmap.
A method of converting the pixel data from a pixel format for every m bits to a pixel format for every n bits in T), each lookup table including n table entries associated with a destination bit plane of the destination bitmap. Initializing each of the n table entries to indicate a source of bits that is mapped to the associated destination bit plane, and using a reformatting engine for each of the table entries. Making an electrical connection between the associated destination bit plane and the indicated bit source; retrieving the block of pixel data from the source bitmap using a BITBLT engine; , One m-bit word at a time, said searched pixel data block Inputting a block of data to the reformatting engine, and outputting one block of the data from the reformatting engine to the destination bitmap, one n-bit word at a time. 26. Each of the n table entries is
A source index is included, wherein for each of the n table entries the initializing step indexes the source bit plane in which the source index is mapped to the associated destination bit plane. Further comprising the step of initializing, wherein the step of creating further comprises the step of creating an electrical connection between the indexed source bit plane and the associated destination bit plane.
The method of claim 25. 27. At least one of the n table entries includes a function code, wherein n
For each of the at least one of the table items, the initialization step further comprises setting the function code to a first value, and the creating step comprises + 5V supply and the associated destination. 26. The method of claim 25, further comprising making an electrical connection with a bit plane. 28. At least one of said n table entries includes a function code, said n
For each of the at least one of the table entries, the step of initializing further comprises setting the function code to a second value, the step of creating the electrical ground and the associated destination. 26. The method of claim 25, further comprising making an electrical connection with a bit plane.