JP3157507B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to indirect addressing using array-type data, and more particularly, to a main storage device composed of a plurality of memory banks and a vector data called a vector register (array-type data). A list of a plurality of elements having one element of scalar data) and a register for holding, and each element of the vector data held in the vector register is regarded as an address (referred to as a list vector). The present invention relates to a data processing device for reading data from each address of a storage device and performing a special vector access generally called a list vector process.

2. Description of the Related Art Conventionally, when accessing each address element, this type of data processing apparatus performs memory access in the order of list vector elements. When the error occurred, the processing was suspended until the cause disappeared. For example, when an address element that is in the process of processing encounters a bank busy, it waits until the busy is resolved, and even if there is an accessible element in the array of elements after that, it processes in order. I didn't do anything.

FIG. 12 is a conceptual diagram of the configuration of the data processing device described above, and FIG.
The figure is a flowchart of the control.

Read address information from main buffer 12 (step 3
1) Bank busy check section 14
(Step 32). If the bank is busy, it is determined whether or not the save buffer 17 is full (step 33). If it is full, the bank free waits (step 34). If not, the address information is saved in the save buffer 17 (step 35). , And return to step 32. If the bank is not busy in step 32, the request generator 15 generates a request and sends it to the storage device 16 (step 36). Next, it is determined whether or not the main buffer 12 is empty (step 37). If it is not empty, the process returns to step 31. If it is empty, it is determined whether or not the evacuation buffer 17 is empty (step 38). To end. If it is not empty, the address information is read from the save buffer 17 (step 39), and it is checked whether the bank is busy (step 40). If it is busy, it waits for a bank free (step 41). (Step 42), it is again determined whether or not the save buffer 17 is empty (Step 43). If it is not empty, the process returns to Step 40, and if it is empty, the process is terminated.

[Problem to be Solved by the Invention] In the conventional memory access control method described above, when an address element which is in the process of processing encounters a bank busy, the process waits until the busy is resolved, and the subsequent elements are arranged in a row. Even if there is something that can be accessed, since the processing is not overtaken, the amount of access per unit time is reduced by shortening the access processing cycle, etc. Even if it is increased, the probability of encountering a bank busy gradually increases, and there is a disadvantage that the upper limit of the throughput is suppressed before the throughput is sufficiently increased. In addition, it has been easily estimated that if the overtaking process is performed, the influence of the bank busy is reduced and the throughput is improved. However, if the overtaking process is simply performed, the control is performed by a normal means (for example, the number of overtaking buffers). The entries are prepared, the inaccessible addresses are saved, the process proceeds to the address processing of the next element, and the saved addresses are accessed later (see FIGS. 12 and 13). It has been questioned to obtain an effect commensurate with the increase in the complexity of hardware and control logic.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data processing apparatus capable of minimizing the influence of bank busy even in an environment where bank busy frequently occurs, and thereby ensuring a high throughput of list vector processing.

[Means for Solving the Problems] A data processing apparatus according to the present invention includes a storage unit having a plurality of banks, a plurality of entries each having a plurality of address storage units, and a plurality of memories for the plurality of banks. Address information holding means for holding an access destination address of an access request in the plurality of address storage units of each of the entries, and storing the plurality of addresses of a head entry of the plurality of entries from the address information holding means Checking means for reading a plurality of access destination addresses held in the section and simultaneously checking whether or not each of the banks specified by the read access destination addresses is in an accessible state; and Out of a plurality of memory access requests related to a plurality of access Selecting at least one of the memory access requests that can be transmitted to the plurality of banks and transmitting the selected memory access request to the plurality of banks, and selecting at least one of the memory access requests that cannot be transmitted to the plurality of banks; And control means for controlling the transmission to the plurality of banks to be performed and storing the access destination address of at least one memory access request which cannot be transmitted in the last entry of the address information storage means.

[Operation] FIG. 10 is a schematic configuration diagram of a data processing device of the present invention, and FIG.
The figure is a flowchart of the control.

According to the present invention, when each address element of the list vector is accessed, the address information of each element is held in the buffer 12 and sequentially retrieved (step 21), and it is determined whether or not the bank corresponding to the address information is accessible. Inspection is performed by the bank busy section 14 (step 22). If the access is possible, the request generation section 15 generates a request and sends it to the main storage device 16 (step 24). , The address is rewritten to the buffer 12 through the selector 11 (step 23),
The operation of delaying the access and shifting to the processing of the address of the next element is repeated until the buffer 12 becomes empty (step 25).

This makes it possible to reuse the buffer, eliminate the need for a buffer for saving addresses during overtaking processing, and minimize the effects of bank busy even in an environment where bank busy occurs frequently in a control sequence with few conditional branches. As a result, it is possible to secure a high throughput of list vector processing.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a data processing apparatus according to one embodiment of the present invention,
FIG. 2 shows the V of the list address buffer 120 of FIG.
FIG. 3 is a view showing a V-bit buffer capable of forming one bit width of a bit portion, and FIG. 3 is a V-bit buffer shown in FIG. 2, which is a flip-flop 1 bit used for storing V bits. FIG. 4 is a diagram showing a control signal for the V. minute portion, FIG. 4 is a diagram showing the V bit portion of the list address buffer 120 constructed using the V bit buffer of FIG. 2, and FIG.
FIG. 6 shows the execution control unit 900 in detail, FIG. 6 shows the request generation unit 140 in FIG. 1 in detail, and FIG. 7 shows the write address counter 930 in FIG. 1 in detail. ,
FIG. 8 is a diagram showing in detail the logical configuration of the write-back control unit 910 of FIG. 1, and FIG. 9 is a time chart showing the operation of the present embodiment.

This apparatus can process up to four address elements at the same time, and performs pipeline processing having A, B, and C stages. However, the address element held in the buffer corresponding to the address information holding means in the claims is the raw address itself, and therefore, the address generation means in the claims is constituted by a simple register. Further, the present apparatus is constituted by a so-called single-phase sequential circuit in which all storage elements (flip-flops, memories, etc.) are updated in synchronization with a single clock. First, each part will be described. The main storage device 110 includes eight memory ports 800 to 807 # 0 to # 7 that can simultaneously receive one memory request, and 16 banks 810 to 825 # 0 to # 15 inside. The bank cycle time (the time from when a certain bank is accessed once until the same bank becomes accessible) is 4T, and the memory port of #x is mod8 x (divided by 8) It is assumed that data transfer of an address having a remainder of x) is performed, and the bank of #x is assigned an address of mod16 x (the remainder divided by 16 is x). The list address buffer 120 includes an address element part and a V bit part. The address element part has 16 entries of storage words (hereinafter, referred to as address element words) for four address elements # 0 to # 3, and V address. The bit portion is a valid bit (hereinafter, referred to as a V bit) corresponding to each address element # in the address element word.
The word (hereinafter, referred to as a V bit word) including 4 bits V0 to V3 consists of 16 entries, both of which can perform simultaneous read and write operations, and the address is common to both read and write. The address element section can be strobed individually for each address element, and can be partially written in address element units within the address element word. Once read, the V bit section resets all four bits of the address. It is assumed that write can be set and specified individually for each 4 bits. The address element portion can be easily formed by a register file, and the V bit portion can be easily formed by ordinary random logic or the like. The read address counter 830 functions to specify a read address to the list address buffer 120 and to count the values 0 to 15 cyclically.
Since each address element in the address element word is sometimes processed a plurality of times, it is put into a hold state to wait for this. The write address counter 930 functions to specify a write address to the list address buffer 120 and to count the values 0 to 15 cyclically, but the count-up timing is such that the memory request from the line 631 is not permitted. It is instructed by a history signal (described later) and an end-of-address-element-word processing end signal (described later) from the line 551. Register 840 is the list address buffer 120
This is a register for holding the address element read from the address element portion of A in the A stage, and is in a hold state in order to process the held address element in a plurality of times in the event of a memory port conflict (described later). Register 850,860
Is a register for sequentially receiving the address elements of the A stage held in the register 840 in the B and C stages via the lines 841 and 851 respectively. The selector 920 includes a path 921 for loading the initial address element data into the address element part of the list address buffer 120 before the start of the list vector processing, and a path 921 for starting the list vector processing.
A path 851 for re-holding the address element read from the address element part of the list address buffer 120 to the address element part of the list address buffer 120 again via the registers 840 and 850 is selected, and the list address buffer is selected. A selector connected to 120 write data input lines. The selector array 870 has eight independently operable 4-way selectors which can select any one of the four address elements # 0 to # 3 held in the register 860. . Bank Busy
The check unit 130 registers a bank address accessed in the past, holds the bank address for a bank cycle time, receives an address element from the line 121 and a V bit from the line 122, and attempts to access (the V bit is '1'). Checks whether the bank of the address (of the address element ') is busy. It is possible to check whether the bank is busy for up to four addresses at the same time, and up to four bank addresses at the same time. Can be registered. The bank free indicator 880 holds the check result of the bank busy check unit 130 at the B stage.
It consists of a 4-bit register, each bit corresponding to four address elements in the address element word.
The request generation unit 140 outputs the bank free indicator 8
Bank busy check result from 80 and execution control unit 90
It receives the processing target address element information from 0 (described later) and the port address information of each address element from the register 850, and generates a memory request corresponding to each of the memory ports 800 to 807. The request register 890 receives the memory request generated by the request generation unit 140 via a line 621, and sends a bit RQ0 to each of the memory ports 800 to 807.
RQ7 holds the memory request of the C stage. The write-back control unit 910 includes the memory request suppression information from the request generation unit 140 and the execution control unit 900 (described later).
, And controls the strobe of the address element part and the set signal of the V bit part so that the address element in which the memory request is suppressed is written back to the address element part of the list address buffer 120. The execution control unit 900 receives the memory port address of each address element from the address element part of the list address buffer 120 and the V bit from the V bit part, and selects a processing target address element in consideration of memory port contention. The request generation unit 140 and the write-back control unit 910 are notified, and the timing at which the processing (memory request or write-back) of all the address elements in the address element word ends is detected in both the A and B stages. Indicates a hold instruction to the read address counter 830 and the register 840, and the latter notifies the write address counter 930 as count-up timing. The above is a brief description of each part, but for convenience of the following operation description, further detailed description will be given as necessary. The V bit portion of the list address buffer 120 has a V bit
It is composed of four buffers. As shown in FIG. 2, the V-bit buffer has 16 flip-flops 210 to 225 therein, decoders 230 and 240 (230 has an enable input), and a 16-way selector 250. The flip-flops 210 to 225 are of the type having the control signal shown in FIG. 3. For the read operation, the read address is received from the line 201, decoded by the decoder 240, and controlled by the selector 250 to be assigned to the address. At the same time as selecting the output of the flip-flop, it operates to reset the flip-flop. For the write operation, the write address is received from the line 202, the set instruction signal is received from the line 203, the write address is decoded by the decoder 230, and the set address is decoded. Decoder when the indication signal becomes valid
It operates to output the decoding result to 230 and set the flip-flop assigned to that address. The V bit portion of the list address buffer 120 is constructed by connecting the four V bit buffers described above as shown in FIG. Note that a read operation and a write operation can be performed simultaneously. The execution control unit 900, as shown in FIG.
(Held at 0)
4-bit V bits VA0 to VA3 (address elements # 0 to # 3)
VAR510, which is a V-bit register of the A stage consisting of
Priority control (processing is performed in ascending order of address element #) for address elements that perform memory access from the same memory port, and the next address element to be processed is determined.
, A VPBR 540 that receives the output as it is at the B stage, a comparator 530 that detects the end of the processing within the address element word and outputs it to a line 531, and holds the detection information at the B stage 1 An end indicator 550 comprising a bit flip-flop is internally provided. Here, the output of the priority logic 520 is a 4-bit V bit VPA0 to VPA3 (corresponding to address elements # 0 to # 3) indicating the address element to be processed next in the address element word, and the VPBR 540 outputs it. Internal 4V bit VPB0
VPB3 is a V-bit register of the B stage.
Tables 1 to 4 show the logical functions of the priority logic 520. In the same address element word, when memory ports conflict, the lowest address element is given priority. Tables 1 to 4 check whether each address element (# 0 to 3) has the same memory port as its own address element. If it does not, the corresponding bit of the line 521 is determined. Indicates that it is true.

The comparator 530 detects the end of the processing within the address element word by detecting that the next processing address element output by the priority logic 520 matches the unprocessed address element held in the VAR 510. Then, the VAR 510 operates to take in the V bit of the next address element word from the V bit of the list address buffer 120. On the other hand, the case where the end is not detected by the comparator 530 means that the address element to be processed in the address element word of the A stage and the unprocessed address element remains, and in this case, the address element to be processed next in the VAR 510 The V bit corresponding to
Reset individually using the output of Request generator
As shown in FIG. 6, reference numeral 140 includes a memory request permission logic 610, a memory request generation logic 620, and a request suppression history indicator 630. The memory request permission logic 610 receives the bank check result from the line 601 and the output of the VPBR 540 (V bit indicating the address element in the address element word to be processed now) from the line 602, and performs bank processing for all the processing target address elements. It is detected whether or not the line is free. If all the lines are bank-free, the line 611 is set to true (the line 612 is false), and the line 61
3 to 616 processing target address element positions (address element # 0
To # 3), and if there is at least one non-bank-free (ie, bank-busy) address element, the line 611 is false (the line 612 is true) and the line 613- 616
Works as false. That is, the signal on line 611 is a representative memory request permission signal, and the signals on lines 613 to 616 are memory request permission signals in units of address elements. The memory request generation logic 260
The lower three bits (memory port address) of each element address (# 0 to # 3) to be processed from now on are received from the line 603, and each is supplied to the decoder 64 with an enable input.
Decode at 0 to 670, and OR the 4 bits corresponding to each of the 8 bits of the decoded result of each of the 4 sets.
Each memory port is sent as a memory request to each memory port via 621, and each decoder receives a memory request permission signal for each address element from the memory request permission logic 610 on each enable input from lines 613 to 616. Only the memory request of the specified address element is true. Eventually, the request to each memory port is output as the logical OR of the corresponding outputs of the four decoders, but when memory ports conflict, the enable of the decoder of the oldest address element becomes false. , At most one OR input is not true. Request suppression history indicator 630 is line 612
The signal is set on condition that the above signal is true, and reset on the condition that the signal on line 604 is true (reset priority).
4 receives the output of the end indicator 550. In other words, the request suppression history indicator 550 temporarily disables sending of memory requests (writeback occurs).
Is turned on at the time when the processing is completed, and is turned off when the processing of all the address elements in the address element word is completed. The line 631 outputs a signal obtained by ORing the signal on the line 612 and the output of the request suppression history indicator 550. This is the history of the disapproval of the memory request in the address element / word currently being processed. Is a signal that indicates the presence or absence of As shown in FIG. 7, the write address counter 930 is a counter that can be strobed by a line 703. The strobe timing is determined when the request suppression history indicator 630 on the line 701 is turned on (writeback occurs). The count is incremented when the end indicator 550 on the 702 turns on (the request suppression history indicator 630 turns off at this point). The write-back control unit 910 is composed of simple logic as shown in FIG. 8, and has a strobe corresponding to the address element of the list address buffer 120 (common to the address element unit and the V bit unit).
Is received, the output of VPBR 540 (V bit of the processing target address element of the B stage) is received from the line 801, and a memory request non-permission report (write back instruction) from the line 802 is received.
The logic is configured to enable the VPBR output and send it out on line 803. In the above, each part has been described in detail as necessary.
It has a control function to load the initial address element to 0, a function to initialize and start each control unit at the start of address element processing, and a function to detect both address element processing and stop each control unit. It has nothing to do with the invention, and it has been omitted because it does not involve any difficulty in its construction.

 Next, the operation of this embodiment will be described.

First, the selector 920 selects the line 921 side, loads an initial address element into the address element section of the list address buffer 120 by appropriate control, sets an initial V beat word in the V bit section, and initializes various types. Yes (84
0,850860,880,890,510,540,550,630,830,930 are all cleared). Here, the loaded address elements are shown in Table 5.

Next, the processing shifts to address element processing.
825 (banks # 0 to # 15) are all in the free state. Although the present apparatus operates in a pipeline as described above, processing for each address element word will be sequentially described from the top for simplicity. First, the read address counter 830 addresses the address 0, the address element of the list address buffer 120 is sent to the register 840 from the address element part, and the V bit is VAR510 from the V bit part.
(At this time, the V bit at address 0 is reset). Here, VA0 to VA3 = '1111', and the address element memory port addresses of # 0 to # 3 are # 1, # 3,
Since both # 4 and # 6 are different, the output 521 of the priority lodge 520
Becomes '1111', and the output 531 of the comparator 530 becomes true. On the other hand, the state of the bank corresponding to each address element is checked by the bank busy check unit 130. Since all the banks are in the free state, '1111' is naturally output to the bank free indicator 880. Request generator 14
At 0, these are received and the processing target address elements are # 0 to #
3, the memory request permission logic 610 sets the line 611 to true upon seeing that the bank free indicator 880 is '1111', and sends the bank address corresponding to the address elements # 0 to # 3 to the bank busy check unit 130. The selector array 870 receives each address element from the register 860 holding the address element of the C stage, and receives the corresponding memory port (ie, corresponding to elements # 0 to # 3, #
1, # 3, # 4, # 6) are connected. Thus, the processing of the first address element word has been completed.

Next, the processing of the second address element word will be described. First, the read address counter 830 (counted up immediately after the reading of the previous address element word) designates the address 1 and the address element from the address element section of the list address buffer 120 to the register 840, and the V bit The V bit is read out to the VAR 510 from this section (at this time, all V bits at address 1 are reset). Here, VA0-VA3 = '1111', and the memory port addresses of the address elements # 0- # 3 are # 2, # 2, # 6, #
In # 6, since # 0 and # 1 and # 2 and # 3 match,
The output 521 of the priority lodge 520 becomes '1010', the output 531 of the comparator 530 becomes false and the VA0 and VA2 of the VAR510 are reset at the next timing, and the read address counter 830 and the register 840 are reset.
Is set to the hold state. On the other hand, the bank busy check unit 130 checks the status of the bank corresponding to each address element, and the busy banks # 1, # 11, # 4,
# 6 (at this point, it is unregistered but is likely to be registered in the bank, so it is treated as busy), and '1111' is output to the bank free indicator 880. The request generation unit 140 receives these, and the address element to be processed is #
When the bank free indicator 880 is '1111' at 0 and # 2, the memory request permission logic 610 sets the line 611 to true, and the bank busy check unit 130 responds to the address elements of # 0 and # 2. When the bank address is registered, the selector array 870 receives each address element from the register 860 holding the address element of the C stage, and receives the corresponding memory port (that is, # corresponding to elements # 0 and # 2,
2, # 6) are connected. Next, for the remaining address elements in the same address element, VA0 to VA3 = '0101',
Since the memory port addresses of the address elements # 1 and # 3 are different, the output 521 of the priority logic 520 becomes '0101', the output 531 of the comparator 530 becomes true, and the read address counter 830 and the register 840 are held. Release it,
The end indicator 550 is turned on at the next timing. On the other hand, the bank busy checker 130 checks the status of the bank corresponding to each address element. Both the banks # 1 and # 3 are busy, and '0000' is output to the bank free indicator 880. Is done. The request generation unit 140 receives these, and the address elements to be processed are # 1 and # 3, and the bank free indicator 880 is '0'.
Seeing 100 ', the memory request grant logic is line
611 is false (612 is true), and the bank busy check unit 13
0 does not instruct registration of any bank address. On the other hand, when the write-back control unit 910 receives a report indicating that the memory request has been rejected via the line 612, the pattern '01
A strobe of 01 'is generated, and address elements # 1 and # 3 are written in the address element of address 0 which is the address indicated by the write address counter 930 of the list address buffer 120, and V1 of the V bit section is written. , V3 is set.
Further, the write address counter 930 indicates that the line 631 is true (the write-back processing has been performed in the processing in the current address element word), and the output 551 of the end indicator 550 is output.
Is true (the current address element word processing has been completed), and is counted up at the next timing in preparation for the next write-back processing. This completes the processing of the second address element word.

Next, the processing of the third address element word will be described. First, the read address counter 830 (counted up immediately after the reading of the previous address element word) addresses the address 2, and the address element from the address element section of the list address buffer 120 is sent to the register 840, and V The V bit is read from the bit portion to VAR510 (at this time, all V bits at address 1 are reset). Here, VA0-VA3 = '1111', and the memory port addresses of the address elements # 0- # 3 are # 6, # 0, # 0, # 6, respectively.
Since # 0 and # 3 and # 1 and # 2 match,
The output 521 of the priority lodge 520 becomes '1100', the output 531 of the comparator 530 becomes false and the VA0 and VA1 of the VAR 510 are reset at the next timing, and the read address counter 830 and the register 840 are reset.
Is set to the hold state. On the other hand, the bank busy check unit 130 checks the status of the bank corresponding to each address element, and the busy banks # 1, # 11, # 4,
# 6, # 2, # 14, # 10 (# 10 is unregistered at this point but is likely to be registered as a bank, so it is treated as busy) "0100" is output to the bank free indicator 880 . In response to the request, the request generation unit 140 sees that the address elements to be processed are # 0 and # 1 and the bank free indicator 880 is “0100”, and the memory request permission logic 610 sets the line 611 to false (the line 612 to true). ), And does not instruct the bank busy check unit 130 to register any bank address. On the other hand, when the write-back control unit 910 receives a report indicating that the memory request has been rejected by the line 612, it generates a strobe of pattern '1100', and the write address counter 930 of the list address buffer 120.
The address elements # 0 and # 1 are written to the address element part of address 1 which is the address designated by V.
Set 1. Next, for the remaining address elements in the same address element, VA0 to VA3 = '0011' and # 2
Since the memory port addresses of the address elements # 3 and # 3 are different, the output 521 of the priority logic 520 becomes "0011", the output 531 of the comparator 530 becomes true and the read address counter
The hold of the register 830 and the register 840 is released, and the end indicator 550 is turned on at the next timing. On the other hand, the bank busy checker 130 checks the status of the bank corresponding to each address element.
Both banks # 3 are busy, and '0000' is output to the bank free indicator 880. The request generation unit 140 receives these, and the address element to be processed is #
When the bank free indicator 880 is '0000' in # 2 and # 3, the memory request permission logic 610 sets the line 611 to false (612 to true), and the bank busy check unit 130 indicates to any bank address No registration is given. On the other hand, when the write-back control unit 910 receives a report indicating that the memory request has been rejected via the line 612, it generates a strobe of the pattern '0011' and instructs the write address counter 930 of the list address buffer 120. The address elements # 2 and # 3 are written in the address element part of address 1 which is an address, and V2 and V3 of the V bit part are set. Further, the write address counter 930 sets the output 631 of the request suppression history indicator 630 to true (there was a write-back process in the current address element word processing).
In addition, in response to the fact that the output 551 of the end indicator 550 is true (the current address element word processing has been completed), the count is incremented at the next timing in preparation for the next write-back processing. This completes the processing of the second address element word.

The processing of the first to third address element words has been described above, but these are pipelined and processed with time overlap. Thereafter, the subsequent address element words are processed in the same manner, but the read address counter 830 and the write address counter 930 circulate from address 15 to address 0, and the processing is continued until a memory request is made for all address elements. This situation is ninth
Shown in the figure. Table 6 shows the contents of the list address buffer 120 at this time.

[Effect of the Invention] As described above, according to the present invention, when accessing each address element of a list vector, the address information of each element is sequentially retrieved while being held in a buffer, and a bank corresponding to the address information can be accessed. It checks whether it is in the state, and if it is accessible, immediately accesses it; if it is not accessible, rewrites the address to the buffer, delays the access and moves to the processing of the address of the next element By repeating the operation, the buffer is reused, the buffer for saving the address at the time of the overtaking process becomes unnecessary, and the control sequence has almost no conditional branching. Is minimized, resulting in high list vector processing throughput Has the effect of being able to
Each element operation of address element reading, bank busy check, memory request (rewriting in the case of bank busy) can be pipelined very easily, and the throughput of list vector processing can be further improved over time. There is.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data processing device according to an embodiment of the present invention,
FIG. 2 shows the V of the list address buffer 120 of FIG.
FIG. 3 is a view showing a V-bit buffer capable of forming one bit width of a bit portion, and FIG. 3 is a V-bit buffer shown in FIG. 2, which is a flip-flop 1 bit used for storing V bits. FIG. 4 is a diagram showing a control signal for the V. minute portion, FIG. 4 is a diagram showing the V bit portion of the list address buffer 120 constructed using the V bit buffer of FIG. 2, and FIG.
FIG. 6 shows the execution control unit 900 in detail, FIG. 6 shows the request generation unit 140 in FIG. 1 in detail, and FIG. 7 shows the write address counter 930 in FIG. 1 in detail. ,
FIG. 8 is a diagram showing in detail the logical configuration of the write-back control unit 910 in FIG. 1, FIG. 9 is a time chart showing the operation of the present embodiment, and FIG. 10 is a schematic configuration of the data processing device of the present invention. Figure,
FIG. 11 is a flowchart of the control, FIG. 12 is a schematic configuration diagram of a conventional data processing apparatus, and FIG. 13 is a flowchart of the control. 110 Main memory 120 List address buffer 130 Bank busy checker 140 Request generator 210-225 Flip flop 230,240 Decoder 250 Selector 510 A stage V Bit register VAR 520: Priority logic 530: Comparator 540: Register receiving the output of priority logic 520 as it is at B stage 550: End indicator 610: Memory request permission logic 620: Memory request generation logic 630: Request suppress history indicator 800 to 807 Memory port 810 to 825 Bank 830 Read address counter 840,850,860 Register 870 Selector array 880 Bank free indicator 890 Request register 900 execution control unit 920 selector 930 write address counter

Claims (2)

(57) [Claims] 1. A storage means having a plurality of banks, and a plurality of entries each having a plurality of address storage units, wherein an access destination address of a plurality of memory access requests for the plurality of banks is stored in the entry of each of the entries. Address information holding means for holding in a plurality of address storage units; and a plurality of access destination addresses held in the plurality of address storage units of a first entry among the plurality of entries from the address information holding means. Checking means for simultaneously checking whether or not each of the banks specified by the read and read access destination addresses is accessible; and a plurality of access destinations of the entry based on the checking by the checking means. At least one of a plurality of memory access requests related to an address that can be transmitted to the plurality of banks. Selecting one of the memory access requests and sending the selected memory access request to the plurality of banks; and selecting at least one of the memory access requests that cannot be sent to the plurality of banks and suppressing transmission to the corresponding plurality of banks. Control means for controlling an access destination address of said at least one memory access request that cannot be transmitted to be held in a last entry of said address information holding means. 2. The address information holding means is provided in correspondence with each address storage section of each entry, and indicates whether each access destination address held in each address storage section of the entry is valid or not. A valid bit storage unit for storing a bit, wherein the control unit, when suppressing transmission of at least one memory access request to the plurality of banks, transfers the content of the entry to the last entry; Of the plurality of access destination addresses transferred to the last entry, the one whose transmission to the plurality of banks is suppressed is generated so that the valid bit is valid and stored in the corresponding valid bit storage unit, The inspection means performs an inspection based on the contents of a valid bit storage corresponding to each address storage of the entry read from the address information storage. The data processing apparatus according to claim 1, wherein a.