JP3169724B2 - Light valve device, method of manufacturing light valve device, and image projection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOS transistor in which at least a channel region is formed on a semiconductor thin film which is a single crystal semiconductor.
The present invention relates to a light valve device that uses a type transistor as a switching element, seals a liquid crystal layer between substrates, and operates by selectively supplying power to the liquid crystal layer by the switching element.

[0002]

2. Description of the Related Art Conventionally, as this type of light valve device, an active LCD in which an amorphous silicon thin film or a polycrystalline silicon thin film is deposited on a glass substrate to form a thin film transistor and perform a switching operation is known. Since this amorphous or polycrystalline silicon thin film can be easily deposited on a glass substrate by a chemical vapor deposition method, it is suitable for manufacturing an active matrix type light valve device having a relatively large area.

However, a conventional active matrix light valve device using an amorphous silicon thin film or a polycrystalline silicon thin film is suitable for a direct-view type display device requiring a relatively large area image surface, while having a transistor element. However, it is not necessarily suitable for miniaturization and high density.

In order to compensate for the disadvantages of the amorphous silicon thin film or the polycrystalline silicon thin film, recently, a single crystal semiconductor thin film layer is formed on an insulating carrier layer, and a MOS transistor is added to the single crystal semiconductor thin film layer. A light valve device formed to constitute a switching element has been proposed. For example, when a silicon single crystal semiconductor thin film layer is used as the single crystal semiconductor thin film layer, the amorphous silicon semiconductor film or the polycrystalline silicon Better than thin films.

FIG. 4 is a sectional view of a semiconductor composite substrate used for the light valve device, in which a single crystal semiconductor thin film layer is laminated on a carrier layer. In FIG. 4, a liquid crystal layer, an opposing substrate, a polarizing plate, and the like are omitted. In FIG. 4, a single crystal semiconductor thin film layer 25 and an interlayer separation region 32 as an insulator are formed on a carrier layer 29 as an insulator via an adhesive layer 30 and an insulator layer 31. A source region 21 and a drain region 22 are formed in the single crystal semiconductor thin film layer by impurity doping, and a gate insulating film 26 and a gate electrode 24 are formed on the single crystal semiconductor thin film layer to form a transistor element 20. ing. In the source region and the drain region, a drain electrode using both the source electrode 27 and the pixel electrode 28 is formed. Further, an insulating film 33 for flattening the surface is formed to form a semiconductor composite substrate. As the insulator layer 31, a silicon oxide film obtained by oxidizing silicon is usually used, and as the single crystal semiconductor thin film layer 25, a silicon single crystal is usually used.

[0006]

However, when the semiconductor substrate is configured as described above, the MOS transistor of a single crystal semiconductor does not occur in the MOS transistor of a polycrystalline or amorphous semiconductor. There is a problem that the current increases.

A main object of the present invention is to generate a parasitic channel near the interface between the above-mentioned single crystal semiconductor thin film layer and the insulating layer on the reflection side when irradiating the single crystal semiconductor thin film layer and to generate a MOS transistor. Bipolar action is prevented, and O
The purpose is to suppress the FF leak current.

[0008]

According to the present invention, a main means adopted to achieve the above object is a semiconductor thin film layer forming a MOS type transistor formed on a semiconductor composite substrate forming a light valve device. The impurity concentration in the channel formation region, which is a single crystal semiconductor, is lower than the impurity concentration in regions other than the channel formation region.

Another means adopted in order to achieve the above object of the present invention is that a parasitic channel or a bipolar action occurs even when the impurity concentration of a single crystal semiconductor thin film layer which is a MOS transistor forming layer is irradiated with light. The impurity concentration was made sufficiently high so that the threshold of the original channel was controlled by doping an impurity of the opposite conductivity type to the original channel formation region.

According to another aspect of the present invention, there is provided a single crystal semiconductor thin film layer having a source region and a drain region adjacent to a source region and a drain region below a channel forming region. A region with a high impurity concentration of the opposite conductivity type was provided. Thus, even if an inversion layer is formed near the interface between the insulator layer and the single crystal semiconductor thin film layer, no inversion layer is formed in the dense impurity concentration region adjacent to the source region and the drain region.

According to another aspect of the present invention, a gate electrode is a lower surface of an insulating layer on a reflection side with respect to a single-crystal semiconductor thin film layer.
An electrode is provided in a portion corresponding to a channel formation region of the S-type transistor so that a voltage can be supplied to the electrode.

Another means adopted in order to achieve the above object of the present invention is to provide a carrier recombination region other than a channel formation region of a single crystal semiconductor thin film layer so that a substrate potential can be maintained even during light irradiation. Change is suppressed.

[0013]

By adopting the above means, it is possible to prevent the occurrence or increase of OFF leak current due to the occurrence of a parasitic channel or a bipolar action during light irradiation, and to suppress the fluctuation of the threshold voltage of the MOS transistor. can do. As a result, the light valve device can be operated stably during light irradiation.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of the embodiments, the MO of a single crystal semiconductor
Since the mechanism of generating an OFF leak current due to light irradiation of the S-type transistor has been elucidated, an N-channel MOS transistor will be described in detail below as an example.

FIG. 5 shows an N channel M according to the presence or absence of light irradiation.
FIG. 3 is a schematic diagram showing a change in drain current-gate voltage characteristics of an OS transistor. If no light is applied, a
As described above, the OFF leakage current of the MOS transistor is extremely small and does not hinder the operation of the transistor.

However, when light is irradiated, MO is increased as shown by b.
The threshold voltage of the S-type transistor decreases, and the OFF leak current also increases. The decrease in the threshold voltage indicates that the potential of the internal region other than the channel region, the source region, and the drain region of the MOS transistor is increasing.

FIG. 6 is a schematic diagram of an energy band over a source region, an internal region, and a drain region of an N-channel MOS transistor in a state where light is not irradiated. This shows a state where a constant positive voltage is applied to the drain region 803. When light is applied to the transistor in this state, a large number of electrons and holes are generated mainly in the depletion layer region 804 by light energy. The amount of these generations increases according to the illuminance of the received light. According to the experiment of the present inventors, the relationship between the illuminance (lx) of white light and the OFF leak current of the MOS transistor is linear (proportional).

Among the generated electrons and holes, the electrons enter the drain region 803 and the source region 801 according to the gradient of the energy band, but the holes accumulate in the internal region 802. Then, the potential of the internal region 802 rises, and an energy band structure as shown in FIG. 7 is obtained.

The threshold voltage of the N-channel MOS transistor decreases due to the rise in the potential of internal region 802.
In addition, in the embodiment of the light valve device according to the present invention shown in FIGS. 1 to 3, a parasitic channel is easily generated in the vicinity of the interface between the internal region 120 and the base insulating film 102.

Further, when the potential of the internal region 802 rises, a bipolar action triggered by light irradiation that a large amount of electrons flow from the source region 801 to the drain region 803 occurs. This bipolar action occurs when electrons diffuse from the source region 801 to the internal region 802 and reach the drain region 803, so that the diffused source region 801 and the drain region 803 are diffused.
The shorter the distance is, the easier the electrons survive.

This phenomenon is peculiar to a single crystal semiconductor MOS transistor, and occurs because the crystallinity of the internal region 802 is excellent. In a polycrystalline or amorphous semiconductor MOS transistor, electrons are transferred to the inner region 802.
This phenomenon does not occur because they recombine and dissipate easily within. With the above mechanism, OFF leakage current of a single crystal semiconductor MOS transistor is increased by light irradiation. As described above, the N-channel MOS type transistor has been described as an example. In the case of the P-channel MOS type transistor, the potential of the internal region is decreased by light irradiation, and the point where holes flow as carriers is opposite to the case of the N-channel type. Yes, OFF leakage increases by a similar mechanism.

Further, a MOS of a single crystal semiconductor by light irradiation
It has been clarified that the OFF leak current of the type transistor is related to the thickness of the semiconductor layer forming the MOS type transistor, and will be described below. As an example, the graph shows the relationship between the OFF leak current and the semiconductor layer thickness during light irradiation of an N-channel MOS transistor having a channel length of 2 μm and a channel width of 20 μm when the semiconductor layer forming the MOS transistor is a single crystal. FIG.

As shown in FIG.
In a region of 3 μm or more, an OFF leak current is generated by light irradiation.
It can be seen that the value of the leak current sharply increases. on the other hand,
When the thickness of the semiconductor layer is 0.3 μm or less, light penetrates the semiconductor layer and does not give sufficient energy to generate carriers. Therefore, an increase in OFF leak current of the MOS transistor due to light irradiation does not occur. .

According to the mechanism of the increase in the OFF leak current of the MOS transistor due to the light irradiation described above, in order to suppress the increase in the OFF leak current during the light irradiation, it is necessary to reduce the thickness of the semiconductor layer, Preventing potential fluctuations in the internal region 802 of the transistor shown,
Alternatively, it has been found that it is important to form a MOS transistor structure that does not cause a parasitic channel or a bipolar action even when the potential fluctuates.

For this purpose, the thickness of the semiconductor layer constituting the MOS transistor is reduced to 0.3 μm or less, an electrode is provided on the back surface of the internal region via an insulating layer, and carriers generated by light irradiation are immediately removed. Even if the potential of the internal region fluctuates by providing a region to be recombined and disappearing, and setting the impurity concentration in the internal region to be high,
An effective means is to have a sufficiently high parasitic channel with a good value voltage and to secure a potential barrier between the source region and the internal region.

Next, an embodiment of the light valve device according to the present invention will be described. FIG. 1 shows a schematic sectional view of a light valve device according to the present invention. This light valve device emits light from below or above and is used as an optical shutter. In FIG. 1, a base insulating film 102 is bonded to a support substrate 101 as a support via an adhesive layer 103. On the base insulating film 102, a MOS transistor device 100 and a device isolation insulating film 104 each composed of a single crystal semiconductor thin film layer are formed. The MOS transistor includes a source region 105, a drain region 106, and a channel formation region 107 which are formed in a single crystal semiconductor thin film 108. Further, a gate electrode 110 is formed on the channel formation region via a gate insulating film 109. Be composed. Source area 10
5 is electrically connected to the wiring electrode 111 via a contact hole formed in the intermediate insulating film 119. Further, the wiring electrode 111 is formed to have a function of a light-shielding film so as to block light incident on the single crystal semiconductor thin film layer 108. A drive electrode 112 for driving an electro-optical material such as a liquid crystal material is formed on the element isolation insulating film 104. The drive electrode 112 is electrically connected to the drain region 106 formed on the single crystal semiconductor thin film. The MOS transistor element 100 and the driving electrode 1
When a liquid crystal is used as an electro-optical material, an alignment film 114 for aligning liquid crystal molecules is formed. A counter electrode 116 for supplying a voltage to the electro-optic material is formed on the surface of the counter substrate 115, and an alignment film 117 is further formed thereon.

Then, the composite substrate on which the MOS transistor is formed and the opposing substrate are bonded together with a gap therebetween, and an electro-optical material layer 118 made of, for example, a liquid crystal material is sealed in the gap. Be composed. FIG. 2 shows another schematic sectional view of the light valve device according to the present invention.

In FIG. 2, a MOS transistor element 1 comprising a single-crystal semiconductor thin film layer on a base insulating film 102
00 and an element isolation insulating film 104 are formed. The MOS transistor includes a source region 105, a drain region 106, and a channel formation region 107 which are formed in a single crystal semiconductor thin film 108. Further, a gate electrode 110 is formed on the channel formation region via a gate insulating film 109. Be composed. The source region 105 includes the wiring 111 and the intermediate insulating film 1.
19 are electrically connected via a contact hole opened. Further, the wiring 111 has a single crystal semiconductor thin film layer 108.
It is formed so as to also have a function of a light-shielding film so as to block light incident on the light source. A drive electrode 112 for driving an electro-optical material such as a liquid crystal material is formed on the element isolation insulating film 104. The drive electrode 112 is electrically connected to the drain region 106 formed on the single crystal semiconductor thin film. The MOS transistor element 100
A protective film 113 is formed on the drive electrode 112 or the intermediate insulating film 119, and is bonded to a support substrate 101 as a support via an adhesive layer 103. The base insulating film 102
A light shielding film 13 is formed on the lower surface of the MOS transistor element so as to prevent light from entering at least the channel region 107 of the MOS transistor element.
0 is formed. When a liquid crystal is used as the electro-optic material, the lower insulating film 102 and the lower surface of the light shielding film 103
An alignment film 114 for liquid crystal molecule alignment is formed. A counter electrode 116 for supplying a voltage to the electro-optic material 118 is formed on the surface of the counter substrate 115, and an alignment film 117 is further formed thereon.

Then, the base insulating film side of the composite substrate on which the MOS transistor is formed and the counter substrate are bonded to each other with a gap provided therebetween, and the gap is filled with an electro-optical material layer 118 made of, for example, a liquid crystal material. Thus, a light valve device is configured. FIG. 3 shows another schematic sectional view of the light valve device according to the present invention.

FIG. 3 is different from FIG.
The element isolation of the type transistor is performed using the single crystal semiconductor thin film 10.
8 is removed by etching, the distance between the drive electrode 112 and the electro-optical material 118 is shorter than in the example of FIG. 2, and the electro-optical material can be driven at a lower voltage. Others are the same as FIG. Normally, liquid crystal is used in this type of light valve device. In this case, a polarizing plate is provided outside the counter substrate 115 and the support substrate 101 so that light entering and exiting the light valve device can be visualized. However, they are omitted in FIGS. 1 to 3. This embodiment, FIG.
In the MOS transistor shown in FIG. 3, the impurity concentration of the channel formation region 107 of the single crystal semiconductor thin film layer 108 is different from that of the conventional MOS transistor in the internal region 120 other than the source region 105 and the drain region 106.
It is set so that the density becomes lower than that.

In other words, since the impurity concentration of the internal region 120 is high, even when the potential of the internal region 120 is changed by carriers generated by light, a parasitic channel hardly occurs. The source region 105 and the internal region 1
Since the height of the potential barrier with respect to 20 is higher than that of a MOS transistor having a conventional structure, bipolar action hardly occurs. Furthermore, since the lifetime of the carrier in the inner region 120 is also shortened, the bipolar action is less likely to occur.

FIG. 9 is a schematic cross-sectional view for explaining the MOS transistor element portion used in the light valve device of FIGS. 1 to 3 more specifically. It is drawn. In FIG. 9, the base insulating film 1
02 is a silicon oxide film. Single crystal semiconductor thin film layer 10
8 is a silicon single crystal. In other words, the MOS transistors shown in FIGS.
(Hereinafter referred to as SOI) type MOS transistor. This MOS transistor is also shown in FIGS.
Similarly, the impurity concentration of the channel formation region 107 is set lower than that of the internal region 120.

More specifically, in forming an N-channel MOS transistor, the single-crystal semiconductor thin film 10
In FIG. 8, an impurity of a conductivity type opposite to that of the source and drain regions, for example, boron is introduced at a high concentration. Then, the impurities are diffused by a method such as heat treatment. For example, when silicon single crystal is used as the single crystal semiconductor thin film 108 and boron is used as a P-type impurity, boron in the silicon single crystal at the interface between the silicon single crystal and the silicon oxide film serving as the base insulating film 102 is It has the property of extremely decreasing. Due to the decrease of the P-type impurities, the silicon single crystal thin film 108 near the interface of the base insulating film 102 is formed.
Are inverted, and a parasitic channel is more likely to be induced during light irradiation. In order to prevent the parasitic channel formed at this low voltage and to prevent the bipolar action,
As described above, high-concentration impurities are introduced into single-crystal silicon in advance. Then, impurities of the same conductivity type as the source and drain regions are further added to the channel forming region 1.
The surface of the silicon single-crystal thin film 108 containing 07 is counter-doped. Thus, the channel formation region 107
Is set to have a lower concentration than the internal region 120.

Further, in some cases, the channel region 1
07 may be of the same conductivity type as the source and drain regions.
As another method, if the implantation energy is appropriately set by ion implantation and boron ions are implanted deeply so that the internal region 120 has a sufficiently high impurity concentration distribution as compared with the channel formation region 107, It is also possible to omit the counter doping step.

FIG. 10 is a schematic sectional view showing another embodiment of the composite substrate used in the light valve device according to the present invention shown in FIGS. In FIG. 10, the components are denoted by the same reference numerals as in FIG. The difference from the embodiment of FIG. 9 is that the source region 105 and the drain region 106 are in contact with the base insulating film 102 made of, for example, a silicon oxide film. With such a structure, the parasitic capacitance formed in the source region and the drain region can be reduced, so that the operation speed of the transistor element can be improved. The structure of the other parts is shown in FIG.
This is the same as the embodiment.

FIGS. 11A and 11B are schematic sectional views showing another embodiment of the composite substrate used in the light valve device according to the present invention. In particular, the structure of the element isolation region of the MOS transistor is shown. Is specified. FIG. 11A shows an example in which an element isolation region 130 is formed by etching and removing a single crystal semiconductor thin film layer 108 as a device formation layer, and FIG. An element isolation region 131 made of a silicon oxide film using a single crystal and selectively disposing the element isolation region.
Are shown below. Other parts are the same as those in the embodiment of FIG.

As described in the above embodiment, the impurity concentration of the channel forming region of the SOI type MOS transistor formed on the base insulating film is set lower than the impurity concentration of the internal region. In this case, the occurrence of a parasitic channel or a bipolar action can be prevented, and a stable transistor operation can be achieved.

FIG. 12D is a schematic sectional view showing another embodiment of the N-channel MOS transistor on the composite substrate used in the light valve device according to the present invention.
12A to 12D show the manufacturing method in the order of steps. As shown in FIG. 12D, an NMOS transistor is formed in a device formation layer 212 made of a P-type semiconductor, which is a first conductivity type, on a silicon oxide film 202 constituting an insulating plate base. The source region 208 and the drain region 209 are made of an n-type impurity layer of the second conductivity type, and are respectively connected to the silicon oxide film 202. The device forming layer inner region 210 has a sufficient concentration (for example, 1 × 10 ¹⁷⁾ to prevent the occurrence of a parasitic channel at the junction 213 between the device forming layer inner region 210 and the silicon oxide film 202.
cm ⁻³ ) of P-type impurities are introduced. Source region 208 and drain region 209 on the surface of the device formation layer
Since the threshold value of the NMOS transistor rises as the impurity concentration of the device forming layer internal region 210 increases, the channel region 206 formed between the P-type regions of the effective channel region 206 increases the threshold value. In order to lower the impurity concentration of n, an n-type impurity is introduced. In some cases, the channel region 206 may be thin N-type.

In the NMOS transistor according to the present application, since the impurity concentration is high in the device forming layer internal region 210 other than the channel region 206, the junction capacitance between the source region 208 and the drain region 209 and the device forming layer internal region 210 is increased. Source region 2
08 and the bottom of the drain region 209 are each joined to the silicon oxide film 202, so that the junction capacitance does not increase as the impurity concentration is increased in a normal semiconductor substrate, so that the operation speed of the transistor hardly decreases.

Next, a method of manufacturing an NMOS transistor according to the present invention will be described. As shown in FIG. 12A, a single crystal silicon device forming layer 203 having a thickness of 1 μm or less on a supporting substrate 201 via a silicon oxide film 202 forming an insulator substrate and forming a semiconductor substrate is provided. An SOI substrate is prepared, and boron or the like is formed to have an impurity concentration (for example, 1 × 10 ¹⁷ cm ⁻³ ) sufficient to prevent generation of a parasitic channel in a single crystal silicon device formation layer 203 where an N-channel transistor is formed. After introducing the P-type impurity by ion implantation or the like, diffusion and activation are performed. Here, heat treatment is performed so that the P-type impurity concentration is substantially uniformly distributed in the single crystal silicon device formation layer 203. When boron is heat-treated in an oxidizing atmosphere, the concentration of boron is reduced at the interface between the single crystal silicon device layer 203 and the silicon oxide film 202 due to segregation.
Heat treatment in a nitrogen atmosphere is preferred.

Next, as shown in FIG. 12B, the single crystal silicon device forming layer 203 is removed by etching while leaving the transistor forming region 204, and each transistor is separated. Although not shown, element isolation between transistors may be performed by a LOCOS method or the like. The above-described introduction of the P-type impurity may be performed after the element isolation shown in FIG.

Next, as shown in FIG. 12C, the gate insulating film 205 of the MOS transistor is formed by thermal oxidation or CVD.
After the formation by the method, ion implantation for threshold control with N-type impurities is performed on the surface portion of the region into which the P-type impurity is introduced, and the P-type impurity concentration is effectively reduced on the surface portion of the transistor formation region 204. The formed channel region 206 is formed. As the N-type impurity, arsenic may have a small diffusion coefficient, but phosphorus or antimony may be used in some cases.

Next, as shown in FIG. 12D, a gate electrode 207 is formed by a normal IC process, and a channel region 20 under the gate electrode 207 doped with an N-type impurity is formed.
An N-channel MOS transistor is completed by forming the source region 208 and the drain region 209 sandwiching 6 by an ion implantation method or the like so as to be joined to the silicon oxide film 202.

FIG. 13 is a schematic sectional view showing another embodiment of the method of manufacturing a semiconductor device according to the present invention. After the steps of FIGS. 12A and 12B, an N-type impurity-containing layer 211 is formed by N-type impurity pre-deposition or molecular layer doping technique as shown in FIG. Step 206 is formed. Thereafter, although not shown, the N-type impurity-containing layer 211 is removed, a gate insulating film 205 is formed, and as shown in FIG.
An N-channel MOS transistor is formed by a C process.

The N-channel MOS transistor has been described above as an example. However, the present invention can be applied to a P-channel MOS by reversing the conductivity type. As described with reference to FIGS. 12 and 13, which are the embodiments of the present invention, the channel region of the MOS transistor formed in the first conductivity type silicon device formation layer of the SOI substrate has the opposite conductivity type to the silicon device layer. By doping the second conductivity type impurity, the first conductivity type impurity concentration in the channel region is effectively lower than the first conductivity type impurity concentration in the transistor internal region. Since the first conductivity type impurity concentration is set high so as not to be easily inverted, it is possible to prevent the occurrence of a parasitic channel and a bipolar action even during light irradiation. That is, according to these embodiments, it is possible to obtain a MOS transistor capable of arbitrarily controlling the threshold value and having a small OFF leak current during light irradiation. In addition, since this MOS transistor can be manufactured by an ordinary IC process without using any special device, the manufacturing method is simple and excellent in mass productivity. By using the composite substrate on which the MOS transistor manufactured in this manner is formed in the light valve device described with reference to FIGS. 1 to 3, it is possible to prevent the occurrence of a parasitic channel even in a state where light is irradiated, The light valve device can be driven stably.

As described above, since the source region and the drain region of the MOS transistor described with reference to FIGS. 9 to 13 are in contact with the internal resistance having a high impurity concentration, there is a possibility that problems such as a reduction in junction breakdown voltage and generation of hot carriers may occur. . To prevent this, although not shown, it is effective to adopt a so-called LDD or DDD structure in which a thin impurity concentration region of the same conductivity type as the drain region is provided at least between the drain region and the internal region. .

FIG. 14 is a schematic cross-sectional view showing another embodiment of a MOS transistor on a composite substrate used in the light valve device according to the present invention, wherein a high impurity concentration region is formed by a base insulating film and a source region. And an embodiment formed between drain regions. Also in this embodiment, FIG.
As in the case of FIG. 13, a silicon substrate is used as a single crystal semiconductor and a silicon oxide film is used as a base insulating film.

As shown in FIG. 14, a silicon substrate 301
In a MOS transistor formed over a base insulating film 302 which is an upper silicon oxide film, a channel forming region 306 is provided between a source region 303 and a drain region 304 below a gate electrode 305 via a gate insulating film 308. Element isolation from an adjacent transistor is performed by an element isolation region 310 made of a silicon oxide film. Then, in the internal region 307 below the channel region 306, the source region 30 is formed.
3 and the drain region 304, respectively.
A high impurity concentration region 309 of the opposite conductivity type to the drain region is formed. The source / drain region and the impurity concentration region 309 of the opposite conductivity type are formed by an ion implantation method or the like before forming the source / drain region during the IC manufacturing process.

FIG. 15 is a schematic sectional view showing another embodiment of the composite substrate for a light valve device according to the present invention. The difference from the example shown in FIG. 14 is that a high breakdown voltage structure called an LDD or DDD structure is adopted. As shown in FIG. 14, the high impurity concentration region 309 and the source region 30
3 and the drain region 304 are in contact with each other, the junction breakdown voltage is reduced.
4, a thin impurity concentration region 311 of the same conductivity type as the source and drain regions is formed to improve the breakdown voltage. As a general manufacturing method, after forming the gate electrode 305,
A thin impurity concentration region 311 of the same conductivity type as the source and drain regions is formed by ion implantation, a side spacer 312 made of an insulating film is formed, and a source region 313 and a drain region 304 are formed again by ion implantation.
The other parts are denoted by the same reference numerals as in FIG. 14 and will not be described.

According to the embodiment shown in FIGS.
In the transistor, a deep impurity concentration region having a conductivity type opposite to that of the source and drain regions is provided below the channel region adjacent to the source and drain regions. Even if an inversion layer is formed near the interface of the base insulating film when a gate voltage lower than the normal threshold is applied by light irradiation, the inversion layer is blocked by the source and drain regions and the impurity concentration region of the opposite conductivity type and has a high impurity concentration. Since no contact is made with the drain region, a substantial parasitic channel does not occur. Also, due to the high impurity concentration region,
Carriers are easy to recombine and bipolar actions are unlikely. Although not shown, element isolation from an adjacent transistor may be performed by removing silicon instead of a silicon oxide film.

As described above, in this embodiment, FIGS.
According to this, in the MOS transistor, the source and drain regions are provided adjacent to the source and drain regions below the channel region, and the impurity concentration region of the opposite conductivity type is provided at a lower portion. Therefore, an inversion layer is formed near the interface of the base insulating film. However, since it is separated from the source and drain regions, the occurrence of a parasitic channel or a bipolar action can be substantially prevented even during light irradiation, and stable operation can be achieved even when used in a light valve device. it can.

FIG. 16 is a schematic sectional view showing another embodiment of the MOS type transistor on the composite substrate used in the light valve device according to the present invention shown in FIG. An example is shown in which an electrode is formed on the surface of the base insulating film opposite to the single crystal semiconductor thin film layer in order to suppress the OFF leakage current of the transistor. Hereinafter, the present embodiment will be described using an NMOS transistor and a PMOS transistor. The NMOS and PMOS transistors are configured in an integrated circuit section formed around the composite substrate of the light valve device. The integrated circuit drives a matrix array section that performs a display operation by controlling the amount of transmitted light. Device forming layer 4 on base insulating film 401
10, N is separated from each other by a selective oxide film 102.
MOS transistor 403 and PMOS transistor 40
4 are formed. Although not shown, each element is connected by wiring to form an integrated circuit. Under the portion between the source and the drain of the NMOS transistor 403 and the PMOS transistor 404, independent electrodes 405 and 406 are formed via a buried insulating film 401, respectively.

FIG. 17 is a schematic sectional view showing another embodiment of the composite substrate used in the light valve device according to the present invention shown in FIG. The difference from the example shown in FIG. 16 is that the element isolation region 414 where the device formation layer 410 is etched away.
This is the point that is performed. Element isolation by etching is advantageous in terms of fine processing as compared with a method using a selective oxide film. The other parts are denoted by the same reference numerals as in FIG. 12 and will not be described.

According to the embodiment of FIGS. 16 and 17, the NMO
Under the underlying insulating film 401 under the S transistor 403 and the PMOS transistor 404, independent electrodes 40 are provided respectively.
5, 406 can be applied, for example, -20 V can be applied to the NMOS side and +20 V can be applied to the PMOS side. This makes it possible to reduce potential fluctuations between the source and the drain even during light irradiation. This can prevent the occurrence of the parasitic channel and the bipolar action. In FIGS. 16 and 17, the electrode 405 and the electrode 406 are independent from each other. However, by making use of the fact that the back channel is less likely to be formed in the PMOS, the electrodes are made common and the common potential is set. , -5V to -10V can be applied to prevent the occurrence of a parasitic channel.

Therefore, the operation of the whole integrated circuit becomes extremely stable and accurate. In the light valve device shown in FIGS. 2 and 3, the light-shielding film 130 under the MOS transistor element 100 is formed of a conductive material such as aluminum or chromium, and by applying a voltage as described above,
It is possible to effectively prevent the occurrence of the OFF leak current of the MOS transistor element 100 in the matrix array section.

In the embodiment shown in FIGS. 16 and 17, the effect is greater as the thickness of the buried insulating film 401 is smaller. The reason will be described below. FIG. 18 is a schematic diagram showing the relationship between the threshold voltage variation ΔV _TH of a MOS transistor and the substrate potential using the thickness of the gate insulating film as a parameter.

As shown in FIG. 18, the threshold voltage variation ΔV _{TH with} respect to the change in the substrate potential is larger when the gate insulating film is thicker than when it is thin. In other words, the case where the thickness of the gate insulating film is large is more susceptible to threshold voltage fluctuation due to a change in substrate potential.

In FIG. 16 and FIG.
If 01 is a gate insulating film and electrodes 405 and 406 are gate electrodes, they can be regarded as one MOS transistor. Here, by setting the thickness of the buried insulating film 401 to be thinner, preferably equal to or less than the thickness of the gate insulating film 420, the potential between the source and the drain is kept constant even during light irradiation. This is effective in suppressing the OFF leak current of the transistor.

FIGS. 19A to 19D are cross-sectional views in the order of steps of a method for manufacturing a composite substrate according to the embodiment of FIG. As shown in FIG. 19A, an integrated circuit including an NMOS transistor 403 and a PMOS transistor 404 is formed using a normal IC process, and a protective film 412 is deposited on the integrated circuit.

Next, as shown in FIG. 19B, a support substrate 421 is bonded via an adhesive layer 413. Here, if the adhesive layer 413 and the support substrate 421 are made of a transparent material, it can be applied to a light transmission type device, for example, a composite substrate for a light valve. Next, as shown in FIG. 19C, the silicon support substrate 420 of SOI is removed by etching. This etching is performed by using a KOH solution or a hydrazine solution as an etchant, and stops when the base insulating film 401 is exposed.

Prior to the etching, the silicon support substrate 420 may be thinned beforehand by polishing or the like. Next, as shown in FIG. 19D, independent electrodes 405 and 406 are formed under the base insulating film 401 below the NMOS transistor 403 and the PMOS transistor 404, respectively.
To form The electrodes 405 and 406 are made of, for example, a metal material such as aluminum or chromium. The electrodes 405 and 406 are formed by removing unnecessary portions by etching after being deposited by a sputtering method or the like. Thus, the composite substrate shown in FIG. 17 is completed.

As described above, FIG. 19A to FIG.
When the liquid crystal cell assembling step is added to the step shown in (d), the light valve device shown in FIG. 3 can be formed. FIG. 2
19 is formed by adding a liquid crystal cell assembling step to the same steps as those shown in FIGS. 19 (a) to 19 (d) except for the element isolation method. be able to.

As described above, according to the present invention, in a MOS type integrated circuit on an SOI substrate, an electrode is provided under a base insulating film so that a voltage can be supplied. Even during light irradiation, formation of an inversion layer near the interface with the base insulating film, that is, occurrence of a back channel or a bipolar action can be prevented, and an integrated circuit that operates stably can be manufactured.

FIGS. 20A to 20D are cross-sectional views in the order of steps of a method of manufacturing the light valve device according to the embodiment of FIG. FIGS. 20A to 20D illustrate a case where the first support substrate 101 is made of silicon.

First, as shown in FIG. 20A, a so-called SOI substrate having a single crystal semiconductor thin film layer 603 is prepared on a first support substrate 601 with a base insulating film 602 interposed therebetween. An SOI substrate is formed by forming an insulating film on at least one of two single crystal application substrates, bonding them together so as to sandwich the insulating film, and then thinning one of the single crystal silicon substrates to a required thickness. Bonding (Bondin
g) The wafer is preferable because it has better crystallinity than an SOI substrate formed by a SIMOX method or a recrystallization method.

Next, as shown in FIG. 20B, a light valve element including a MOS transistor, a drive electrode 609, a wiring 611, and the like is formed using a normal IC process. Here, the case where an N-channel MOS transistor is provided will be described. First, the single crystal semiconductor thin film layer 60
In FIG. 3, a P-type impurity such as boron is introduced by ion implantation so as to have a concentration (for example, 1 × 10 ¹⁷ cm ⁻³ ) sufficient to prevent a parasitic channel, and then diffused and activated. Here, heat treatment is performed so that the P-type impurity has a substantially uniform concentration distribution in the single crystal semiconductor thin film layer 603. When boron is used as a P-type impurity, the heat treatment is performed in an oxidizing atmosphere, the impurity concentration decreases due to segregation near the interface between the single crystal semiconductor thin film layer 603 and the base insulating film. Is preferred.

Next, the single crystal semiconductor thin film layer 603 other than the transistor formation region is removed by etching, and each transistor is separated. This element separation is performed by the single crystal semiconductor thin film layer 6.
The LOCOS method performed by oxidizing 03 may be used. In this case, the light valve device according to the embodiment shown in FIG. 2 is finally obtained.

Next, after the gate insulating film 608 is formed by a thermal oxidation method or a CVD method, the single crystal semiconductor thin film layer 603 is formed.
N-type impurities are introduced into the vicinity of the surface by ion implantation, molecular layer doping, or pre-deposition, and the threshold voltage is controlled. Channel region 604 reduced to
To form In some cases, the channel region 604 may be a thin N-type. As the N-type impurity, arsenic is preferable because of its small thermal diffusion coefficient, but phosphorus or antimony may be used in some cases. If the ion implantation energy and diffusion conditions are appropriately set so that the above-mentioned P-type impurity is high in the internal region of the single-crystal semiconductor thin film layer 603 and low in the channel region 604, the channel region 604 by the introduction of the N-type impurity is formed. Can be omitted. Subsequently, a gate electrode 607 made of polysilicon or the like is used.
Is formed on the gate insulating film 608 in a predetermined shape, and the source region 605 and the drain region 606 are formed by ion implantation of N-type impurities or the like so as to sandwich the channel region 604 below the gate electrode 607.

A drive electrode 609 is provided on the drain region 606 of the N-channel MOS transistor thus formed.
The source region 605 is formed so as to be connected to the wiring 611 which also serves as a light shielding of the MOS transistor, and the whole is formed with the protective film
2 to form a light valve element.

Next, as shown in FIG.
An adhesive layer 613 which also serves as a flattening is applied on
Is bonded. Here, the adhesive layer 613
When the second support substrate 614 is made of a transparent material, a composite substrate for a light transmission type light valve device can be formed. Subsequently, the first support substrate 601 (here, silicon) is removed. For the removal, etching using a KOH solution or a hydrazine solution as an etchant may be used, polishing may be performed, or a combination thereof may be performed. According to the etching, the base insulating film 6 made of SiO ₂ , SiN, etc.
This is convenient because the progress stops when 02 is exposed.

Next, a light-shielding film 615 is formed on the exposed underlying insulating film 602 as shown in FIG. 20D so as to cover at least the channel region 604 of the MOS transistor region formed in FIG. . This light shielding film 61
The reference numeral 5 may be omitted when light is irradiated and used at a level that does not hinder the operation of the MOS transistor in actual use.
Further, it is formed of a conductive material such as Al, Cr, etc.
It is also possible to apply a required voltage as described in the example shown in FIG. Subsequently, the electro-optic material 61
When the liquid crystal 7 is liquid crystal, an alignment film made of polyimide or the like is formed on the base insulating film 602 and the light-shielding film 615.

On the other hand, a counter electrode 618 is formed on the surface of the counter substrate 619, and an alignment film 617 is further formed thereon. After the alignment film 617 is provided with an alignment function by a rubbing process or the like, a substrate having a light valve element and an opposing substrate are bonded to each other with a predetermined gap, and an electro-optical material layer made of, for example, a liquid crystal material is provided in the gap. 617 is sealed, and the light valve device shown in FIG. 3 is completed.

Although not shown, after FIG.
A third support substrate made of a transparent material is bonded under the base insulating film 602 via an adhesive layer, and the second support substrate shown in FIG.
After the support substrate 614 and the adhesive layer 613 are removed and the protective film 612 is flattened, an alignment film is formed on the protective film 612 and alignment processing is performed. When a predetermined gap is provided to the opposing substrate and bonded to each other, and an electro-optical material layer made of liquid crystal or the like is sealed in the gap, a light valve device substantially equivalent to FIG. 1 is completed. In this case, the second support substrate 614 and the adhesive layer 613 need not be made of a transparent material. In this case, the difference from the example of FIG.
The element isolation method between the transistors is performed by removing the single crystal semiconductor thin film layer instead of the LOCOS method of FIG. 1. In the IC process shown in FIG. Then, the light valve device equivalent to FIG. 1 is completed.

FIG. 21 is a schematic sectional view showing another embodiment of the MOS transistor in the light valve device according to the present invention. The MOS transistor 710 on the semiconductor thin film layer 701 on the base insulating film 702 has a source region 70
3, degree region 704, gate insulating film 708, gate electrode 7
05 and a channel region 706 made of a single crystal semiconductor are formed.

Further, a carrier recombination region 709 into which a lifetime killer is introduced is formed in an internal region other than the source region 703, the drain region 704 and the channel region 706 of the semiconductor thin film layer 701. Even when light is applied to the MOS transistor shown in FIG. 21 to generate electrons and holes, the generated electrons and holes recombine and disappear here because the carrier recombination region 709 exists. Therefore, the potential change in the internal region due to the light irradiation does not occur, and the occurrence of the parasitic channel and the bipolar action is effectively prevented, and the increase in the OFF leak current of the transistor is suppressed.

Lifetime killers include Si, Au
It is preferable to introduce an element such as an ion by an ion implantation method or the like. Also, S
It is also effective to form the carrier recombination region 709 which has been broken into polycrystal or amorphous by ion implantation of i or the like. The carrier recombination region is
In order to reduce the junction leakage current, preferably, the source region 7
03, the drain region 704 and the channel region 706 are preferably formed in an internal region. However, in actuality, there are advantages such as simplification of a manufacturing process, and the junction leakage current is a problem in use of the device. In the case where the source region 703 and the drain region 704 are not provided, a part or all of the source region 703 and the drain region 704 may be formed.

FIGS. 22A to 22D are cross-sectional views in the order of steps of a method of manufacturing the light valve device including the MOS transistor shown in FIG. FIGS. 22A to 22D illustrate a case where the first support substrate 901 is silicon.

First, as shown in FIG. 22A, an SOI substrate having a single crystal semiconductor thin film layer 903 is prepared over a first supporting substrate 901 with a base insulating film 902 interposed therebetween. SO
The I substrate is preferably formed by the “lamination method” described with reference to FIG.

Next, as shown in FIG. 22B, a light valve element including a MOS transistor, a driving electrode 909, a wiring 911 and the like is formed by using a normal IC process. First, a lifetime killer atom such as gold or silicon is introduced by ion implantation or the like into an internal region of the single crystal semiconductor thin film layer 903 except for a surface side to be a channel region 904 later. Alternatively, by ion implantation of silicon or the like,
The carrier recombination region 920 is formed by destroying the crystallinity of the internal region and making the internal region polycrystalline or amorphous.

Next, the single crystal semiconductor thin film layer 903 other than the transistor formation region is removed by etching, and each transistor is separated. This element isolation step may be performed by a LOCOS method performed by oxidizing the single crystal semiconductor thin film layer 903.
Next, a gate insulating film 908 is formed by a thermal oxidation method or the like, and an impurity for controlling a threshold voltage of the transistor is introduced by an ion implantation method or the like, so that a channel region 904 is formed. continue,
A gate electrode 907 made of polysilicon or the like is formed on the gate insulating film 908 in a predetermined shape, and the source region 905 is sandwiched between the channel region 904 below the gate electrode 907.
And a drain region 906 is formed by an ion implantation method or the like.

Here, the above-described step of forming the region for carrier recombination may be performed after the element separation step. In the above-described manufacturing method, the source region 905 and the drain region 90
When 6 is formed deeply, it overlaps with the carrier recombination region 920. From the viewpoint of device characteristics, the source region 905 and the drain region 906 are preferably formed to be equal to or less than the channel region 904 so as not to overlap the carrier recombination region 920.

Although not shown, a polycrystalline silicon or amorphous silicon layer is formed between the base insulating film 902 and the single crystal semiconductor thin film layer 903 in the manufacturing process of the SOI substrate shown in FIG. By introducing a lifetime killer or the like, a layer serving as the carrier recombination region 920 is formed in advance, and the single crystal semiconductor thin film layer 903 is formed.
Is formed so as to have the same thickness as that of the channel region 904, it is not necessary to newly form the carrier recombination region 920 in the IC process.

The drive electrode 909 is connected to the drain region 906 of the NMOS transistor thus formed, and the wiring 911 also serving as a light-shielding function of the MOS transistor is connected to the source region 905.
2 to form a light valve element.

Next, as shown in FIG.
12 is coated with an adhesive layer 913 which also serves as a flattening,
Is bonded. Here, the adhesive layer 913
When the second support substrate 914 is made of a transparent material, a composite substrate for a light transmission type light valve device can be formed. Subsequently, the first support substrate 901 (here, silicon) is removed. For the removal, etching using a KOH solution or hydrazine solution as an etchant may be used, polishing may be performed, or a combination thereof may be performed. According to the etching, the progress is stopped when the base insulating film 902 made of SiO ₂ , SiN or the like is exposed, which is convenient.

Next, a light-shielding film 915 is formed on the exposed underlying insulating film 902 as shown in FIG. 22D so as to cover at least the channel region 904 of the MOS transistor region formed in FIG. 22B. . This light shielding film 91
The reference numeral 5 may be omitted when light is irradiated and used at a level that does not hinder the operation of the MOS transistor in actual use.
Further, it is formed of a conductive material such as Al, Cr, etc.
It is also possible to apply a required voltage as described in the example shown in FIG. Subsequently, the electro-optic material 91
When the liquid crystal 7 is a liquid crystal, an alignment film made of polyimide or the like is formed on the base insulating film 902 and the light-shielding film 915.

On the other hand, a counter electrode 918 is formed on the surface of the counter substrate 919, and an alignment film 916 is further formed thereon. After the alignment film 916 is provided with an alignment function by a rubbing process or the like, a substrate having a light valve element and a counter substrate are attached with a predetermined gap provided therebetween, and an electro-optical material layer made of, for example, a liquid crystal material is provided in the gap 917 is sealed, and the light valve device shown in FIG. 3 is completed.

Although not shown, after FIG.
A third support substrate made of a transparent material is bonded under the base insulating film 902 via an adhesive layer, and the second support substrate shown in FIG.
After the support substrate 914 and the adhesive layer 913 are removed and the protective film 912 is planarized, an alignment film is formed on the protective film 912 and the alignment process is performed. When a predetermined gap is provided to the opposing substrate and bonded to each other, and an electro-optical material layer made of liquid crystal or the like is sealed in the gap, a light valve device substantially equivalent to FIG. 1 is completed. In this case, the second support substrate 914 and the adhesive layer 913 need not be made of a transparent material.

FIG. 23 shows an embodiment according to the present invention, and is a schematic large sectional view of a video projector using a light valve device according to the present invention. Video projector 50
0 denotes three active matrix transmission type light valve devices 50
1 to 503 are incorporated. After the white light emitted from the white light source lamp 504 is reflected by the reflecting mirror M1,
The three-color separation filter 505 separates the light into red light, blue light, and green light. The red light selectively reflected by the dichroic mirror DM1 is reflected by the reflecting mirror M2, is then condensed by the condenser lens C1, and is incident on the first light valve device 501. The red light modulated by the light valve device 501 according to the video signal passes through dichroic mirrors DM3 and DM4, and is enlarged and projected forward through an enlargement lens 506. Similarly, the blue light that has passed through the dichroic mirror DM1 is selectively reflected by the dichroic mirror DM2, condensed by the condenser lens C2, and then enters the second light valve device 502. Here, after being modulated according to the video signal,
The light is incident on a common magnifying lens 506 via dichroic mirrors DM3 and DM4. Further, after passing through the dichroic mirrors DM1 and DM2, the green light is condensed by the condenser lens C3, and is condensed by the third light valve device 5
03. Here, after being modulated according to the video signal, the light is reflected by the reflecting mirror M3 and the dichroic mirror DM4, and travels to the magnifying lens 506. In this manner, the three primary color lights modulated respectively by the three light valve devices finally project a forward enlarged secondary image synthesized by the magnifying lens 506. As described with reference to FIGS. 1-3 and 5-23, the light valve device used suppresses the OFF leak current even during light irradiation, and thus can operate stably. Also,
The dimensions are on the order of centimeters, and the dimensions of various optical components and white light lamps can be reduced correspondingly. Therefore, the overall shape and size of the video projector 500 can be significantly reduced as compared with the conventional one.

[0089]

As described above, according to the present invention, a parasitic channel generated when light is irradiated to a channel formation region formed of a single crystal semiconductor thin film layer of a MOS transistor, and OFF caused by a bipolar action.
This has an excellent effect that an adverse effect on the light valve device due to an increase in leakage current can be suppressed, and a light valve device that operates stably can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing one embodiment of a light valve device according to the present invention.

FIG. 2 is a schematic sectional view showing another embodiment of the light valve device according to the present invention.

FIG. 3 is a schematic sectional view showing another embodiment of the light valve device according to the present invention.

FIG. 4 is a schematic cross-sectional view of a conventionally known composite substrate including a single crystal semiconductor thin film for a light valve device.

FIG. 5 is a schematic diagram showing a change in drain current-gate voltage characteristics of an N-channel MOS transistor depending on the presence or absence of light irradiation.

FIG. 6 shows an N-channel MOS in a state where no light is irradiated.
FIG. 4 is a schematic diagram of an energy band extending from a source region to an inner region to a drain region of a type transistor.

FIG. 7 is a schematic diagram of an energy band over a source region, an inner region, and a drain region of a channel MOS transistor in a state where light is irradiated.

FIG. 8 is a diagram showing a relationship between an OFF leak current and a semiconductor layer thickness when light is irradiated to an N-channel MOS transistor having a channel length of 2 μm and a channel width of 20 μm.

FIG. 9 is a schematic cross-sectional view showing another embodiment of a MOS transistor formed on a composite substrate used in the light valve device according to the present invention.

FIG. 10 is a schematic sectional view showing another embodiment of a MOS transistor formed on a composite substrate used in a light valve device according to the present invention, in which a source region and a drain region are in contact with a surface of a base insulator layer. MOS type transistors are shown.

FIGS. 11A and 11B are schematic cross-sectional views showing another embodiment of the MOS transistor on the composite substrate used in the light valve device according to the present invention. The area is shown schematically.

FIG. 12 is a schematic cross-sectional view showing another embodiment of the MOS transistor on the composite substrate used in the light valve device according to the present invention, and (a) to (d) show the manufacturing method in the order of steps.

FIG. 13 is a schematic sectional view showing another embodiment of the method of manufacturing a composite substrate used in the light valve device according to the present invention.

FIG. 14 is a schematic cross-sectional view showing another embodiment of the MOS transistor on the composite substrate used in the light valve device according to the present invention. 5 shows a MOS transistor having a heavily doped region.

FIG. 15 is a schematic cross-sectional view showing another embodiment of the MOS transistor on the composite substrate used in the light valve device according to the present invention, showing the structure of the high breakdown voltage MOS transistor.

FIG. 16 is a schematic cross-sectional view showing another embodiment of the MOS transistor on the composite substrate used in the light valve device according to the present invention, in which an electrode for preventing a parasitic channel is provided on an insulator below a channel formation region. 2 shows a MOS transistor provided.

FIG. 17 is a schematic sectional view showing another embodiment of the MOS transistor on the composite substrate used in the light valve device according to the present invention.

FIG. 18 is a schematic diagram showing a relationship between a threshold voltage reaction amount ΔV _{TH of a} MOS transistor and a substrate potential as a parameter of a thickness of a gate insulating film.

19 (a) to (d) show a method of manufacturing a composite substrate on which the MOS transistors shown in FIG. 17 are formed in the order of steps.

20 (a) to (d) are flowcharts showing a method of manufacturing the light valve device according to FIG. 3 in the order of steps.

FIG. 21 is a schematic sectional view showing another embodiment of the MOS transistor in the light valve device according to the present invention.

FIGS. 22A to 22D are cross-sectional views in the order of steps of a method for manufacturing a light valve device including the MOS transistor shown in FIG.

FIG. 23 is a cross-sectional view of an image projection device in which the light valve device of the invention is applied to a projection type projector.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 MOS transistor 101 support substrate 102 base insulating film 103 adhesive layer 104 element isolation insulating film 105 source region 106 drain region 107 channel forming region 108 single crystal semiconductor thin film layer 109 gate insulating film 110 gate electrode 111 source electrode 112 drive electrode 113 Protective film 114 Alignment film 115 Counter substrate 116 Counter electrode 117 Alignment film 119 Intermediate insulating film 120 Internal region

──────────────────────────────────────────────────続 き Continued on the front page (31) Priority claim number Japanese Patent Application No. 4-238268 (32) Priority date September 7, 1992 (197.9.7) (33) Priority claim country Japan (JP) (56) References JP-A-3-142418 (JP, A) JP-A-2-81476 (JP, A) JP-A-63-101832 (JP, A) JP-A-4-10434 (JP, A) ( 58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/1362 G02F 1/1343 H01L 29/78

Claims (16)

(57) [Claims] 1. A semiconductor thin film formed on a base insulating layer
Made of single-crystal semiconductor thin film layer formed on the layer, the semiconductor
Channel type whose impurity concentration is lower than that of the body thin film layer
And a source provided with the channel formation region interposed therebetween.
Source region, a drain region, and the channel region.
The gate insulating film and the gate electrode sequentially formed on the
A MOS transistor that is formed in the next lamination, and a MOS transistor that is provided on the semiconductor thin film layer through an element isolation insulating film.
A pixel electrode electrically connected to the drain region, and a counter substrate and the semiconductor film layer facing each other with a predetermined distance therebetween.
The gap is filled with electro-optical material
And selectively connected to the pixel electrode by the MOS transistor.
Power, the light transmission amount of the electro-optical material changes.
1. A light valve device which operates in an integrated manner, wherein generation of a leak current due to light irradiation between the source region and the drain region of the single crystal semiconductor layer thin film layer is prevented. 2. A light valve apparatus according to claim 1, said semiconductor thin film layer made of a semiconductor of a first conductivity type comprise impurity layer of a second conductivity type formed in said <br/> semiconductor thin film layer said source region, said drain region, consists of a first conductivity type the channel formation region of the first conductivity type semiconductor is between the source region and the drain region, wherein the semiconductor thin film layer A light valve device having an impurity concentration sufficient to prevent a parasitic channel formed near an interface with a base insulating layer and a bipolar action generated between the source region and the drain region. . 3. A light valve apparatus according to claim 1, wherein the MOS transistor, the single crystal semiconductor channel crystal region is the source region and the same conductivity type as said drain region, a lower portion of the channel forming region Wherein the semiconductor thin film layer between the source region and the drain region is of a conductivity type opposite to that of the source region and the drain region. 4. A light valve apparatus according to claim 1, said semiconductor thin film layer made of a semiconductor of a first conductivity type, consisting impurity layer of a second conductivity type formed in said <br/> semiconductor thin film layer consists of a said source region and said drain region,
At least one region of the drain region and the source region is bonded to the base insulating layer, prior to said source region
A vicinity of the at least one region of the serial drain region,
A light valve device wherein a first conductivity type impurity region having a higher concentration than the first conductivity type semiconductor is formed in a semiconductor thin film layer below a channel formation region to be joined to a base insulating layer. 5. The light valve device according to claim 1, wherein a surface of the base insulating layer opposite to the semiconductor thin film layer corresponds to a single crystal semiconductor channel formation region of the semiconductor thin film layer. A light valve device, wherein a conductive layer is formed in a region, and a predetermined voltage is supplied to the conductive layer. 6. The light valve device according to claim 1, wherein the M
A light valve device, wherein the OS transistor has an LDD or DDD structure. 7. The light valve device according to claim 1, wherein the thickness of the base insulating layer is equal to or less than the thickness of the gate insulating film. 8. The light valve device according to claim 1, wherein the M
The OS type transistor has a carrier recombination region for recombination and elimination of electron and hole carriers generated by light irradiation other than the channel formation region, the source, and the drain region. Light valve device. 9. The light valve device according to claim 8 , wherein the carrier recombination region contains a lifetime killer atom. 10. The light valve according to claim 8 , wherein the carrier recombination region has been destroyed in crystallinity and is made of one of polycrystalline and amorphous materials. apparatus. 11. A step of forming a single crystal semiconductor thin film layer on a base insulating layer, a step of introducing and diffusing a first conductivity type impurity into the single crystal semiconductor thin film layer, and a step of introducing the first conductivity type impurity. Introducing a second conductivity type impurity into a surface portion of the semiconductor device, forming a gate electrode on the second conductivity type impurity introduction region via a gate insulating film, and introducing the second conductivity type impurity under the electrode. Forming a source substrate and a drain region by introducing an impurity of the second conductivity type across the region, forming a composite substrate; and forming a gap between the opposing substrate on which the electrodes are formed and the composite substrate. A method of manufacturing a light valve device, comprising the steps of providing, laminating and bonding, and filling the gap with an electro-optical material. 12. The method for manufacturing a light valve device according to claim 11 , wherein a heat treatment in a nitrogen atmosphere is used for the impurity diffusion in the step of introducing and diffusing a first conductivity type impurity into the single crystal semiconductor thin film layer. A method for manufacturing a light valve device. 13. The method of manufacturing a light valve device according to claim 11 , wherein the step of introducing the second conductivity type impurity into a surface portion of the first conductivity type impurity introduction region of the single crystal semiconductor thin film layer comprises: A method of manufacturing a light valve device, wherein arsenic is used as the second conductivity type impurity in an N-channel MOS transistor region. 14. A step of forming a single-crystal semiconductor thin-film layer on a base insulating layer, and distributing a first conductivity type impurity in the single-crystal semiconductor thin-film layer on the base insulating layer side high and on the surface side low concentration. Forming a gate electrode on the single crystal semiconductor thin film via a gate insulating film, and forming a source region and a drain region by introducing a second conductivity type impurity. A light valve device comprising: a step of forming a composite substrate including a step; a step of laminating and bonding a counter substrate having electrodes formed thereon to the composite substrate with a gap provided therebetween; and a step of filling the gap with an electro-optical material. Manufacturing method. 15. The method for manufacturing a light valve device according to claim 14 , wherein the step of forming the single crystal semiconductor thin film layer on the base insulating film layer is at least one of two single crystal silicon substrates. Forming an insulating layer on the surface of the substrate, bonding the insulating layers to each other so as to sandwich the insulating layer, and firmly adhering the substrate by heat treatment. A method for manufacturing a light valve device, comprising a step of forming a thin film layer. 16. Light emission using the defense device according to claim 1.
A light source through the light valve device and a light valve device.
Image projection that enlarges and projects the above image with a lens
Device.