JP3767599B2 - Electro-optical device drive circuit, electro-optical device drive method, electro-optical device, and electronic apparatus - Google Patents

Description

  The present invention relates to an active matrix driving type liquid crystal device driven by a thin film transistor (hereinafter referred to as TFT as appropriate), an electro-optical device driving circuit such as electroluminescence, an electro-optical device including the driving circuit, and driving of the electro-optical device. The present invention belongs to a technical field of a method and an electronic apparatus using the electro-optical device, and particularly to a technical field of a peripheral circuit such as a scanning line driving circuit and a data line driving circuit of a liquid crystal device preferably used as a light valve of a liquid crystal projector. Belongs.

  Conventionally, when a liquid crystal device is used as a light valve of this type of liquid crystal projector, a single-plate method using only one colored liquid crystal device (that is, a color filter formed on a counter substrate) and no color ( In other words, there is a multi-plate method in which three liquid crystal devices each having R, G, and B (no color filter is formed) are used. The single plate method is simple in structure, but the double plate method is more excellent in that the display screen is brightened and a high quality image can be obtained. According to this double plate system, the three color lights separately modulated by the three liquid crystal devices are combined into one projection light by the prism and the dichroic mirror, and then projected onto the screen.

  Thus, when combined with a prism or the like, for example, as shown in FIG. 16, compared with the R light and B light reflected by the prism 502 after modulation by three light valves 500R, 500G, and 500B for RGB, The G light is not reflected by the prism 502. That is, the number of times of light inversion is reduced by one for G light. Of course, this phenomenon is the same even if the optical system is configured so that the R light or B light is not reflected by the prism 502 instead of the G light, and also when three-color light is synthesized using a dichroic mirror or the like. It happens as well. Therefore, in such a case, it becomes necessary to invert the display image for the G light to the left and right in some way.

  On the other hand, depending on the product strategy, you may want to configure a single-panel or double-panel LCD projector so that it can be used as a floor-mounted type that is normally installed on the floor or as a ceiling-mounted type that is installed upside down on the ceiling. is there. In this case, even in the single plate method, there is a need to reverse the display image supplied to the liquid crystal device left and right and up and down depending on the way of installation. In some cases, a liquid crystal monitor that is a single-plate liquid crystal device, such as a liquid crystal monitor of a portable video camera, may be viewed in a reversed manner with a flexible joint as a fulcrum, for example, depending on the user's shooting posture. In this case as well, the display image of the liquid crystal device needs to be reversed vertically and horizontally in some form.

  Therefore, conventionally, an image signal processing IC that supplies image signals to a data line driving circuit of a liquid crystal device in a predetermined format. For example, only for an image signal for G or for all color image signals, Then, an image signal corresponding to an image that is inverted vertically and horizontally is generated and supplied for each field. This is convenient because it is not necessary to make any changes to the liquid crystal device or the peripheral circuit.

  Or, conventionally, for example, in the case of the above-described double-plate type liquid crystal projector, the scanning direction is reversed left and right as compared with the liquid crystal device for R and the liquid crystal device for B in order to synthesize three-color light. A liquid crystal device is used as a G liquid crystal device.

  However, the method of reversing the display image vertically and horizontally using the above-described conventional image signal processing IC is too heavy on the image signal processing IC in order to deal with recent high-quality images. It is no longer practical.

  Further, the method using a liquid crystal device in which the scanning direction is inverted vertically and horizontally has the following problems. That is, in general, a scanning line driving circuit and a data line driving circuit have a unidirectional shift register in which the transfer direction is fixed to one side, and line sequential or data transfer is performed based on a transfer signal generated from the unidirectional shift register. A scanning signal or an image signal is supplied in a dot sequential manner, and the display screen is scanned vertically and horizontally. Accordingly, in the case of a liquid crystal projector using a double-plate system, in order to use a liquid crystal device whose scanning direction is reversed, the shift register is configured so that the data line driving circuit scans the display image from left to right. There is a need to manufacture two types: a shift type liquid crystal device and an L shift type liquid crystal device in which a shift register is configured such that the data line driving circuit scans the display image from right to left. Thus, it is obviously disadvantageous from the standpoint of the manufacturer to manufacture the two types of liquid crystal devices in the TFT manufacturing process using a semiconductor manufacturing apparatus or the like. Also, from the user's standpoint, there is no compatibility between similar liquid crystal devices, and there is a practical problem that any individual device can only be used as either type. Further, in such a liquid crystal device in which the scanning direction is fixed, it is impossible to realize a liquid crystal projector that can be used as the above-described floor-standing type or a ceiling-mounted type, or a portable video camera with a screen inverted.

  Further, when a scanning signal or an image signal is supplied to a data line or a data line group based on a transfer signal from the shift register, an overlap of image signals supplied to adjacent data lines or data line groups may be caused. Therefore, the preceding image signal component is written, and ghost and image unevenness occur. Such a problem becomes conspicuous in a high frequency drive environment.

  The present invention solves the above-described problems, and a drive circuit for an electro-optical device such as a liquid crystal device that can easily invert the direction of horizontal scanning or vertical scanning left and right or up and down using a relatively simple configuration, It is an object of the present invention to provide an electro-optical device including a driving circuit and an electronic apparatus including the electro-optical device.

In order to solve the above problems, a drive circuit for an electro-optical device according to an aspect of the invention includes a plurality of data lines to which image signals are supplied, and a plurality of scanning lines that intersect the plurality of data lines and to which a scanning signal is supplied. A driving circuit of an electro-optical device having switching means provided corresponding to the intersection of each data line and each scanning line and pixel electrodes provided corresponding to the switching means, A bi-directional shift register having a plurality of stages and supplying a transfer signal in the first or second transfer direction based on a clock signal; and output from an odd-numbered stage in the transfer direction of the bi-directional shift register A first waveform selection circuit that outputs a sampling circuit drive signal having a pulse width limited by a pulse of the first waveform selection signal based on an input of the transfer signal and the first waveform selection signal. Sampling circuit drive in which the pulse width is limited by the pulse of the second waveform selection signal based on the input of the transfer signal output from the even-numbered stage in the transfer direction of the directional shift register and the second waveform selection signal A second waveform selection circuit that outputs a signal; and a sampling circuit that samples the image signal based on the sampling circuit drive signal and supplies the image signal to the data line; and A first waveform selection circuit to which a transfer signal output from the first stage in the transfer direction is input, and a first waveform selection to which a transfer signal output from the first stage in the second transfer direction of the bidirectional shift register is input The first waveform selection signal is input to both of the circuits, and the transfer direction of the bidirectional shift register is the same as that of the first and second transfer directions. Even in the case of deviation, the pulse waveforms of the first waveform selection signal and the second waveform selection signal are the same, and the pulse of the first waveform selection signal is the same as the pulse of the second waveform selection signal. It is characterized by not overlapping.

  According to the drive circuit of this electro-optical device, the first and second waveform selection signals supplied to the adjacent waveform selection circuits are spaced at an appropriate time interval. Ghosting and image unevenness due to writing can be prevented in advance. This is particularly effective in a high frequency drive environment.

Further, the present invention is characterized in that each of the first and second waveform selection circuits includes a logic circuit that takes a logical product or a negative logical product of the transfer signal and the first or second waveform selection signal. .

  According to this configuration, since the first logic circuit that takes the logical product or exclusive logical product of the first transfer signal and the first waveform selection signal is included, it can be limited to a predetermined pulse width.

According to another aspect of the drive circuit of the electro-optical device of the invention, the pulse widths of the first and second waveform selection signals are narrower than the pulse width of the transfer signal.

  According to the drive circuit of the electro-optical device, an appropriate time interval is provided between image signals supplied to adjacent data lines or data line groups, so that an image caused by overlapping of the image signals can be obtained. Ghosts and image unevenness due to signal component writing can be prevented in advance. This is particularly effective in a high frequency drive environment.

The drive circuit of the electro-optical device according to the aspect of the invention supplies a first waveform selection signal line for supplying the first waveform selection signal to the first waveform circuit, and supplies the second waveform selection signal to the second waveform circuit. A second waveform selection signal line that is disposed adjacent to the first and second waveform selection signal lines so as to smooth the transition of the pulse waveform of the first and second waveform selection signals. It is characterized by.
Further, the image signal line for supplying the image signal to the sampling circuit is provided, and the image signal line is arranged along the first waveform selection signal line and the second waveform selection signal line. And

  According to the driving circuit of the electro-optical device, by smoothing the pulse waveform, it is possible to suppress the ringing of the waveform selection signal itself and to prevent the signal component of the waveform selection signal from being written as noise on the image signal line. It can be done.

The rising or falling transitions of the pulse waveforms of the first and second waveform selection signals are in the range of 20 to 50 ns.

According to this configuration, it is possible to reliably prevent the signal component of the waveform selection signal from being written as noise in the image signal.

The electro-optical device driving method of the present invention includes a plurality of data lines to which image signals are supplied, a plurality of scanning lines that intersect with the plurality of data lines and to which a scanning signal is supplied, the data lines, A driving method of an electro-optical device having switching means provided corresponding to the intersection of the scanning lines and pixel electrodes provided corresponding to the switching means, both having an odd number of stages A sampling circuit drive signal whose pulse width is limited by the pulse of the first waveform selection signal based on the input of the transfer signal output from the odd-numbered stage in the transfer direction of the directional shift register and the first waveform selection signal , And the second waveform selection signal based on the input of the transfer signal output from the even-numbered stage in the transfer direction of the bidirectional shift register and the second waveform selection signal. A step of outputting a sampling circuit driving signal whose pulse width is limited by a pulse of the sampling, a sampling step of sampling the image signal based on the sampling circuit driving signal and supplying the image signal to the data line, and selecting the scanning line Supplying the image signal sampled in the sampling step to the switching means electrically connected to the selected scanning line via the data line, and the bidirectional shift register A step of outputting a sampling circuit drive signal based on a transfer signal output from the first stage in the first transfer direction, and a transfer signal output from the first stage in the second transfer direction of the bidirectional shift register. And outputting the sampling circuit drive signal based on the pulse of the first waveform selection signal. The pulse width of the sampling circuit drive signal is limited by the above, and the first waveform selection signal and the second waveform selection signal are the same regardless of the transfer direction of the transfer signal of the bidirectional shift register. Pulses having the same waveform are used, and the first and second waveform selection signals are pulses that are alternately output without overlapping each other.

According to the driving method of the electro-optical device, sampling in which the pulse width is limited by the pulses of the first and second waveform selection signals between the image signals supplied in succession to adjacent data lines or data line groups. Since an appropriate time interval is set by the control signal, it is possible to prevent ghost and image unevenness due to writing of image signal components due to overlapping of image signals. This is particularly effective in a high frequency drive environment.

The present invention is characterized in that the sampling circuit drive signal is output based on a logical product or a negative logical product of the transfer signal and the first or second waveform selection signal.

The shift register is a bidirectional shift register that supplies the transfer signal in a first direction or a second direction, and when the shift register supplies the transfer signal in a first direction, the first direction of the shift register The sampling circuit drive signal is output based on the input of the transfer signal output from the first stage and the first waveform selection signal in the first stage, and the shift register supplies the transfer signal in the second direction. The sampling circuit drive signal is output based on the input of the transfer signal and the first waveform selection signal output from the first stage in the second direction of the register.

In addition, the driving method of the electro-optical device according to the present invention is characterized in that the transition of the pulse waveform of the first and second waveform selection signals is smoothed.

  According to the drive circuit of the electro-optical device, by suppressing the transition of the pulse waveform, it is possible to suppress the ringing of the waveform selection signal itself and to prevent the signal component of the waveform selection signal from being written into the image signal as noise. It can be done.

  Also, the driving method of the electro-optical device according to the present invention is characterized in that the transition of the rising or falling of the pulse waveform of the first and second waveform selection signals is in the range of 20 to 50 ns.

  Such an operation and other advantages of the present invention will become apparent from the embodiments described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Overall configuration of liquid crystal device)
First, an overall configuration of a liquid crystal device as an example of an electro-optical device will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of various wirings, peripheral circuits and the like provided on the TFT array substrate 1 in the embodiment of the liquid crystal device. In this embodiment, the present invention is applied to a liquid crystal device of an active matrix driving system by TFT driving.

  In FIG. 1, a TFT array substrate 1 is made of, for example, a quartz substrate, hard glass, a silicon substrate, or the like. On the TFT array substrate 1, a plurality of pixel electrodes 11 provided in a matrix, a plurality of data lines 35 arranged in the X direction and extending in the Y direction, and a plurality of data electrodes 35 arranged in the Y direction are arranged. A scanning line 31 is formed, each extending along the X direction. Further, the scanning line 31 is electrically connected to the gate of the TFT 30, and scanning signals Y1, Y2,..., Ym are applied to the scanning line 31 in a pulsed manner at a predetermined timing. The pixel electrode 11 is electrically connected to the drain of the TFT 30, and the image signal VID supplied from the image signal line 304 is converted to D 1, D 2,. , Dn is written to the data line 35. A predetermined level of the image signal VID written in the liquid crystal via the pixel electrode 11 is held for a certain period with a counter electrode (described later) formed on a counter substrate (described later). On the TFT array substrate 1, a capacitor line 31 ′ (storage capacitor electrode) that is a wiring for the storage capacitor 70 is formed substantially in parallel along the scanning line 31, and the storage capacitor 70 is formed on the pixel electrode 11. Is added. Thereby, deterioration of display quality such as flicker caused by parasitic capacitance can be prevented. In order to form the storage capacitor 70, the preceding scanning line 31 may be used as an electrode for forming the storage capacitor. If such a configuration is adopted, the capacitor line 31 ′ need not be provided.

  The image signal VID written to the data line 35 may be supplied line by line for each data line 35 or may be supplied for each group of a plurality of adjacent data lines 35. If a plurality of adjacent data lines 35 are driven at the same time, it is possible to reduce the drive frequency of the data line drive circuit by shifting the phase of the image signal VID, thereby reducing the circuit reliability and power consumption. Can be realized.

  On the TFT array substrate 1, a sampling circuit 301 that samples the image signal VID and supplies it to the data lines 35, a data line driving circuit 101, and a scanning line driving circuit 104 are further formed.

  The scanning line driving circuit 104 has a bidirectional shift register described later, and this bidirectionality is based on the reference clock signal CLY supplied from the external control circuit, its inverted clock signal CL INV, the start signal SPY, and the like. A scanning signal having a predetermined waveform and a predetermined timing is generated from the transfer signal output from the shift register, and is applied to the scanning line 31 in a pulse-sequential manner. In particular, the scanning line driving circuit 104 fixes a plurality of scanning lines 31 by fixing the transfer direction of the bidirectional shift register in the forward direction or the reverse direction in accordance with a transfer direction control signal input from the outside as described in detail later. On the other hand, it is possible to sequentially supply scanning signals in the order of T to B in FIG. 1 or sequentially supply scanning signals in the order of B to T.

  The data line driving circuit 101 has a bidirectional shift register, which will be described later, a reference clock CLX supplied from an external control circuit, an inverted signal of the clock signal (hereinafter referred to as an inverted clock signal) CLX INV, start Based on the signal SPX and the like, sampling circuit drive signals S1, S2,... Sn with a predetermined waveform and predetermined timing are generated from the transfer signal output from the bidirectional shift register.

  The sampling circuit 301 includes a TFT 302 for each data line 35, the image signal line 304 is connected to the source electrode of the TFT 302, and the sampling circuit drive signal line 306 is connected to the gate electrode of the TFT 302. When the sampling circuit drive signals S1, S2,... Sn are input to the sampling circuit 301 via the sampling circuit drive signal line 306, the image signal VID supplied from the image signal line 304 is converted into the data lines in the order of DL, D2,. Apply to 35. In particular, the data line driving loop 101 fixes the data line 35 to the data line 35 by fixing the transfer direction of the bidirectional shift register in the forward direction or the reverse direction in accordance with a transfer direction control signal input from the outside as described in detail later. On the other hand, the image signal VID can be sequentially supplied in the order of L to R, and the image signal VID can be sequentially supplied in the order of R to L. As described above, in the present embodiment, the data lines 35 are selected for each line. However, the data lines 35 may be selected for a plurality of lines at the same time. For example, an image signal VID that is phase-expanded into a plurality of phases (for example, three phases, six phases, twelve phases,...) According to the writing characteristics of the TFT 302 that constitutes the sampling circuit 301 and the frequency of the image signal VID. May be configured to be sampled simultaneously for each group. At this time, it goes without saying that at least the number of image signal lines 304 is required for the number of phase expansions.

(First Embodiment of Driving Circuit)
Next, a first embodiment of the drive circuit will be described with reference to FIGS. FIG. 2 shows the data line driving circuit 101 in the first embodiment. In FIG. 2, the image signal output as a serial signal is phase-expanded into six parallel image signals, and the image signals VID1 to VID6 are input to the data line 35 via the six image signal lines 304, respectively. This will be described using a configuration example. 3A and 3B are timing charts of various signals in the data line driving circuit 101. FIG. 4A and 4B are circuit diagrams of clocked inverters constituting the bidirectional shift register 111 of the data line driving circuit 101. FIG. FIG. 5 is a diagram showing a modification of the sampling circuit drive signal line 306 output from the data line drive circuit 101 of FIG.

  First, the data line driving circuit will be described.

  In FIG. 2, the data line driving circuit 101 includes a bidirectional shift register 111, a plurality of waveform selection circuits 112 a provided corresponding to outputs of odd-numbered stages of the bidirectional shift register 111, and the bidirectional And a plurality of waveform selection circuits 112b provided corresponding to the even-numbered stages of the output shift register 111, respectively.

  Particularly in the present embodiment, the data line driving circuit 101 as an example of the data line driving means includes a bidirectional shift register 111 having an odd number of output stages, for example, six data lines 35 adjacent to each other. A sampling circuit drive signal S1 sequentially output from each stage of the bidirectional shift register 111 in a transfer direction corresponding to a direction from L to R or a direction from R to L with respect to an odd number of data line groups; Based on S2, S3,..., Sn, the image signals VID1 to VID6 can be sequentially supplied in cooperation with the sampling circuit 302. In the bidirectional shift register 111, a start signal SP (L) for starting transfer of a transfer signal from L to R is input from the L side in the drawing, or a transfer signal from R to L is input. A start signal SP (R) for starting transfer is input from the R side in the figure. Then, the data line driving circuit 101 performs the start signal SP (L), the clock signal CL, the inverted clock signal CL INV, and the first and second waveform selection signals ENB1 and ENB2 at the timing shown in the timing chart of FIG. Are sequentially delayed by a half cycle of the clock signal CL, and each of the sampling circuit drive signals S1, S2, S3,..., Sn (where n is a pulse width narrower than the pulse width of the clock signal CL) Odd number) is supplied to the sampling circuit 301.

  Next, the bidirectional shift register 111 will be described in detail.

  As shown in FIG. 2, each stage of the bidirectional shift register 111 includes a binary transfer direction control signal D as an example of the first direction control signal and an inverted signal (hereinafter referred to as an inverted transfer direction) of the transfer direction control signal. The transfer direction is fixed according to D INV (referred to as a control signal), and is fed back to the transfer signal every time the binary level of the reference clock signal CL and the inverted clock signal CL INV as an example of the first clock signal of a predetermined period changes. And includes four clocked inverters 114, 115, 116 and 117 which constitute an example of the first gate means for transferring and outputting to the next stage.

  The clocked inverter 114 as an example of the first clocked inverter is configured so that transfer is possible when the transfer direction control signal D is at a high level, and the transfer direction is fixed in a direction from L to R as an example of the forward direction. It is connected.

  The clocked inverter 115 as an example of the second clocked inverter is capable of transferring when the inverted transfer direction control signal D INV is at a high level so that the transfer direction is fixed in a direction from R to L as an example of the reverse direction. Configured and connected.

  When the transfer direction is fixed in the direction from L to R, the clocked inverter 116 as an example of the third clocked inverter receives a transfer signal transferred through the clocked inverter 114 and the clock signal CL is at a high level. And when the transfer direction is fixed in the direction from R to L, the transfer signal transferred via the clocked inverter 115 is fed back when the clock signal CL is at a high level. It is connected.

  Further, when the transfer direction is fixed in the direction from R to L, the clocked inverter 117 as an example of the fourth clocked inverter converts the transfer signal transferred via the clocked inverter 115 to the inverted clock signal CL. When the INV signal is transferred at the high level and the transfer direction is fixed in the direction from L to R, the transfer signal transferred via the clocked inverter 114 is fed back when the inverted clock signal CL INV is at the high level. Configured and connected.

  A specific circuit configuration of the clocked inverter 116 extracted from FIG. 4A is shown in a circuit diagram in FIG. For the other clocked inverters 114, 115, and 117, the clock signal CL and the inverted clock signal CL INV input to the clock input terminal are the transfer direction control signal D, the inverted transfer direction control signal D INV, and the inverted transfer direction, respectively. Only the control signal D INV and the transfer direction control signal D, the inverted clock signal CL INV and the clock signal CL are used, and the circuit configuration is the same.

  As shown in FIG. 4B, the clocked inverter 116 has an N-channel TFT to which the clock signal CL is input to the gate, a P-channel TFT to which the inverted clock signal CL INV is input, and a transfer signal to the gate. A P-channel TFT and an N-channel TFT connected in parallel so as to be input, and a power source VSS (ground potential power source) and VDD (high potential power source) are connected as shown in the figure. Thus, since each clocked inverter requires the power supply VSS and VDD, it is necessary to route the power supply wiring to each clocked inverter as the entire bidirectional shift register 111 shown in FIG. In each clocked inverter, since the input terminal and the output terminal are insulated by the gate insulating film of each TFT, even if the frequency of the transfer signal is high, no current leaks against the transfer direction. There are advantages. Therefore, the bidirectional shift register 111 as a whole has an advantage that a stable transfer signal can be output with respect to a high frequency.

  Next, the waveform selection circuits 112a and 112b will be described.

  In FIG. 2, the waveform selection circuit 112a is configured to limit the pulse width of the transfer signal output from the odd-numbered stages of the bidirectional shift register 111 to the pulse width of the first waveform selection signal ENB1. For example, as shown in FIG. 2, the waveform selection circuit 112a includes an NAND circuit that forms an exclusive logical product of the transfer signal and the waveform selection signal ENB1 and that constitutes an example of the first logic circuit, and an inverter circuit that inverts the result. By such a logical operation, as shown in FIGS. 3A and 3B, the pulse width of the transfer signal is limited to the pulse width of the signal ENB1.

  The waveform selection circuit 112b is configured to limit the pulse width of the transfer signal output from the even-numbered stages of the bidirectional shift register 111 to the pulse width of the second waveform selection signal ENB2. For example, as shown in FIG. 2, the waveform selection circuit 112b includes an NAND circuit that forms an exclusive logical product of the transfer signal and the waveform selection signal ENB2, and an inverter circuit that inverts the result. As shown in FIGS. 3A and 3B, the pulse width of the transfer signal is limited to the pulse width of the signal ENB2 by such a logical operation.

  Next, the operation of the data line driving circuit 101 configured as described above will be described.

  First, as a first case in FIG. 2, when the transfer direction control signal D is fixed at a high level and the inverted transfer direction control signal D INV is fixed at a low level and inputted to the bidirectional shift register 111, The transfer direction is changed from L to R by the clocked inverter 114 that is provided in each stage of the bidirectional shift register 111 and that can be transferred under this condition and the clocked inverter 115 that cannot be transferred under this condition. Fixed in the direction to go. In this state, as shown in FIG. 3A, when a signal SP (L) for starting transfer is input, every time the binary level of the clock signal CL and the inverted clock signal CL INV changes, Clocked inverters 116 and 117 to which the clock signal CL and the inverted clock signal CL INV are input perform transfer and feedback, respectively. Then, the transferred transfer signal is transferred to the next stage (R side stage) of the bidirectional shift register 111 and output to the corresponding waveform selection circuit 112a or 112b. Since feedback is applied at each stage in this way, the transfer signal is not lost and is sequentially transferred to the next stage.

  On the other hand, in the second case in FIG. 2, when the transfer direction control signal D is fixed at a low level and the inverted transfer direction control signal D INV is fixed at a high level and is input to the bidirectional shift register 111. In each stage of the bidirectional shift register 111, the transfer direction is changed from R to L by the clocked inverter 114 that cannot be transferred under this condition and the clocked inverter 115 that can be transferred under this condition. Fixed. In this state, as shown in FIG. 3B, when a start signal SP (R) for starting transfer is input, every time the binary level of the clock signal CL and its inverted clock signal CL INV changes. The clocked inverters 116 and 117 to which the clock signal CL and its inverted clock signal CL INV are input perform feedback and transfer, respectively. Then, the transferred transfer signal is transferred to the next stage (L side stage) of the bidirectional shift register 111 and output to the corresponding waveform selection circuit 112a or 112b.

  Assuming that the bidirectional shift register 111 is an even-numbered bidirectional shift register, the transfer direction is a direction from L to R and a direction from R to L. The transfer signal output from the first stage (for example, the L-end or R-end stage) of the bidirectional shift register 111 is a signal whose phase is shifted by a half cycle of the clock signal CL. Therefore, in order to actually reverse the transfer direction and display the image with the liquid crystal device 10 without any trouble, it is not sufficient to change only the binary level of the transfer direction control signal D and the reverse transfer direction control signal D INV. Therefore, it is necessary to invert the clock signal CL and the inverted clock signal CL INV. That is, in this case, the wiring of the clock signal CL and the inverted clock signal CL INV has to be switched somewhere. In this embodiment, the bidirectional shift register 111 has an odd number of output stages. 3A and 3B, the transfer direction of the bidirectional shift register 111 is the same regardless of whether the transfer direction is from L to R or from R to L, as shown in FIGS. The transfer signal output from the first stage (left end or right end stage) is the same signal. That is, in order to invert the transfer direction, it is only necessary to change the binary level of the transfer direction control signal D and the inversion transfer direction control signal D INV, and it is not necessary to invert the clock signal CL and the inversion clock CL INV. This is very advantageous in terms of the configuration and control of the apparatus.

  Similarly, in the case of the waveform selection circuit, when the bidirectional shift register is an even number output stage, the waveform selection signal input to the waveform selection circuit 112a controlled by the output signal from the odd number stage of the bidirectional shift register. Although the waveform selection signal ENB2 input to the waveform selection circuit 112b controlled by the output signal from the ENB1 and the even-numbered stage of the bidirectional shift register needs to be switched every time the transfer direction is inverted, the waveform selection signals ENB1 and ENB2 must be switched. In this embodiment, since the bidirectional shift register 111 is configured to have an odd number of output stages, the transfer direction is from L to R as shown in FIGS. The output signal output from the first stage (left end or right end stage) of the bidirectional shift register 111 is the same signal regardless of the direction or the direction from R to L. It made. That is, in order to invert the transfer direction, it is only necessary to change the binary level of the transfer direction control signal D and the inversion transfer direction control signal D INV, and it is not necessary to invert the waveform selection signals ENB1 and ENB2. Is very advantageous in terms of control.

  For this reason, the image signal processing IC or the like does not require a mechanism or control for switching the clock signal by providing a memory or the like, which is very advantageous not only in terms of the configuration and control of the liquid crystal device 10 but also in terms of cost. In particular, such switching is generally more difficult as the drive frequency becomes higher, and is thus very effective in the case of the data line drive circuit 101 having a high drive frequency.

  As described above, when the transfer signal is sequentially output from each of the bidirectional shift registers 111 in the direction from L to R or from R to L, the waveform selection circuits 112a and 112b perform the following operations. .

  That is, the pulse width of the transfer signal output from the odd-numbered stage of the bidirectional shift register 111 is set by the waveform selection circuit 112a as shown in FIG. 3 (a) or (b). Limited to pulse width. As shown in FIG. 3 (a) or (b), the pulse width of the transfer signal output from the even-numbered stage of the bidirectional shift register 111 is set by the waveform selection circuit 112b to the pulse width of the second waveform selection signal ENB2. Limited to After that, if the transfer signal whose pulse width is limited is a direction in which the transfer direction is from R to L, as shown in FIG. 3A, sampling circuit drive signals S1, S2,. , N are odd numbers) and are sequentially output to the sampling circuit 301. Alternatively, if the transfer direction is the direction from L to R, as shown in FIG. 3B, the sampling circuit drive signals Sn, Sn-1, Sn-2,..., S1 are sequentially output to the sampling circuit 301. Is done.

  Therefore, according to the signals S 1, S 2,..., Sn having an appropriate time interval due to the limitation of the pulse width, there is an appropriate time between image signals supplied to adjacent data line groups. Spaced. In this way, if an appropriate time interval is provided between the image signals, these image signals are overlapped particularly in an environment of high frequency driving, and a ghost or the like caused by writing some of the preceding image signal components. This is very advantageous because it can prevent the occurrence of image unevenness.

  As described above, the sampling circuit drive signals S1, S2,..., Sn, or Sn, Sn−1,..., S1, (, generated by limiting the pulse width of the transfer signal by the waveform selection circuits 112a and 112b. However, N is an odd number), for example, at the gates of the six TFTs 302 constituting the sampling circuit 301 in the data line group composed of the six adjacent data lines corresponding to the respective image signals VID1 to VID6 developed in six phases. Input at the same time. As a result, six data lines 35 are simultaneously driven, and this operation is repeated, so that an image signal is sequentially supplied to each data line group composed of six data lines.

  In addition, since an image signal is supplied to one data line group based on the same transfer signal, the number of data lines 35 constituting the data line group is changed from the image signal processing IC to the data line driving circuit. It is preferable to match the number of phase expansions of the image signal input to 101. Therefore, when the phase development is not performed according to the format of the image signal, or when the writing capability of each TFT 302 of the sampling circuit 301 is high, or when a sufficient writing time is given to the sampling circuit 302, for example, as shown in FIG. As described above, the data line group may be formed by a single data line.

  FIG. 5 shows a modification of the sampling circuit drive signal line 306 output from the data line drive circuit 101 of FIG. In FIG. 5, the configuration of the data line driving circuit 101 is the same as that in FIG. 2, but each TFT 302 of the sampling circuit 301 is connected to one waveform selection circuit 112a or 112b. As a result, the data lines 35 are sequentially driven one by one by the data line driving circuit 101.

  Next, the scanning line driving circuit will be described.

  Similar to the data line driving circuit 101, the scanning line driving circuit 104 as an example of the scanning line driving unit includes the bidirectional shift register 111 having the odd number of output stages shown in FIG. The output of the transfer signal is connected to the scanning line 31, and each stage of the bidirectional shift register 111 is in the transfer direction corresponding to the direction from T to B or the direction from B to T with respect to the scanning line 31. The transfer signals sequentially output from are directly supplied as scan signals, or as scan signals via the waveform selection circuits 112a and 112b shown in FIG. ing.

  In this case, the bidirectional shift register 111 has the same configuration, but the transfer direction control signal may be the same transfer direction control signal D and the inverted transfer direction control signal D INV as those of the data line driving circuit 101. A transfer direction control signal dedicated to the scanning line driving circuit 104 may be prepared. If the same transfer direction control signal D and inverted transfer direction control signal D INV are used, the transfer directions of the data line driving circuit 101 and the scanning line driving circuit 104 can be switched completely in synchronization with each other. When the signal is used, the transfer direction of the data line driving circuit 101 and the scanning line driving circuit 104 can be switched independently.

  Note that the clock signal for the scanning line driving circuit 104 depends on the total number of scanning lines 31 and the length of the vertical scanning period. However, unless special high-speed driving such as multi-sync driving is performed, the clock of the data line driving circuit 101 is used. A clock signal having a lower frequency than the signals CL and CL INV is used. Further, if the scanning frequency supplied to the adjacent scanning lines 31 is not substantially overlapped by setting the clock frequency in the scanning line driving circuit 104 to be low, the scanning line driving circuit 104 has an external signal. The waveform selection circuits 112a and B controlled by the waveform selection signal can be omitted.

(Second Embodiment of Driving Circuit)
Next, a second embodiment of the drive circuit will be described with reference to FIGS. FIG. 6 shows the data line driving circuit 101 in the second embodiment. FIG. 7 is a circuit diagram of a transmission gate constituting the bidirectional shift register of the data line driving circuit 101. The same constituent elements as those in the first embodiment shown in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 6, the data line driving circuit 101 includes a bidirectional shift register 121 having an odd number of output stages, and each stage of the bidirectional shift register 121 constitutes another example of the first gate means. Two transmission gates 124 and 125 and two clocked inverters 126 and 127 are included.

  The transmission gate 124 as an example of the first transmission gate is configured and connected so that transfer is possible when the transfer direction control signal D is at a high level and the transfer direction is fixed in the direction from L to R.

  The transmission gate 125 as an example of the second transmission gate is configured and connected so that transfer is possible when the inverted transfer direction control signal D INV is at a high level, and the transfer direction is fixed in the direction from R to L.

  The clocked inverter 126 as another example of the first clocked inverter is configured such that when the transfer direction is fixed in the direction from L to R, the transfer signal transferred via the transmission gate 124 is transferred to the clock signal CL. Configuration and connection so that when the clock signal CL is high level, the transfer signal is transferred when the clock signal CL is high level. Has been.

  In addition, when the transfer direction is fixed in the direction from R to L, the clocked inverter 127 as another example of the second clocked inverter receives the transfer signal of the inverter 128 via the transmission gate 125. Before and after, when the inverted clock signal CL INV is at a high level, feedback is applied and when the transfer direction is fixed in the direction from L to R, the transfer signal transferred via the transmission gate 124 is transferred to the front and rear of the inverter 128. Are configured and connected so as to provide feedback when the inverted clock signal CL INV is at a high level.

  A specific circuit configuration of the transmission gate 126 extracted from FIG. 7A is shown in a circuit diagram in FIG. The circuit configurations of the other transmission gates 127 are the same except that the clock signal CL and the inverted clock signal CL INV input to the clock input terminal become the inverted transfer direction control signal D INV and the transfer direction control signal D, respectively. It is.

  In the transmission gate 126, as shown in the figure, the N-channel TFT to which the clock signal CL is input to the gate and the P-channel TFT to which the inverted clock signal CL INV is input transfer the transfer signal between the source and the drain. It is connected to the. Thus, since each transmission gate does not require a power supply, the bidirectional shift register 121 as a whole has an advantage that it is not necessary to route the power supply wiring to each transmission gate. Accordingly, the layout area of the data line driving circuit 101 and the scanning line driving circuit 104 can be reduced, so that a small liquid crystal device can be realized.

  Since it is configured as described above, the bidirectional shift register 121 is configured such that the transfer direction is from L to R or R according to the binary level of the transfer direction control signal D and the inverted transfer direction control signal D INV. Functions as a unidirectional shift register in the direction from L to L.

  The waveform selection circuits 112a and 112b are the same as those in the first embodiment.

  In the second embodiment, the scanning line driving circuit may be configured similarly to the scanning line driving circuit 104 in the first embodiment using the bidirectional shift register 111 or 121. Description is omitted.

(Third embodiment of drive circuit)
Next, a third embodiment of the drive circuit will be described with reference to FIG. FIG. 8 shows a data line driving circuit according to the third embodiment. The same constituent elements as those in the first embodiment shown in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 8, the data line driving circuit 101 includes a bidirectional shift register 131 having an odd number of output stages, and each stage of the bidirectional shift register 131 constitutes another example of the first gate means. Four transmission gates 134 to 137 are included.

  The transmission gate 134 as another example of the first transmission gate is configured to be transferable when the transfer direction control signal D is at a high level, and is configured to fix the transfer direction in a direction from L to R.

  The transmission gate 135 as another example of the second transmission gate is configured to be able to transfer when the inverted transfer direction control signal D INV is at a high level, and to fix the transfer direction in the direction from R to L.

  The transmission gate 136 as an example of the third transmission gate transfers the transfer signal transferred via the transmission gate 134 when the transfer direction is fixed in the direction from L to R when the clock signal CL is at the high level. At the same time, when the transfer direction is fixed from R to L and fixed in the la direction, the transfer signal transferred through the transmission gate 135 is configured and connected to transfer when the clock signal CL is at the high level. Yes.

  In addition, the transmission gate 137 as an example of the fourth transmission gate is configured such that when the transfer direction is fixed in the direction from R to L, the inverted clock signal CL INV is added to the transfer signal transferred through the transmission gate 135. At the level, when feedback is applied before and after the inverters 138 and 139 and the transfer direction is fixed in the direction from L to R, the inverted clock signal CL INV is added to the transfer signal transferred via the transmission gate 134. When the level is high, feedback is applied before and after the inverters 138 and 139.

  Since it is configured as described above, the bidirectional shift register 131 has a direction in which the transfer direction is from L to R or R depending on the binary level of the transfer direction control signal D and the inverted transfer direction control signal D INV. Functions as a unidirectional shift register in the direction from L to L.

  Further, in this embodiment, since all the circuits constituting the bidirectional shift register 131 are configured by transmission gates, there is no need to route power to the bidirectional shift register 131, and the data line driving circuit 101 and the scanning line Since the layout area of the driver circuit 104 can be reduced, a small liquid crystal device can be realized.

The waveform selection circuits 112a and 112b are the same as those in the first embodiment.

  In the third embodiment, the scanning line driving circuit may be configured similarly to the scanning line driving circuit 104 in the first embodiment using the bidirectional register 111, 121, or 131. I will omit the present.

(Modified form of drive circuit)
Next, a modified embodiment of the drive circuit will be described with reference to FIGS. Since each modification relates to a modification of the bidirectional shift register, only this point will be described.

  First, as shown in FIG. 9, in the first modified embodiment, instead of the clocked inverters 114 and 115 for fixing the transfer direction in the first embodiment (see FIG. 2), a “transmission gate” is used. + Inverter "114 '" and "Transmission gate + Inverter" 115' are used. If the transfer direction control signal D and the inverted transfer direction control signal D INV are input to the “transmission gate + inverter” 114 ′ and 115 ′, the transfer direction goes from L to R according to their binary level. The unidirectional shift register can be a direction or a direction from R to L. In this case, as compared with the first embodiment, the power supply is not required for the transmission gate as shown in FIG. 7B, so that the layout area of the peripheral circuit can be reduced, and the size can be reduced. The liquid crystal device can be realized.

  Next, a second modification is the same as the second and third embodiments described above (see FIGS. 6 and 8), except that at least one of the transmission gates 124, 125, and 134 to 137 is replaced with P Either a channel TFT or an N-channel TFT is used. FIG. 10 shows an example using one of such P-channel TFT and N-channel TFT. In this case, as compared with the first embodiment, the structure using one of the P-channel TFT and the N-channel TFT is simpler than the transmission gate shown in FIG. 7 and does not require a power source. . Since the number of elements is half that of the transmission gate, the layout area of the data line driving circuit 101 and the scanning line driving circuit 104 can be further reduced, and an ultra-small liquid crystal device can be realized.

  In addition, a bidirectional shift register having an odd number of output stages according to the present invention can be configured by using various semiconductor elements, basic circuits, etc., and since it has an odd number of output stages, as described above, a clock signal and waveform selection It is possible to construct a convenient bidirectional register that can reverse the transfer direction by changing the binary level of the transfer direction control signal without having to invert the signal, and this makes it possible to easily invert the vertical and horizontal scans from left to right and up and down. A device can be realized.

  In the above embodiment, in the bidirectional shift register, the waveform selection signals ENB1 and ENB2 output from the adjacent waveform selection circuits are not overlapped so that the waveform selection signals ENB1 and ENB2 are spaced at an appropriate time interval. It is configured as follows. However, even in the case of a shift register that does not have a bidirectional shift register, the pulse width of the clock signal is adjusted using the waveform selection circuit of this embodiment so that adjacent waveform selection signals do not overlap. If configured, it is effective in preventing ghosts and image irregularities.

  A modification of the waveform selection signal in the above embodiment will be described with reference to FIG. FIG. 17 shows waveforms of the start signal SP, the clock signal CL and the inverted clock signal CL INV, and the waveform selection signals ENB1 and ENB2. Only the differences from the above embodiment will be described, and the common configuration will be described. Is omitted.

  In FIG. 17, the transition of the pulse waveform of the waveform selection signal is smoothed within a range of several + ns, preferably 20 ns or more and 50 ns or less. Specifically, the waveform selection signals ENB1 and ENB2 are configured to be smoothed in the above range at the rise and fall. By smoothing the pulse waveform in this manner, ringing of the waveform selection signal itself can be suppressed, and writing of the signal component of the waveform selection signal as noise to the image signal line can be prevented.

  Further, description will be made with reference to the plan view of the layout of the waveform selection signal lines and the image signal lines in FIG. In FIG. 18, 185 and 186 are waveform selection signal lines for waveform selection signals ENB1 and ENB2, respectively, and 187 to 192 are image signal lines for image signals VIDL to VID6.

  Waveform selection signals ENB1, ENB2 and image signals VID1 and VID2 are input to waveform selection signal lines 185 and 186 and image signal lines 187 and 188, respectively, via mounting terminals 181, 182, 183 and 184 from an external circuit (not shown). Is done. Note that the mounting terminals of the image signal wirings 189 to 192 are omitted in the drawing.

  For example, as shown in FIG. 18, when the waveform selection signal lines 185 and 186 of the waveform selection signals ENB1 and ENB2 and the image signal lines 187 to 192 of the image signals VIDL to VID6 are arranged adjacent to each other, the waveform selection signal There is a possibility that the waveform selection signals ENB1 and ENB2 of the lines 185 and 186 are superimposed on the image signals VID1 to VID6 of the image signal wirings 187 to 182 as noise. However, even if they are arranged adjacent to each other, such a problem can be prevented by smoothing the transition of the waveform selection signal as described above.

  In the above embodiment, the pixel electrode 11 and the TFT 30 constitute an example of a pixel driving unit that actively drives a liquid crystal portion corresponding to a pixel. However, the pixel driving means is not limited to this example. For example, one of the data line 35 and the scanning line 31 is provided on the counter substrate as a counter electrode, and the other of the data line 35 and the scanning line 31 formed on the TFT array substrate 1 and the pixel electrode 11 are provided. Another example of pixel driving means is configured from the counter electrode, the pixel electrode 11 and the two-terminal nonlinear element by interposing two-terminal nonlinear elements such as MIM driving elements each having bidirectional diode characteristics. Also good. In addition, the present embodiment can be applied to various switching elements, various liquid crystal materials (liquid crystal phases), operation modes, liquid crystal alignments, driving methods, and the like.

(Electronics)
Next, an embodiment of an electronic apparatus including the liquid crystal device 10 described in detail above will be described with reference to FIGS.

  First, FIG. 11 shows a schematic configuration of an electronic apparatus including the liquid crystal device 10 as described above.

  In FIG. 11, an electronic device includes a display information output source 1000, a display information processing circuit 1002, a driving circuit 1004 including the scanning line driving circuit 104 and the data line driving circuit 101, a liquid crystal device 10, a clock generation circuit 1008, and a power supply circuit. 1010 is provided. The display information output source 1000 includes a ROM (Read Only Memory), a RAM (Read Access Memory), a memory such as an optical disk device, a tuning circuit, and the like, and an image signal of a predetermined format based on a clock signal from the clock generation circuit 1008. Are output to the display information processing circuit 1002. The display information processing circuit 1002 includes various known processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and a display input based on a clock signal. A digital signal is sequentially generated from the information and is output to the drive circuit 1004 together with the clock signal CLK. The driving circuit 1004 drives the liquid crystal device 10 by the above-described driving method. The power supply circuit 1010 supplies predetermined power to the above-described circuits. Note that the drive circuit 1004 may be mounted on the TFT array substrate constituting the liquid crystal device 10, and in addition to this, the display information processing circuit 1002 may be mounted.

  Next, FIGS. 12 to 15 show specific examples of the electronic apparatus configured as described above.

  In FIG. 12, a liquid crystal projector 1100 as an example of an electronic device prepares three liquid crystal display modules including the liquid crystal device 10 in which the drive circuit 1004 described above is mounted on a TFT array substrate. It is configured as a projection type projector used as 10G and 10B. In the liquid crystal projector 1100, when projection light is emitted from the lamp unit 1102 of the white light source, light corresponding to the three primary colors of RGB is generated by the two dichroic mirrors 1108 through the plurality of mirrors 1106 inside the light guide 1104. Divided into components R, G, and B, they are led to light valves 10R, 10G, and 10B corresponding to the respective colors. The light components corresponding to the three primary colors modulated by the light valves 10R, 10G, and 10B are synthesized again by the dichroic prism 1112 and then projected as a color image on the screen or the like via the projection lens 1114.

  In FIG. 13, a laptop personal computer 1200, which is another example of an electronic device, includes the above-described liquid crystal device 10 in a top cover case, and further houses a CPU, a memory, a modem, and the like, and a keyboard 1202. An integrated main body 1204 is provided.

  In FIG. 14, a pager 1300 as another example of an electronic device includes a liquid crystal device 10 in which the above-described driving circuit 1004 is mounted on a TFT array substrate in a metal frame 1302 to form a liquid crystal display module, and a light including a backlight 1306a. A guide 1306, a circuit board 1308, first and second shield plates 1310 and 1312, two elastic conductors 1314 and 1316, and a film carrier tape 1318 are accommodated. In the case of this example, the display information processing circuit 1002 (see FIG. 11) described above may be mounted on the circuit board 1308 or on the TFT array substrate of the liquid crystal device 10. Further, the above-described drive circuit 1004 can be mounted on the circuit board 1308.

  14 is a pager, a circuit board 1308 and the like are provided. However, in the case of the liquid crystal device 10 in which the driving circuit 1004 and the display information processing circuit 1002 are mounted to form a liquid crystal display module, the liquid crystal device 10 fixed in the metal frame 1302 is used as or in addition to the liquid crystal device. As a backlight type liquid crystal device incorporating the light guide 1306, it is possible to produce, sell, use, and the like.

  As shown in FIG. 15, in the case of the liquid crystal device 10 in which the drive circuit 1004 and the display information processing circuit 1002 are not mounted, an IC 1324 including the drive circuit 1004 and the display information processing circuit 1002 is mounted on a polyimide tape 1322. (Tape Carrier Package) 1320 can be physically and electrically connected to the periphery of the TFT array substrate 1 through an anisotropic conductive film to produce, sell, use, etc. as a liquid crystal device Is possible.

  In addition to the electronic devices described above with reference to FIGS. 12 to 15, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic notebook, a calculator, a word processor, a workstation, a mobile phone A video phone, a POS terminal, a device equipped with a touch panel, and the like are examples of the electronic device shown in FIG.

  The electro-optical device according to the present invention can be used as an electro-optical device such as a liquid crystal, a light emitting polymer, and an LED, and the pixel driving circuit according to the present invention can be used in various active matrix driving systems. is there. In addition, the electronic apparatus according to the present invention is configured using such an electro-optical device and its driving circuit, and can be used as an electronic apparatus that can display a high-quality image.

It is a block diagram of various wirings, peripheral circuits and the like formed on the TFT array substrate in the embodiment of the liquid crystal device. FIG. 2 is a circuit diagram of a first embodiment of a drive circuit provided in the liquid crystal device of FIG. 1. (A) And (b) is a timing chart of the various signals in the drive circuit of FIG. FIG. 3 is a circuit diagram of a clocked inverter constituting the drive circuit of FIG. 2. FIG. 5 is a circuit diagram illustrating a modification in which an output wiring to a sampling circuit of the drive circuit in FIG. 2 is changed. FIG. 6 is a circuit diagram of a second embodiment of a drive circuit provided in the liquid crystal device of FIG. 1. It is a circuit diagram of the transmission gate which comprises the drive circuit of FIG. FIG. 6 is a circuit diagram of a third embodiment of a drive circuit provided in the liquid crystal device of FIG. 1. FIG. 3 is a circuit diagram illustrating a first modification of the drive circuit of FIG. 2. FIG. 6 is a circuit diagram illustrating a second modification of the drive circuit in FIG. 2. It is a block diagram which shows schematic structure of embodiment of the electronic device by this invention. It is sectional drawing which shows the liquid crystal projector as an example of an electronic device. It is a front view which shows the personal computer as an example of an electronic device. It is a disassembled perspective view which shows the pager as an example of an electronic device. It is a perspective view which shows the liquid crystal device using TCP as an example of an electronic device. It is a conceptual diagram which shows the prism optical system which synthesize | combines the RGB three-color light of a liquid crystal projector. It is a modification of the waveform selection signal of the timing chart in FIG. It is a top view which shows the example of a layout of a waveform selection signal line and an image signal line.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... TFT array substrate 10 ... Liquid crystal device 11 ... Pixel electrode 31 ... Scan line 35 ... Data line 101 ... Data line drive circuit 104 ... Scan line drive circuit 111, 121, 131 ... Bidirectional shift register 112a, 112b ... Waveform selection Circuit 301 ... Sampling circuit

Claims (15)

A plurality of data lines to which image signals are supplied, a plurality of scanning lines that intersect the plurality of data lines and that are supplied with scanning signals, and the data lines and the scanning lines are provided corresponding to the intersections. A drive circuit for an electro-optical device having switching means and pixel electrodes provided corresponding to the switching means,
A bidirectional shift register having an odd number of stages and supplying a transfer signal in a first or second transfer direction based on a clock signal;
Sampling whose pulse width is limited by the pulse of the first waveform selection signal based on the input of the transfer signal output from the odd-numbered stage in the transfer direction of the bidirectional shift register and the first waveform selection signal A first waveform selection circuit for outputting a circuit drive signal;
Sampling whose pulse width is limited by the pulse of the second waveform selection signal based on the input of the transfer signal output from the even-numbered stage in the transfer direction of the bidirectional shift register and the second waveform selection signal A second waveform selection circuit for outputting a circuit drive signal;
A sampling circuit that samples the image signal based on the sampling circuit drive signal and supplies the image signal to the data line;
Comprising
A first waveform selection circuit to which a transfer signal output from the first stage in the first transfer direction of the bidirectional shift register is input, and an output from the first stage in the second transfer direction of the bidirectional shift register. The first waveform selection signal is input to both the first waveform selection circuit to which the transfer signal is input,
Regardless of whether the transfer direction of the bidirectional shift register is the first transfer direction or the second transfer direction, the pulse waveforms of the first waveform selection signal and the second waveform selection signal are the same. ,
The drive circuit of the electro-optical device, wherein the pulse of the first waveform selection signal does not overlap with the pulse of the second waveform selection signal.   2. The circuit according to claim 1, wherein each of the first and second waveform selection circuits includes a logic circuit that performs a logical product or a negative logical product of the transfer signal and the first or second waveform selection signal. Drive circuit for electro-optical device.   3. The drive circuit of the electro-optical device according to claim 1, wherein a pulse width of the first and second waveform selection signals is narrower than a pulse width of the transfer signal. A first waveform selection signal line for supplying the first waveform selection signal to the first waveform selection circuit; and a second waveform selection signal line for supplying the second waveform selection signal to the second waveform selection circuit;
The first and second waveform selection signal lines are disposed adjacent to each other,
4. The drive circuit for an electro-optical device according to claim 1, wherein transition of a pulse waveform of the first and second waveform selection signals is smoothed. 5. An image signal line for supplying the image signal to the sampling circuit;
5. The drive circuit of the electro-optical device according to claim 4, wherein the image signal line is disposed along the first waveform selection signal line and the second waveform selection signal line.   6. The drive circuit for an electro-optical device according to claim 4, wherein a transition of rising of the pulse waveform of the first and second waveform selection signals is in a range of 20 to 50 ns.   7. The drive circuit for an electro-optical device according to claim 4, wherein the transition of the falling edge of the pulse waveform of the first and second waveform selection signals is in the range of 20 to 50 ns. A plurality of data lines to which image signals are supplied, a plurality of scanning lines that intersect the plurality of data lines and that are supplied with scanning signals, and the data lines and the scanning lines are provided corresponding to the intersections. A drive circuit for an electro-optical device having switching means and pixel electrodes provided corresponding to the switching means,
A bidirectional shift register having an odd number of stages and supplying a transfer signal in a first or second transfer direction based on a clock signal;
The pulse width is limited by the pulse of the first waveform selection signal based on the input of the transfer signal output from the odd-numbered stage in the transfer direction of the bidirectional shift register and the first waveform selection signal. A first waveform selection circuit for outputting a scanning signal;
The pulse width is limited by the pulse of the second waveform selection signal based on the input of the transfer signal output from the even-numbered stage in the transfer direction of the bidirectional shift register and the second waveform selection signal. A second waveform selection circuit for outputting a scanning signal;
Comprising
A first waveform selection circuit to which a transfer signal output from the first stage in the first transfer direction of the bidirectional shift register is input, and an output from the first stage in the second transfer direction of the bidirectional shift register. The first waveform selection signal is input to both the first waveform selection circuit to which the transfer signal is input,
Regardless of whether the transfer direction of the bidirectional shift register is the first transfer direction or the second transfer direction, the pulse waveforms of the first waveform selection signal and the second waveform selection signal are the same. ,
The drive circuit of the electro-optical device, wherein the pulse of the first waveform selection signal does not overlap with the pulse of the second waveform selection signal.   An electro-optical device comprising the drive circuit for the electro-optical device according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 9. A plurality of data lines to which image signals are supplied, a plurality of scanning lines that intersect the plurality of data lines and that are supplied with scanning signals, and the data lines and the scanning lines are provided corresponding to the intersections. A driving method of an electro-optical device having a switching unit and a pixel electrode provided corresponding to the switching unit,
Pulsed by the pulse of the first waveform selection signal based on the input of the transfer signal and the first waveform selection signal output from the odd-numbered stage in the transfer direction of the bidirectional shift register having an odd number of stages. Outputting a sampling circuit drive signal with a limited width;
Based on the input of the transfer signal output from the even-numbered stage in the transfer direction of the bidirectional shift register and the second waveform selection signal, the pulse width is limited by the pulse of the second waveform selection signal Outputting a sampling circuit drive signal;
A sampling step of sampling the image signal based on the sampling circuit drive signal and supplying the sampled image signal to the data line;
Selecting the scan line, and the switching means electrically connected to the selected scan line,
Supplying the image signal sampled in the sampling step via the data line,
A step of outputting a sampling circuit drive signal based on a transfer signal output from the first stage in the first transfer direction of the bidirectional shift register; and a first stage in the second transfer direction of the bidirectional shift register. In the step of outputting the sampling circuit drive signal based on the output transfer signal, both the pulse width of the sampling circuit drive signal is limited by the pulse of the first waveform selection signal,
Regardless of the transfer direction of the transfer signal of the bidirectional shift register, the first waveform selection signal and the second waveform selection signal use pulses having the same waveform,
The method for driving an electro-optical device, wherein the first and second waveform selection signals use pulses that are alternately output without overlapping each other.   12. The driving method of the electro-optical device according to claim 11, wherein the sampling circuit driving signal is output based on a logical product or a negative logical product of the transfer signal and the first or second waveform selection signal.   13. The method of driving an electro-optical device according to claim 11 or 12, wherein a transition of a pulse waveform of the first and second waveform selection signals is smoothed.   14. The method of driving an electro-optical device according to claim 13, wherein transitions of rising edges of the pulse waveforms of the first and second waveform selection signals are in a range of 20 to 50 ns. 15. The driving method of the electro-optical device according to claim 13, wherein the transition of the falling edge of the pulse waveform of the first and second waveform selection signals is in a range of 20 to 50 ns.

Images