JP3823636B2 - Semiconductor chip module and manufacturing method thereof - Google Patents

Semiconductor chip module and manufacturing method thereof Download PDF

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Publication number
JP3823636B2
JP3823636B2 JP26892099A JP26892099A JP3823636B2 JP 3823636 B2 JP3823636 B2 JP 3823636B2 JP 26892099 A JP26892099 A JP 26892099A JP 26892099 A JP26892099 A JP 26892099A JP 3823636 B2 JP3823636 B2 JP 3823636B2
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semiconductor chip
columnar electrode
silicon substrate
chip module
manufacturing
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JP2001094033A (en
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伸治 脇坂
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
この発明は半導体チップモジュール及びその製造方法に関する。
【０００２】
【従来の技術】
例えばＭＣＭ(multi chip module)と呼ばれる半導体チップモジュールには、図１７に示すようなものがある。この半導体チップモジュールはシリコン基板１を備えている。シリコン基板１の上面の中央部には複数組の接続パッド２が設けられ、同上面の外周部には複数の外部接続端子３が設けられている。シリコン基板１上には複数の半導体チップ（ベアチップ）４がその下面に設けられた半田からなるバンプ電極５を接続パッド２に接合されて搭載されている。外部接続端子３にはリード６の一端部が接合されている。半導体チップ４、外部接続端子３及びリード６の一端部を含むシリコン基板１の上面全体にはエポキシ樹脂からなる封止膜７が設けられている。そして、図示していないが、この半導体チップモジュールは、リード６の他端部を回路基板上の接続端子に接合されることにより、回路基板上に実装される。
【０００３】
【発明が解決しようとする課題】
しかしながら、従来のこのような半導体チップモジュールでは、シリコン基板１の外側にリード６が突出することになるので、平面サイズが大きくなり、ひいては実装面積が大きくなるという問題があった。
この発明の課題は、半導体チップモジュールの平面サイズを小さくすることである。
【０００４】
【課題を解決するための手段】
請求項１記載の発明に係る半導体チップモジュールは、シリコン基板上にアルミニウムからなる複数の接続パッド及び該接続パッドのいずれかに接続されたアルミニウムからなる複数の外部接続端子を設け、前記シリコン基板上に複数の半導体チップを前記接続パッドに接合させて搭載し、前記外部接続端子上に形成された銅からなる金属層上に前記各半導体チップの高さと同じかそれ以上の高さの銅からなる柱状電極を設け、前記シリコン基板上の前記各半導体チップ及び前記柱状電極の周囲に前記シリコン基板と同一の平面サイズである封止膜を形成して、前記柱状電極の上面が前記封止膜の上面と面一となったものである。請求項５記載の発明に係る半導体チップモジュールの製造方法は、シリコン基板上に複数の接続パッド及び該接続パッドのいずれかに接続された複数の外部接続端子を形成し、前記外部接続端子上に搭載される複数の半導体チップの高さと同じかそれ以上の高さの柱状電極をメッキを行うことにより形成し、次に、前記シリコン基板上に前記各半導体チップを前記接続パッドに接合させて搭載し、前記シリコン基板上の前記各半導体チップ及び前記柱状電極の周囲に封止膜を形成するようにしたものである。この発明によれば、基板上に設けられた外部接続端子上に柱状電極を設けているので、基板の外側に外部接続用のリードを突出させる場合と比較して、平面サイズを小さくすることができる。
【０００５】
【発明の実施の形態】
（第１実施形態）
図１〜図８はそれぞれこの発明の第１実施形態における半導体チップモジュールの各製造工程を示したものである。そこで、これらの図を順に参照して、この実施形態における半導体チップモジュールの構造についてその製造方法と併せ説明する。まず、図１に示すように、ウエハ状態のシリコン基板１１の各半導体チップモジュール形成領域の上面の中央部にアルミニウムからなる複数組の接続パッド１２が形成されていると共に、同上面の外周部に同じくアルミニウムからなる複数の外部接続端子１３が形成され、その上面において接続パッド１２及び外部接続端子１３の各中央部を除く部分に絶縁膜１４が形成され、接続パッド１２及び外部接続端子１３の各中央部が絶縁膜１４に形成された開口部１５、１６を介して露出されたものを用意する。この場合、接続パッド１２及び外部接続端子１３は、シリコン基板１１の上面に形成されたアルミニウムからなる引き回し線（図示せず）を介して適宜に接続されている。
【０００６】
次に、図２に示すように、上面全体にスパッタ法によりチタンからなる第１金属層２１及び銅からなる第２金属層２２を形成する。次に、第２金属層２２の上面にメッキレジスト層２３を形成する。この場合、メッキレジスト層２３の外部接続端子１３に対応する部分には開口部２４が形成されている。次に、図３に示すように、第１及び第２金属層２１、２２をメッキ電流路として銅の電解メッキを行うことにより、メッキレジスト層２３の開口部２４内の第２金属層２２の上面に柱状電極２５を形成する。次に、メッキレジスト層２３を剥離する。次に、柱状電極２５をマスクとして第２及び第１金属層２２、２１の不要な部分をエッチングして除去すると、図４に示すように、柱状電極２５下にのみ第２及び第１金属層２２、２１が残存される。したがって、この状態では、外部接続端子１３上に第１及び第２金属層２１、２２を介して柱状電極２５が形成されている。
【０００７】
次に、図５に示すように、複数の半導体チップ（ベアチップ）３１を、その下面に設けられた半田からなるバンプ電極３２を接続パッド１２にリフローにより接合することにより、シリコン基板１１上に搭載する。ここで、柱状電極２５の高さは、シリコン基板１１上に搭載された半導体チップ３１の上面よりも高くなるように形成する。次に、図６に示すように、柱状電極２５及び半導体チップ３１を含むシリコン基板１１の上面全体にエポキシ樹脂からなる封止膜３３をスクリーン印刷法、ディスペンサ法、トランスファモールド法等により厚さが柱状電極２５の高さよりもやや厚くなるように形成する。したがって、この状態では、柱状電極２５の上面は封止膜３３によって覆われている。次に、封止膜３３の上面側を適宜に研磨することにより、図７に示すように、柱状電極２５の上面を露出させる。次に、ダイシング工程を経ると、図８に示すように、個々の半導体チップモジュールが得られる。
【０００８】
このようにして得られた半導体チップモジュールでは、シリコン基板１１上に設けられた外部接続端子１３上に柱状電極２５を設けているので、シリコン基板の外側に外部接続用のリードを突出させる場合と比較して、平面サイズを小さくすることができ、ひいては実装面積を小さくすることができる。この場合、図示していないが、柱状電極２５の露出面を回路基板上の接続端子に該接続端子上に予め設けられた半田（ペースト）を介して接合するようにしてもよく、また柱状電極２５の露出面を回路基板上の接続端子に異方性導電接着剤を介して接合するようにしてもよい。
【０００９】
（第２実施形態）
図９〜図１４はそれぞれこの発明の第２実施形態における半導体チップモジュールの各製造工程を示したものである。そこで、これらの図を順に参照して、この実施形態における半導体チップモジュールの構造についてその製造方法と併せ説明する。まず、図９に示すように、ウエハ状態のシリコン基板４１の各半導体チップモジュール形成領域の上面の外周部に複数の接続パッド４２が形成され、その上面において接続パッド４２の中央部を除く部分に絶縁膜４３が形成され、接続パッド４２の中央部が絶縁膜４３に形成された開口部４４を介して露出されたものを用意する。この場合、シリコン基板４１の上面には、各接続パッド４２、４２間の領域に、集積回路が形成されており、その入出力端子が各接続パッド４２に接続されている。
【００１０】
次に、図１０に示すように、上面全体に配線形成用層４５を形成する。この配線形成用層４５は、例えば、スパッタ法により形成した銅層上に電解メッキにより銅層を厚付けしたものからなっている。次に、配線形成用層４５の上面に配線形成用のレジストパターン４６を形成する。この場合、レジストパターン４６は、例えば、外部接続端子４２上から半導体チップ接合用接続パッド形成領域及び外部接続端子形成領域にかけて適宜に形成されている。次に、レジストパターン４６をマスクとして配線形成用層４５の不要な部分をエッチングして除去すると、図１１に示すように、シリコン基板４１の各半導体チップモジュール形成領域における絶縁膜４３の上面の中央部に複数組の接続パッド４７が形成されると共に、同上面の外周部に、各接続パッド４２に接続された引き回し線４９及び該引き回し線４９に一体に形成された外部接続端子４８が形成される。また、この場合、、各接続パッド４７は、図示しないが、引き回し線４９のような引き回し線に接続されており、該引き回し線を介してそれぞれ対応する接続パッド４２に接続されている。次に、レジストパターン４６を剥離する。
【００１１】
次に、図１２に示すように、上面全体にスパッタ法により銅からなる金属層５１を形成する。次に、金属層５１の上面にメッキレジスト層５２を形成する。この場合、メッキレジスト層５２の外部接続端子４８に対応する部分には開口部５３が形成されている。次に、図１３に示すように、金属層５１をメッキ電流路として銅の電解メッキを行うことにより、メッキレジスト層５２の開口部５３内の金属層５１の上面に柱状電極５４を形成する。次に、メッキレジスト層５２を剥離する。次に、柱状電極５４をマスクとして金属層５１の不要な部分をエッチングして除去すると、図１４に示すように、柱状電極５４下にのみ金属層５１が残存される。したがって、この状態では、外部接続端子４８上に金属層５１を介して柱状電極５４が形成されている。また、接続パッド４７が露出される。以下の工程は、図５〜図８に示す場合と同じであるので、省略する。
【００１２】
なお、例えば、図１５に示すこの発明の第３実施形態のように、柱状電極２５の上面を露出させるための研磨工程において、柱状電極２５の上面を露出させると共に、半導体チップ３１のチップ本体の上面を露出させるようにしてもよい。このようにした場合には、モジュール厚さを薄くすることができ、また半導体チップ３１のチップ本体の上面からの放熱性を良くすることができる。また、例えば、図７に示す工程後に、図１６に示すこの発明の第４実施形態のように、柱状電極２５の上面に半田ボール６１を形成するようにしてもよい。また、図２に示すメッキレジスト層２３としてポジ型フォトレジストを用い、開口部２４に対応する位置を露光して開口部２４を形成し、該開口部２４内に柱状電極２５を形成した後、図３の状態で、ポジ型フォトレジストの各接続パッド１２に対応する箇所を除く部分を露光し、露光した分を除去することにより各接続パッド１２に対応する部分のフォトレジストのみを残存し、この残存したフォトレジストをマスクにして、各接続パッド１２上にも第１及び第２金属層２１、２２を形成するようにしてもよい。さらに、半導体チップ３１としては、ベアチップに限らず、ＣＳＰ(Chip Size Package)と呼ばれる半導体パッケージ等であってもよい。
【００１３】
【発明の効果】
以上説明したように、この発明によれば、基板上に設けられた外部接続端子上に柱状電極を設けているので、基板の外側にリードを突出させる場合と比較して、平面サイズを小さくすることができ、ひいては実装面積を小さくすることができる。
【図面の簡単な説明】
【図１】この発明の第１実施形態における半導体装置の製造に際し、当初用意したものの断面図。
【図２】図１に続く製造工程の断面図。
【図３】図２に続く製造工程の断面図。
【図４】図３に続く製造工程の断面図。
【図５】図４に続く製造工程の断面図。
【図６】図５に続く製造工程の断面図。
【図７】図６に続く製造工程の断面図。
【図８】図７に続く製造工程の断面図。
【図９】この発明の第２実施形態における半導体装置の製造に際し、当初用意したものの断面図。
【図１０】図９に続く製造工程の断面図。
【図１１】図１０に続く製造工程の断面図。
【図１２】図１１に続く製造工程の断面図。
【図１３】図１２に続く製造工程の断面図。
【図１４】図１３に続く製造工程の断面図。
【図１５】この発明の第３実施形態を説明するために示す断面図。
【図１６】この発明の第４実施形態を説明するために示す断面図。
【図１７】従来の半導体装置の一例の断面図。
【符号の説明】
１１ シリコン基板
１２ 接続パッド
１３ 外部接続端子
２５ 柱状電極
３１ 半導体チップ
３３ 封止膜[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor chip module and a manufacturing method thereof.
[0002]
[Prior art]
For example, a semiconductor chip module called an MCM (multi chip module) is shown in FIG. This semiconductor chip module includes a silicon substrate 1. A plurality of sets of connection pads 2 are provided at the center of the upper surface of the silicon substrate 1, and a plurality of external connection terminals 3 are provided at the outer periphery of the upper surface. A plurality of semiconductor chips (bare chips) 4 are mounted on the silicon substrate 1 by bonding bump electrodes 5 made of solder provided on the lower surface thereof to the connection pads 2. One end of a lead 6 is joined to the external connection terminal 3. A sealing film 7 made of an epoxy resin is provided on the entire top surface of the silicon substrate 1 including the semiconductor chip 4, the external connection terminals 3, and one ends of the leads 6. Although not shown, the semiconductor chip module is mounted on the circuit board by bonding the other end of the lead 6 to a connection terminal on the circuit board.
[0003]
[Problems to be solved by the invention]
However, in such a conventional semiconductor chip module, since the lead 6 protrudes outside the silicon substrate 1, there is a problem that the planar size is increased and the mounting area is increased.
An object of the present invention is to reduce the planar size of a semiconductor chip module.
[0004]
[Means for Solving the Problems]
The semiconductor chip module according to claim 1 is provided with a plurality of connection pads made of aluminum on a silicon substrate and a plurality of external connection terminals made of aluminum connected to any one of the connection pads. A plurality of semiconductor chips bonded to the connection pads and mounted on a metal layer made of copper formed on the external connection terminals and made of copper having a height equal to or higher than the height of each semiconductor chip. A columnar electrode is provided, a sealing film having the same planar size as the silicon substrate is formed around each semiconductor chip and the columnar electrode on the silicon substrate, and an upper surface of the columnar electrode is the sealing film It is flush with the top surface. According to a fifth aspect of the present invention, there is provided a semiconductor chip module manufacturing method comprising: forming a plurality of connection pads and a plurality of external connection terminals connected to any one of the connection pads on a silicon substrate; A columnar electrode having a height equal to or higher than the height of a plurality of semiconductor chips to be mounted is formed by plating, and then each semiconductor chip is mounted on the silicon substrate by bonding to the connection pads. A sealing film is formed around each of the semiconductor chips and the columnar electrodes on the silicon substrate. According to the present invention, since the columnar electrode is provided on the external connection terminal provided on the substrate, the planar size can be reduced as compared with the case where the external connection lead protrudes outside the substrate. it can.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
1 to 8 show respective manufacturing steps of the semiconductor chip module according to the first embodiment of the present invention. The structure of the semiconductor chip module in this embodiment will be described together with its manufacturing method with reference to these drawings in order. First, as shown in FIG. 1, a plurality of sets of connection pads 12 made of aluminum are formed at the center of the upper surface of each semiconductor chip module formation region of the silicon substrate 11 in the wafer state, and the outer peripheral portion of the upper surface is formed. Similarly, a plurality of external connection terminals 13 made of aluminum are formed, and an insulating film 14 is formed on the upper surface of each of the connection pads 12 and the external connection terminals 13 except for the central portions thereof. The one whose central portion is exposed through the openings 15 and 16 formed in the insulating film 14 is prepared. In this case, the connection pad 12 and the external connection terminal 13 are appropriately connected via a lead wire (not shown) made of aluminum formed on the upper surface of the silicon substrate 11.
[0006]
Next, as shown in FIG. 2, a first metal layer 21 made of titanium and a second metal layer 22 made of copper are formed on the entire upper surface by sputtering. Next, a plating resist layer 23 is formed on the upper surface of the second metal layer 22. In this case, an opening 24 is formed in a portion corresponding to the external connection terminal 13 of the plating resist layer 23. Next, as shown in FIG. 3, by performing electrolytic plating of copper using the first and second metal layers 21 and 22 as plating current paths, the second metal layer 22 in the opening 24 of the plating resist layer 23 is formed. A columnar electrode 25 is formed on the upper surface. Next, the plating resist layer 23 is peeled off. Next, when unnecessary portions of the second and first metal layers 22 and 21 are removed by etching using the columnar electrode 25 as a mask, the second and first metal layers are only under the columnar electrode 25 as shown in FIG. 22 and 21 remain. Therefore, in this state, the columnar electrode 25 is formed on the external connection terminal 13 via the first and second metal layers 21 and 22.
[0007]
Next, as shown in FIG. 5, a plurality of semiconductor chips (bare chips) 31 are mounted on the silicon substrate 11 by bonding the bump electrodes 32 made of solder provided on the lower surface thereof to the connection pads 12 by reflow. To do. Here, the columnar electrode 25 is formed to be higher than the upper surface of the semiconductor chip 31 mounted on the silicon substrate 11. Next, as shown in FIG. 6, a sealing film 33 made of an epoxy resin is formed on the entire upper surface of the silicon substrate 11 including the columnar electrodes 25 and the semiconductor chip 31 by a screen printing method, a dispenser method, a transfer mold method or the like. The columnar electrode 25 is formed to be slightly thicker than the height. Therefore, in this state, the upper surface of the columnar electrode 25 is covered with the sealing film 33. Next, by appropriately polishing the upper surface side of the sealing film 33, the upper surface of the columnar electrode 25 is exposed as shown in FIG. Next, through a dicing step, individual semiconductor chip modules are obtained as shown in FIG.
[0008]
In the semiconductor chip module obtained in this way, the columnar electrode 25 is provided on the external connection terminal 13 provided on the silicon substrate 11, so that external connection leads protrude from the outside of the silicon substrate. In comparison, the planar size can be reduced, and consequently the mounting area can be reduced. In this case, although not shown, the exposed surface of the columnar electrode 25 may be joined to the connection terminal on the circuit board via solder (paste) provided in advance on the connection terminal. The 25 exposed surfaces may be bonded to connection terminals on the circuit board via an anisotropic conductive adhesive.
[0009]
(Second Embodiment)
9 to 14 show respective manufacturing steps of the semiconductor chip module according to the second embodiment of the present invention. The structure of the semiconductor chip module in this embodiment will be described together with its manufacturing method with reference to these drawings in order. First, as shown in FIG. 9, a plurality of connection pads 42 are formed on the outer peripheral portion of the upper surface of each semiconductor chip module formation region of the silicon substrate 41 in the wafer state. The insulating film 43 is formed, and the connection pad 42 is exposed through the opening 44 formed in the insulating film 43. In this case, an integrated circuit is formed on the upper surface of the silicon substrate 41 in a region between the connection pads 42 and 42, and input / output terminals thereof are connected to the connection pads 42.
[0010]
Next, as shown in FIG. 10, a wiring formation layer 45 is formed on the entire top surface. The wiring forming layer 45 is made of, for example, a copper layer formed by electrolytic plating on a copper layer formed by sputtering. Next, a resist pattern 46 for forming a wiring is formed on the upper surface of the wiring forming layer 45. In this case, the resist pattern 46 is appropriately formed, for example, from the external connection terminal 42 to the semiconductor chip bonding connection pad formation region and the external connection terminal formation region. Next, when unnecessary portions of the wiring formation layer 45 are removed by etching using the resist pattern 46 as a mask, the center of the upper surface of the insulating film 43 in each semiconductor chip module formation region of the silicon substrate 41 is removed as shown in FIG. A plurality of sets of connection pads 47 are formed in the part, and lead lines 49 connected to the connection pads 42 and external connection terminals 48 formed integrally with the lead lines 49 are formed on the outer peripheral part of the upper surface. The In this case, each connection pad 47 is connected to a lead line such as a lead line 49 (not shown), and is connected to the corresponding connection pad 42 via the lead line. Next, the resist pattern 46 is peeled off.
[0011]
Next, as shown in FIG. 12, a metal layer 51 made of copper is formed on the entire upper surface by sputtering. Next, a plating resist layer 52 is formed on the upper surface of the metal layer 51. In this case, an opening 53 is formed in a portion corresponding to the external connection terminal 48 of the plating resist layer 52. Next, as shown in FIG. 13, columnar electrodes 54 are formed on the upper surface of the metal layer 51 in the openings 53 of the plating resist layer 52 by performing electrolytic plating of copper using the metal layer 51 as a plating current path. Next, the plating resist layer 52 is peeled off. Next, when unnecessary portions of the metal layer 51 are removed by etching using the columnar electrode 54 as a mask, the metal layer 51 remains only under the columnar electrode 54 as shown in FIG. Therefore, in this state, the columnar electrode 54 is formed on the external connection terminal 48 via the metal layer 51. Further, the connection pad 47 is exposed. The following steps are the same as those shown in FIGS.
[0012]
For example, as in the third embodiment of the present invention shown in FIG. 15, in the polishing step for exposing the upper surface of the columnar electrode 25, the upper surface of the columnar electrode 25 is exposed and the chip body of the semiconductor chip 31 is exposed. The upper surface may be exposed. In this case, the module thickness can be reduced, and the heat dissipation from the upper surface of the chip body of the semiconductor chip 31 can be improved. Further, for example, after the step shown in FIG. 7, the solder balls 61 may be formed on the upper surface of the columnar electrode 25 as in the fourth embodiment of the present invention shown in FIG. Further, a positive photoresist is used as the plating resist layer 23 shown in FIG. 2, a position corresponding to the opening 24 is exposed to form the opening 24, and the columnar electrode 25 is formed in the opening 24. In the state of FIG. 3, the portion except the portion corresponding to each connection pad 12 of the positive photoresist is exposed, and only the portion of the photoresist corresponding to each connection pad 12 remains by removing the exposed portion, The first and second metal layers 21 and 22 may also be formed on the connection pads 12 using the remaining photoresist as a mask. Further, the semiconductor chip 31 is not limited to a bare chip but may be a semiconductor package called a CSP (Chip Size Package).
[0013]
【The invention's effect】
As described above, according to the present invention, since the columnar electrode is provided on the external connection terminal provided on the substrate, the planar size is reduced as compared with the case where the lead is projected outside the substrate. As a result, the mounting area can be reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device initially prepared for manufacturing a semiconductor device according to a first embodiment of the invention.
FIG. 2 is a cross-sectional view of the manufacturing process subsequent to FIG.
FIG. 3 is a cross-sectional view of the manufacturing process following FIG. 2;
FIG. 4 is a cross-sectional view of the manufacturing process following FIG. 3;
FIG. 5 is a cross-sectional view of the manufacturing process following FIG. 4;
6 is a cross-sectional view of the manufacturing process following FIG. 5. FIG.
7 is a cross-sectional view of a manufacturing step that follows FIG. 6. FIG.
FIG. 8 is a cross-sectional view of the manufacturing process following FIG. 7;
FIG. 9 is a cross-sectional view of a semiconductor device initially prepared for manufacturing a semiconductor device according to a second embodiment of the invention.
10 is a cross-sectional view of a manufacturing step that follows FIG. 9; FIG.
FIG. 11 is a cross-sectional view of the manufacturing process following FIG. 10;
FIG. 12 is a cross-sectional view of the manufacturing process following FIG. 11;
13 is a cross-sectional view of a manufacturing step that follows FIG. 12. FIG.
FIG. 14 is a cross-sectional view of the manufacturing process following FIG. 13;
FIG. 15 is a sectional view for explaining a third embodiment of the invention.
FIG. 16 is a sectional view for explaining a fourth embodiment of the invention.
FIG. 17 is a cross-sectional view of an example of a conventional semiconductor device.
[Explanation of symbols]
11 Silicon substrate 12 Connection pad 13 External connection terminal 25 Columnar electrode 31 Semiconductor chip 33 Sealing film

Claims (10)

シリコン基板上にアルミニウムからなる複数の接続パッド及び該接続パッドのいずれかに接続されたアルミニウムからなる複数の外部接続端子が設けられ、前記シリコン基板上に複数の半導体チップが前記接続パッドに接合されて搭載され、前記外部接続端子上に形成された銅からなる金属層上に前記各半導体チップの高さと同じかそれ以上の高さの銅からなる柱状電極が設けられ、前記シリコン基板上の前記各半導体チップ及び前記柱状電極の周囲に前記シリコン基板と同一の平面サイズである封止膜が形成されていて、前記柱状電極の上面が前記封止膜の上面と面一となっていることを特徴とする半導体チップモジュール。A plurality of connection pads made of aluminum and a plurality of external connection terminals made of aluminum connected to any one of the connection pads are provided on the silicon substrate, and a plurality of semiconductor chips are bonded to the connection pads on the silicon substrate. A columnar electrode made of copper having a height equal to or higher than the height of each semiconductor chip is provided on a metal layer made of copper formed on the external connection terminal, and A sealing film having the same planar size as the silicon substrate is formed around each semiconductor chip and the columnar electrode, and the upper surface of the columnar electrode is flush with the upper surface of the sealing film. A featured semiconductor chip module. 請求項１記載の発明において、前記接続パッド及び前記外部接続端子は、前記シリコン基板上の周囲に設けられた複数の接続パッドに引き回し線を介して接続されていることを特徴とする半導体チップモジュール。  2. The semiconductor chip module according to claim 1, wherein the connection pad and the external connection terminal are connected to a plurality of connection pads provided around the silicon substrate via lead wires. . 請求項１または２記載の発明において、前記柱状電極の上面及び前記半導体チップの上面が前記封止膜の上面と面一となっていることを特徴とする半導体チップモジュール。  3. The semiconductor chip module according to claim 1, wherein an upper surface of the columnar electrode and an upper surface of the semiconductor chip are flush with an upper surface of the sealing film. 請求項３記載の発明において、前記柱状電極の上面に半田ボールが設けられていることを特徴とする半導体チップモジュール。  4. The semiconductor chip module according to claim 3, wherein a solder ball is provided on the upper surface of the columnar electrode. シリコン基板上に複数の接続パッド及び該接続パッドのいずれかに接続された複数の外部接続端子を形成し、前記外部接続端子上に搭載される複数の半導体チップの高さと同じかそれ以上の高さの柱状電極をメッキを行うことにより形成し、次に、前記シリコン基板上に前記各半導体チップを前記接続パッドに接合させて搭載し、前記シリコン基板上の前記各半導体チップ及び前記柱状電極の周囲に封止膜を形成することを特徴とする半導体チップモジュールの製造方法。A plurality of connection pads and a plurality of external connection terminals connected to any of the connection pads are formed on the silicon substrate, and the height is equal to or higher than the height of the plurality of semiconductor chips mounted on the external connection terminals. was formed by performing plating to the columnar electrodes, then the mounting with the respective semiconductor chip is bonded to the connection pads on the silicon substrate, the respective semiconductor chip and the columnar electrode on the silicon substrate A method of manufacturing a semiconductor chip module, comprising forming a sealing film around the periphery. 請求項５記載の発明において、前記接続パッド及び前記外部接続端子は、前記シリコン基板上の周囲に設けられた複数の接続パッドに引き回し線を介して接続させて形成することを特徴とする半導体チップモジュールの製造方法。  6. The semiconductor chip according to claim 5, wherein the connection pads and the external connection terminals are formed by being connected to a plurality of connection pads provided around the silicon substrate through lead lines. Module manufacturing method. 請求項５または６記載の発明において、前記封止膜の上面側を研磨することにより、前記柱状電極の上面を露出させることを特徴とする半導体チップモジュールの製造方法。  7. The method of manufacturing a semiconductor chip module according to claim 5, wherein the upper surface of the columnar electrode is exposed by polishing the upper surface side of the sealing film. 請求項５または６記載の発明において、前記封止膜の上面側を研磨することにより、前記柱状電極の上面及び前記各半導体チップの上面を露出させることを特徴とする半導体チップモジュールの製造方法。7. The method of manufacturing a semiconductor chip module according to claim 5, wherein the upper surface side of the columnar electrode and the upper surface of each semiconductor chip are exposed by polishing the upper surface side of the sealing film. 請求項７または８記載の発明において、前記柱状電極の上面に半田ボールを形成することを特徴とする半導体チップモジュールの製造方法。  9. The method of manufacturing a semiconductor chip module according to claim 7, wherein a solder ball is formed on the upper surface of the columnar electrode. 請求項５〜９のいずれかに記載の発明において、前記外部接続端子上に金属層を形成し、該金属層上に前記柱状電極を形成することを特徴とする半導体チップモジュールの製造方法。  10. The method of manufacturing a semiconductor chip module according to claim 5, wherein a metal layer is formed on the external connection terminal, and the columnar electrode is formed on the metal layer.
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