JP4325595B2 - LIGHT EMITTING DEVICE AND ELECTRONIC DEVICE - Google Patents

Description

  The present invention relates to a light-emitting device and an electronic device, and more particularly, to a light-emitting device including a current-driven light-emitting element such as an organic electroluminescence element and an electronic device including the light-emitting device.

  An electroluminescence device provided between a pixel electrode and a counter electrode and having a light emitting layer for each pixel that emits light by a current flowing between the pixel electrode and the counter electrode is expected as a next-generation display device. (For example, refer to Patent Document 1).

International Publication Number WO98 / 36407 Pamphlet

However, in a device that emits light when a current flows, such as the above-described electroluminescence device, the luminance depends on the current level, and therefore it is necessary to optimize the wiring structure and wiring layout for supplying current or driving voltage to the pixel. There is.
The present invention has been made in view of the above circumstances, and provides an electro-optical device capable of stably supplying a driving voltage or current to each pixel and an electronic apparatus including the electro-optical device. Objective.

In order to solve the above problems, a light emitting device of the present invention includes a first electrode group region in which a plurality of first electrodes and a transistor connected to each of the plurality of first electrodes are provided on a substrate. A second electrode provided in common to the plurality of first electrodes, a light emitting element provided between each of the plurality of first electrodes and the second electrode, and the first electrode A drive circuit for supplying an electric signal to the transistor, a first wiring for supplying a power supply voltage to the first electrode via the transistor, and a second electrode , provided outside the region ; A second wiring provided so as to overlap the entire surface and in contact with a region overlapping the second electrode, and the second wiring provided in contact with the second electrode, And extending along a plurality of sides forming the outer periphery of the base body Is provided between the outer circumference and the drive circuit of the substrate, wherein the.

  In the light emitting device according to the present invention, in the above light emitting device, the first wiring extends along a plurality of sides forming the outer periphery of the base, and between the second wiring and the drive circuit. It has the part provided in this.

  In the light-emitting device of the present invention, in the above light-emitting device, the second wiring extends along at least three sides among a plurality of sides forming an outer periphery of the base.

  The light-emitting device of the present invention is characterized in that, in the light-emitting device, the line width of the second wiring is wider than the line width of the first wiring.

  The light-emitting device of the present invention is characterized in that, in the light-emitting device, the line width of the second wiring is formed wider than the line width of the first wiring over the entire wiring. To do.

  In the light emitting device of the present invention, in the above light emitting device, a connection portion between the second wiring and the second electrode is between the first electrode group region and a plurality of sides forming the outer periphery of the base. It is provided in.

  In the light emitting device of the present invention, in the above light emitting device, the connecting portion between the second wiring and the second electrode is at least one of a plurality of sides forming an outer periphery of the first electrode group region and the base. It is provided between the three sides.

  Further, the light emitting device of the present invention is the above light emitting device, wherein each of the plurality of light emitting elements is provided between a corresponding first electrode and the second electrode among the plurality of first electrodes, A light-emitting layer that emits light when a voltage is applied between the corresponding first electrode and the second electrode, and the plurality of light-emitting elements include a plurality of types of light-emitting elements having different emission colors of the light-emitting layer. In addition, the first wiring is wired for each emission color.

  The light-emitting device of the present invention includes a plurality of control lines that transmit the electrical signal to the transistor in the light-emitting device, and the plurality of control lines include the first wiring and the second wiring. At least one of them is arranged so as not to intersect at least on the substrate.

  The light emitting device of the present invention is the above light emitting device, wherein the control line includes a scanning line for supplying a scanning signal to the transistor and a data line for supplying a data signal to the transistor. It is characterized by that.

  The light-emitting device of the present invention is characterized in that, in the light-emitting device, the light-emitting element is formed by laminating a hole injection / transport layer and a light-emitting layer made of an organic electroluminescent material. To do.

  In order to solve the above-described problems, an electro-optical device according to the present invention includes a plurality of first electrodes provided in an effective region on a base, and a second electrode provided in common to the plurality of first electrodes. A plurality of electro-optic elements provided between the plurality of first electrodes and the second electrode, a first wiring for supplying a power supply voltage to the first electrode, and the second electrode And a second wiring provided between at least one side of the plurality of sides forming the outer periphery of the base body and the effective region, and an occupied area of the second wiring on the base body Is larger than the occupied area on the base of the portion of the first wiring provided outside the effective region.

  Like the above electro-optical device, by increasing the occupation area on the base of the second wiring connected to the second electrode that is provided in common to the plurality of first electrodes, Wiring resistance is reduced and the current level of the current supplied to the plurality of electro-optic elements is stabilized.

  When it is necessary to minimize the area outside the effective region, the occupied area of the second wiring on the base is determined by the first wiring for supplying a power supply voltage to the first electrode. Of these, the area provided outside the effective area is preferably larger than the area occupied on the substrate.

  In the above electro-optical device, the “effective area” corresponds to, for example, an area having an electro-optical function or a display area.

  In the above electro-optical device, it is preferable that the second wiring includes a portion where a line width of the second wiring is formed wider than that of the first wiring.

  In the electro-optical device, the second wiring may have a line width wider than that of the first wiring over the entire wiring.

  In the electro-optical device, each of the plurality of electro-optical elements is provided between a corresponding first electrode and the second electrode among the plurality of first electrodes, and the corresponding first electrode and the first electrode A light-emitting layer that emits light when a voltage is applied between the two electrodes, and the plurality of electro-optical elements include a plurality of types of electro-optical elements having different emission colors of the light-emitting layer, The wiring may be wired for each emission color.

  In the above electro-optical device, the line width of the second wiring outside the effective area is the line width of the portion outside the effective area of the first wiring wired for each type of the electro-optical element. It may be larger than the most widely formed.

  In the electro-optical device, a dummy region is provided between the effective region and at least one side of a plurality of sides forming an outer periphery of the base, and the first wiring and the second wiring are It may be formed between the dummy region and at least one of a plurality of sides forming the outer periphery of the substrate.

  In the above electro-optical device, the second electrode may be formed so as to cover at least the effective region and the dummy region.

  In the electro-optical device, the connection portion between the second wiring and the second electrode is provided between the effective region and at least three sides among a plurality of sides forming the outer periphery of the base. Is preferred.

  Thus, problems such as current unevenness are reduced by increasing the area of the connection portion between the second electrode and the second wiring.

  In the above electro-optical device, each of the plurality of first electrodes includes a plurality of control lines that are included in the corresponding pixel circuit provided in the effective region and transmit a signal that controls the pixel circuit. The plurality of control lines are preferably arranged so as not to intersect at least one of the first wiring and the second wiring on at least the base.

  When the control line intersects the first wiring or the second wiring, a parasitic capacitance is generated between the first wiring or the second wiring and the control line, and is transmitted to the control line. However, the control line and the first wiring or the second wiring are arranged so as not to intersect with each other as described above. Problems such as delay and dullness of the signal transmitted on the line are reduced.

  In the electro-optical device, the control line may include a scanning line for supplying a scanning signal to the pixel circuit and a data line for supplying a data signal to the pixel circuit.

  In the above electro-optical device, the electro-optical element may be formed by laminating a hole injection / transport layer and a light emitting layer made of an organic electroluminescent material.

  According to another aspect of the invention, there is provided an electronic apparatus including the above electro-optical device.

  The wiring board of the present invention is for an electro-optical device including an electro-optical element provided between each of a plurality of first electrodes and a second electrode provided in common to the plurality of first electrodes. A plurality of first electrodes provided on a substrate, a first wiring for supplying a power supply voltage to the first electrode, and a first electrode for connection to the second electrode The second wiring is disposed outside an effective region in which the plurality of first electrodes are provided, and an occupied area of the second wiring on the base is the first wiring Of the portion of the wiring, the portion provided outside the effective region is larger than the occupied area on the substrate.

  Hereinafter, an electro-optical device and an electronic apparatus according to an embodiment of the invention will be described in detail with reference to the drawings. Each drawing referred to in the following description has a different scale for each layer and each member so that each layer and each member can be recognized on the drawing. FIG. 1 is a diagram schematically showing a wiring structure of an electro-optical device according to an embodiment of the present invention.

  The electro-optical device 1 shown in FIG. 1 is an active matrix organic EL device using a thin film transistor as a switching element. The electro-optical device 1 according to the present embodiment illustrated in FIG. 1 includes a plurality of scanning lines 101, a plurality of signal lines 102 extending in a direction intersecting the scanning lines 101, and a plurality of light emitting elements extending in parallel with the signal lines 102. A power supply wiring 103 is wired, and a pixel region A is provided near each intersection of the scanning line 101 and the signal line 102. The scanning line 101 and the signal line 102 correspond to part of the control line in the present invention.

  Each signal line 102 is connected to a data side driving circuit 104 including a shift register, a level shifter, a video line, and an analog switch. Each signal line 102 is connected to an inspection circuit 106 including a thin film transistor. Further, each scanning line 101 is connected to a scanning side driving circuit 105 including a shift register and a level shifter.

  Each pixel area A includes a switching thin film transistor 112, a storage capacitor Cap, a current thin film transistor 123, a pixel electrode (first electrode) 111, a light emitting layer 110, and a cathode (second electrode) 12. Is provided. The switching thin film transistor 112 has a gate electrode connected to the scanning line 101 and is driven according to a scanning signal supplied from the scanning line 101 to be turned on or off. The holding capacitor Cap holds an image signal supplied from the signal line 102 via the switching thin film transistor 112.

  The gate electrode of the current thin film transistor 123 is connected to the switching thin film transistor 112 and the storage capacitor Cap, and an image signal held by the storage capacitor Cap is supplied to the gate electrode. The pixel electrode 111 is connected to the current thin film transistor 123. When the pixel electrode 111 is electrically connected to the light emission power supply wiring 103 via the current thin film transistor 123, a drive current flows from the light emission power supply wiring 103. The light emitting layer 110 is sandwiched between the pixel electrode 111 and the cathode 12.

  The light emitting layer 110 includes three types of light emitting layers: a light emitting layer 110R that emits red light, a light emitting layer 110G that emits green light, and a light emitting layer 110B that emits blue light, and each of the light emitting layers 110R, 110G, and 110B. Are arranged in stripes. Light emitting power supply wirings 103R, 103G, and 103B connected to the light emitting layers 110R, 110G, and 110B through the current thin film transistor 123 are connected to the light emitting power supply circuit 132, respectively. The reason why the light-emitting power supply wirings 103R, 103G, and 103B are wired for each color is that the driving potentials of the light-emitting layers 110R, 110G, and 110B are different for each color.

In the electro-optical device according to the present embodiment, the first capacitance C ₁ is formed between the cathode 12 and the light-emitting power supply wirings 103R, 103G, and 103B. When the electro-optical device 1 is driven, charges are accumulated in the _first capacitance C ₁ . When the potential of the driving current flowing through each light emitting power supply wiring 103 changes during driving of the electro-optical device 1, the accumulated charge is discharged to each light emitting power supply wiring 103 to suppress the potential fluctuation of the driving current. . Thereby, the image display of the electro-optical device 1 can be kept normal.

  In the electro-optical device 1, when the scanning signal is supplied from the scanning line 101 and the switching thin film transistor 112 is turned on, the potential of the signal line 102 at that time is held in the holding capacitor Cap and held in the holding capacitor Cap. The on / off state of the current thin film transistor 123 is determined in accordance with the applied potential. Then, a driving current flows from the light emitting power supply wirings 103R, 103G, and 103B to the pixel electrode 111 through the channel of the current thin film transistor 123, and further a current flows to the cathode 12 through the light emitting layers 110R, 110G, and 110B. At this time, light emission corresponding to the amount of current flowing through the light emitting layer 110 is obtained from the light emitting layer 110.

  Next, a specific configuration of the electro-optical device 1 according to the present embodiment will be described with reference to FIGS. 2 is a schematic plan view of the electro-optical device according to the present embodiment, FIG. 3 is a cross-sectional view taken along the line AA ′ in FIG. 2, and FIG. 4 is taken along the line BB ′ in FIG. It is sectional drawing which follows. As shown in FIG. 2, the electro-optical device 1 according to this embodiment includes a substrate 2, a pixel electrode group region (not shown), a light-emitting power supply wiring 103 (103R, 103G, 103B), and a display pixel unit 3 (one point in the figure). It is roughly composed of a chain line).

  The substrate 2 is a transparent substrate made of, for example, glass. The pixel electrode group region is a region in which pixel electrodes (not shown) connected to the current thin film transistor 123 shown in FIG. As shown in FIG. 2, the light emission power supply wiring 103 (103R, 103G, 103B) is arranged around the pixel electrode group region and connected to each pixel electrode. The display pixel unit 3 is located at least on the pixel electrode group region and has a substantially rectangular shape in plan view. The display pixel unit 3 includes an actual display area 4 (within a two-dot chain line in the figure) at the center and a dummy area 5 (one point) arranged around the actual display area 4 (also referred to as an effective display area). And a region between a chain line and a two-dot chain line).

  Further, the scanning line driving circuit 105 described above is arranged on both sides of the actual display area 4 in the drawing. The scanning line driving circuit 105 is provided below the dummy area 5 (on the substrate 2 side). Further, a scanning line driving circuit control signal wiring 105 a and a scanning line driving circuit power supply wiring 105 b connected to the scanning line driving circuit 105 are provided below the dummy region 5. Furthermore, the above-described inspection circuit 106 is arranged on the upper side of the actual display area 4 in the drawing. The inspection circuit 106 is provided on the lower side (substrate side 2) of the dummy area 5, and the inspection circuit 106 can inspect the quality and defects of the electro-optical device during production or at the time of shipment. it can.

  As shown in FIG. 2, the light-emitting power supply wirings 103 </ b> R, 103 </ b> G, and 103 </ b> B are disposed around the dummy region 5. Each light-emitting power supply wiring 103R, 103G, 103B extends from the lower side of the substrate 2 in FIG. 2 along the scanning line drive circuit control signal wiring 105b in FIG. 2, and the scanning line drive circuit power supply wiring 105b. Is bent from the position where it is interrupted, extends along the outside of the dummy area 5, and is connected to a pixel electrode (not shown) in the actual display area 4. Further, a cathode wiring 12 a connected to the cathode 12 is formed on the substrate 2. The cathode wiring 12a is formed in a substantially U shape in plan view so as to surround the light emitting power wirings 103R, 103G, and 103B.

  Thus, the real display area 4 and the dummy area 5 are formed so as to be surrounded by the cathode wiring 12a and the light-emitting power supply wirings 103R, 103G, and 103B. A plurality of scanning lines 101 shown in FIG. 1 are arranged, and signal lines 102 are arranged so as to extend in a direction intersecting with the scanning lines 101. That is, the scanning line 101 and the signal line 102 are wired on the substrate 2 so that the three directions are taken in by the cathode wiring 12a and the light-emitting power supply wirings 103R, 103G, and 103B.

  Here, the light-emitting power supply wirings 103R, 103G, and 103B and the cathode wiring 12a corresponding to the characteristic configuration of the present invention will be described. As shown in FIG. 1, the current supplied from the light-emitting power supply wirings 103R, 103G, and 103B to the light-emitting layer 110 flows into the cathode 12 (cathode wiring 12a). For this reason, in particular, if there is wiring resistance of the cathode wiring 12a whose wiring width is limited, the voltage drop becomes large, the potential changes depending on the position of the cathode wiring 12a, and image display abnormalities such as contrast reduction are caused. .

  In order to prevent such a problem, in the present embodiment, the total area of the cathode wiring 12a is formed to be larger than the areas of the light-emitting power supply wirings 103R, 103G, and 103B. In order to reduce the wiring resistance as much as possible, the cathode wiring 12a preferably has a large area. However, as shown in FIG. 2, since various wirings are arranged on the substrate 2, the area of the cathode wiring 12a is limited to some extent.

  Therefore, assuming that the resistivity per unit length in the length direction of the light-emitting power supply wirings 103R, 103G, 103B and the cathode wiring 12a is equal, the line width is set to at least a part of the cathode wiring 12a. By making it wider than the line widths of the power supply lines 103R, 103G, and 103B, the total area of the cathode line 12a is designed to be larger than the areas of the light-emitting power supply lines 103R, 103G, and 103B. In the example shown in FIG. 2, the line width of the cathode wiring 12a is made wider than that of each of the light-emitting power supply wirings 103R, 103G, and 103B.

  Here, it is assumed that the voltage values applied to the light-emitting power supply wirings 103R, 103G, and 103B are the same, the light-emitting power supply wirings 103R, 103G, and 103B have the same line width, and the same current flows through each of them. It is assumed that all the light emitting layers 110 have the same electrical characteristics. At this time, a current obtained by adding the currents flowing through the light-emitting power supply wirings 103R, 103G, and 103B and the light-emitting layer 110 flows through the cathode wiring 12a. Therefore, in order to make the voltage drop in the cathode wiring 12a the same as the voltage drop in the light emitting power supply wirings 103R, 103G, 103B, the line width of the cathode wiring 12a is set to each of the light emitting power supply wirings 103R, 103G, 103B. It is preferable to make the line width wider than the sum of the line widths.

  However, in the electro-optical device of the present embodiment, the characteristics of each light emitting layer 110 are different for each color, the voltage values applied to the light emitting power supply lines 103R, 103G, and 103B are also different for each color, and the flowing currents are also different. come. Therefore, in the present embodiment, the line width of the cathode wiring 12a is wider than the line width of the light-emitting power supply wiring where the highest voltage is applied and the most current flows (in other words, the voltage drop is the largest). Just do it. Wiring other than the light-emitting power supply wiring is applied with a lower voltage and less current flows, so that the line width is formed narrower.

  As a result, in this embodiment, the line width of the cathode wiring 12a is formed wider than the line width of each of the light emitting power supply wirings 103R, 103G, and 103B. In this way, the light-emitting power supply wirings 103R, 103G, and 103B and the cathode wiring 12a are set. In the example shown in FIG. 2, the line width of the cathode wiring 12a is formed wider than that of the light-emitting power supply wirings 103R, 103G, and 103B. It is only necessary that the portion is wider than the light-emitting power supply wirings 103R, 103G, and 103B.

  As shown in FIG. 2, a polyimide tape 130 is attached to one end of the substrate 2, and a control IC 131 is mounted on the polyimide tape 130. The control IC 131 incorporates the data side drive circuit 104, the cathode power supply circuit 131, and the light emission power supply circuit 132 shown in FIG.

  Next, as shown in FIGS. 3 and 4, the circuit unit 11 is formed on the substrate 2, and the display pixel unit 3 is formed on the circuit unit 11. In addition, a sealing material 13 surrounding the display pixel unit 3 is formed on the substrate 2, and a sealing substrate 14 is further provided on the display pixel unit 3. The sealing substrate 14 is bonded to the substrate 2 via the sealing material 13 and is made of glass, metal, resin, or the like. An adsorbent 15 is attached to the back side of the sealing substrate 14 so that water or oxygen mixed in the space between the display pixel unit 3 and the sealing substrate 14 can be absorbed. A getter agent may be used instead of the adsorbent 15. Further, the sealing material 13 is made of, for example, a thermosetting resin or an ultraviolet curable resin, and is particularly preferably made of an epoxy resin which is a kind of thermosetting resin.

  A pixel electrode group region 11 a is provided in the central portion of the circuit portion 11. The pixel electrode group region 11 a includes a current thin film transistor 123 and a pixel electrode 111 connected to the current thin film transistor 123. The current thin film transistor 123 is formed to be embedded in the base protective layer 281, the second interlayer insulating layer 283, and the first interlayer insulating layer 284 stacked on the substrate 2, and the pixel electrode 111 is formed on the first interlayer insulating layer 284. Is formed. One of the electrodes (source electrode) connected to the current thin film transistor 123 and formed on the second interlayer insulating layer 283 is connected to the light-emitting power supply wiring 103 (103R, 103G, 103B). The circuit unit 11 is also formed with the storage capacitor Cap and the switching thin film transistor 112 described above, but these are not shown in FIGS. 3 and 4. Further, in FIG. 3 and FIG. 4, illustration of the signal line 102 is omitted. Further, in FIG. 4, the switching thin film transistor 112 and the current thin film transistor 123 are not shown.

  Next, in FIG. 3, the above-described scanning line driving circuit 105 is provided on both sides of the pixel electrode group region 11a in the drawing. In FIG. 4, the above-described inspection circuit 106 is provided on the left side of the pixel electrode group region 11a in the drawing. The scanning line driver circuit 105 is provided with an N-channel or P-channel thin film transistor 105c that constitutes an inverter included in the shift register, and the thin film transistor 105c is not connected to the pixel electrode 111 except for the above. The structure is the same as that of the current thin film transistor 123. Similarly, the inspection circuit 106 includes a thin film transistor 106 a, and this thin film transistor 106 a has the same structure as the current thin film transistor 123 except that it is not connected to the pixel electrode 111.

  Further, as shown in FIG. 3, a scanning line circuit control signal wiring 105a is formed on the base protective layer 281 outside the scanning line driving circuit 105 in the drawing. Further, a scanning line circuit power supply wiring 105b is formed on the second interlayer insulating layer 283 outside the scanning line circuit control signal wiring 105a. Further, as shown in FIG. 4, a test circuit control signal wiring 106 b is formed on the base protective layer 281 on the left side of the test circuit path 106 in the drawing. Further, a test circuit power supply wiring 106c is formed on the second interlayer insulating layer 283 on the left side of the test circuit control signal wiring 106b. A light-emitting power supply wiring 103 is formed outside the scanning line circuit power supply wiring 105b. The light-emitting power supply wiring 103 employs a double wiring structure including two wirings, and is disposed outside the display pixel unit 3 as described above. Wiring resistance can be reduced by adopting a double wiring structure.

For example, the red light-emitting power supply wiring 103R on the left side in FIG. 3 is formed on the first wiring 103R ₁ via the first wiring 103R ₁ formed on the base protective layer 281 and the second interlayer insulating layer 283. The second wiring 103R ₂ is formed. The first wiring 103R ₁ and the second wiring 103R ₂ are connected by a contact hole 103R ₃ penetrating the second interlayer insulating layer 283 as shown in FIG. Thus, the first wiring 103R ₁ is formed at the same hierarchical position as the cathode wiring 12a, and the second interlayer insulating layer 283 is disposed between the first wiring 103R ₁ and the cathode wiring 12a. . As shown in FIGS. 3 and 4, the cathode wiring 12a is electrically connected to the cathode wiring 12b formed on the second interlayer insulating layer 283 through the contact hole. It has a double wiring structure. Therefore, the second wiring 103R ₂ is formed at the same level as the cathode wiring 12b, and the first interlayer insulating layer 284 is disposed between the first wiring 103R ₂ and the cathode wiring 12b. By adopting such a structure, the second electrostatic capacitance C ₂ is formed between the first wiring 103R ₁ and the cathode wiring 12a and between the second wiring 103R ₂ and the cathode wiring 12b. ing.

Similarly, the blue and green light-emitting power supply wirings 103G and 103B on the right side of FIG. 3 also adopt a double wiring structure, and the first wirings 103G ₁ and 103B ₁ formed on the base protection layer 281 respectively. And second wirings 103G ₂ and 103B ₂ formed on the second interlayer insulating layer 283, and the first wirings 103G ₁ and 103B ₁ and the second wirings 103G ₂ and 103B ₂ are shown in FIGS. As shown in FIG. 5, the contact holes 103G ₃ and 103B ₃ that penetrate through the second interlayer insulating layer 283 are connected. A _second capacitance C ₂ is formed between the blue first wiring 103B ₁ and the cathode wiring 12a and between the blue second wiring 103B ₂ and the cathode wiring 12b.

The distance between the first wiring 103R ₁ and the second wiring 103R ₂ is preferably in the range of 0.6 to 1.0 μm, for example. If the distance is less than 0.6 μm, parasitic capacitance between the source metal and the gate metal having different potentials such as the signal line 102 and the scanning line 101 is not preferable. For example, there are many locations where the source metal and the gate metal intersect in the real table time region 4, and if there is a large parasitic capacitance at such locations, there is a risk of causing a time delay of the image signal. As a result, an image signal cannot be written into the pixel electrode 111 within a predetermined period, which causes a decrease in contrast. The material of the second interlayer insulating layer 283 sandwiched between the first wiring 103R ₁ and the second wiring 103R ₂ is preferably, for example, SiO _2, but if formed to be 1.0 μm or more, the substrate 2 may break due to the stress of SiO _2. .

As shown in FIG. 4, the light-emitting power supply wiring 103 has a double wiring structure, but the area of the light-emitting power supply wiring 103 in the present invention refers to one of the double wiring structures (for example, , The area of the power supply wiring 103R ₂ , the power supply wiring 103G ₂ , and the power supply wiring 103B ₂ ).

A cathode 12 extending from the display pixel unit 3 is formed on the upper side of each light-emitting power supply wiring 103R. As a result, the second wiring 103R ₂ of each light-emitting power supply wiring 103R is disposed opposite to the cathode 12 with the first interlayer insulating layer 284 interposed therebetween, whereby the above-described second wiring 103R ₂ and the cathode 12 are interposed between the second wiring 103R ₂ and the cathode 12. 1 capacitance C ₁ is formed.

Here, the distance between the second wiring 103R ₂ and the cathode 12 is preferably in the range of 0.6 to 1.0 μm, for example. When the distance is less than 0.6 μm, parasitic capacitance between the pixel electrode and the source metal having different potentials such as the pixel electrode and the source metal increases, and therefore a wiring delay of the signal line using the source metal occurs. As a result, the image signal cannot be written within a predetermined period, which causes a decrease in contrast. The material of the first interlayer insulating layer 284 sandwiched between the second wiring 103R ₂ and the cathode 12 is preferably, for example, SiO ₂ or acrylic resin. However, if SiO ₂ is formed to have a thickness of 1.0 μm or more, the substrate 2 may be broken by stress. In the case of an acrylic resin, it can be formed up to about 2.0 μm. However, since it has a property of expanding when it contains water, the pixel electrode formed thereon may be broken.

As described above, in the electro-optical device 1 according to the present embodiment, the first electrostatic capacitance C ₁ is provided between the light-emitting power supply wiring 103 and the cathode 12, so When the voltage fluctuates, the charge accumulated in the _first capacitance C ₁ is supplied to the light-emitting power supply wiring 103, and the potential deficiency of the drive current is compensated by this charge, thereby suppressing the potential fluctuation. The image display of the electro-optical device 1 can be kept normal. In particular, since the light-emitting power supply wiring 103 and the cathode 12 face each other outside the display pixel unit 3, the distance between the light-emitting power supply wiring 103 and the cathode 12 is reduced and stored in the _first capacitance C1. The amount of charge that is generated can be increased, and the potential fluctuation of the drive current can be further reduced to stably display an image. Further, the light-emitting power supply wiring 103 has a double wiring structure composed of the first wiring and the second wiring, and the second capacitance C ₂ is provided between the first wiring and the cathode wiring. Since the electric charge accumulated in the _second capacitance C ₂ is also supplied to the light-emitting power supply wiring 103, the potential fluctuation can be further suppressed, and the image display of the electro-optical device 1 can be maintained more normally. it can.

Here, the structure of the circuit unit 11 including the current thin film transistor 123 will be described in detail. FIG. 5 is a cross-sectional view showing the main part of the pixel electrode group region 11a. As shown in FIG. 5, a base protective layer 281 mainly composed of SiO ₂ is laminated on the surface of the substrate 2, and an island-like silicon layer 241 is formed on the base protective layer 281. The silicon layer 241 and the base protective layer 281 are covered with a gate insulating layer 282 mainly composed of SiO ₂ and / or SiN. A gate electrode 242 is formed on the silicon layer 241 with a gate insulating layer 282 interposed therebetween.

5 shows the cross-sectional structure of the current thin film transistor 123, the switching thin film transistor 112 has the same structure. The gate electrode 242 and the gate insulating layer 282 are covered with a second interlayer insulating layer 283 mainly composed of SiO ₂ . In the present specification, the “main component” means a component having the highest content.

  Next, in the silicon layer 241, a region facing the gate electrode 242 with the gate insulating layer 282 interposed therebetween is a channel region 241a. Further, in the silicon layer 241, a low concentration source region 241b and a high concentration source region 241S are provided on the left side of the channel region 241a in the drawing. A low-concentration drain region 241c and a high-concentration drain region 241D are provided on the right side of the channel region 241a in the drawing, and a so-called LDD (Light Doped Drain) structure is formed. The current thin film transistor 123 is mainly composed of this silicon layer 241.

  The high-concentration source region 241S is connected to a source electrode 243 formed on the second interlayer insulating layer 283 through a contact hole 244 opened through the gate insulating layer 282 and the second interlayer insulating layer 283. ing. The source electrode 243 is configured as a part of the signal line 102 described above. On the other hand, the high-concentration drain region 241D is connected to the drain electrode 244 formed in the same layer as the source electrode 243 through a contact hole 245 opened through the gate insulating layer 282 and the second interlayer insulating layer 283. Has been.

  A first interlayer insulating layer 284 is formed on the second interlayer insulating layer 283 on which the source electrode 243 and the drain electrode 244 are formed. A transparent pixel electrode 111 made of ITO or the like is formed on the first interlayer insulating layer 284 and connected to the drain electrode 244 via a contact hole 111a provided in the first interlayer insulating layer 284. Yes. That is, the pixel electrode 111 is connected to the high concentration drain electrode 241D of the silicon layer 241 through the drain electrode 244. As shown in FIG. 3, the pixel electrode 111 is formed at a position corresponding to the actual display region 4, but the dummy electrode 5 formed around the actual display region 4 has the same configuration as the pixel electrode 111. Dummy pixel electrode 111 'is provided. The dummy pixel electrode 111 ′ has the same form as the pixel electrode 111 except that it is not connected to the high concentration drain electrode 241D.

  Next, a light emitting layer 110 and a bank unit (bank) 122 are formed in the actual pixel region 4 of the display pixel unit 3. As shown in FIGS. 3 to 5, the light emitting layer 110 is stacked on each of the pixel electrodes 111. The bank unit 122 is provided between each pixel electrode 111 and each light emitting layer 110, and partitions each light emitting layer 110. The bank unit 122 is configured by laminating an inorganic bank layer 122 a located on the substrate 2 side and an organic bank layer 122 b located away from the substrate 2. A light shielding layer may be disposed between the inorganic bank layer 122a and the organic bank layer 122b.

The inorganic and organic bank layers 122a and 122b are formed to extend on the peripheral edge of the pixel electrode 111, and the inorganic bank layer 122a extends to the center side of the pixel electrode 111 from the organic bank layer 122b. Is formed. Also, the inorganic bank layer 122a is, for example, preferably made of an inorganic material of SiO _2, TiO _2, SiN or the like. The film thickness of the inorganic bank layer 122a is preferably in the range of 50 to 200 nm, particularly 150 nm. If the film thickness is less than 50 nm, the inorganic bank layer 122a is thinner than the hole injection / transport layer described later, and the flatness of the hole injection / transport layer cannot be ensured. On the other hand, if the film thickness exceeds 200 nm, the step due to the inorganic bank layer 122a becomes large, and the flatness of the light emitting layer to be described later stacked on the hole injection / transport layer cannot be secured, which is not preferable.

  Furthermore, the organic bank layer 122b is formed of a normal resist such as an acrylic resin or a polyimide resin. The thickness of the organic bank layer 122b is preferably in the range of 0.1 to 3.5 μm, and particularly preferably about 2 μm. If the thickness is less than 0.1 μm, the organic bank layer 122b becomes thinner than the total thickness of the hole injection / transport layer and the light emitting layer, which will be described later, and the light emitting layer may overflow from the upper opening, which is not preferable. On the other hand, if the thickness exceeds 3.5 μm, the step due to the upper opening becomes large, and step coverage of the cathode 12 formed on the organic bank layer 122b cannot be secured, which is not preferable. Further, if the thickness of the organic bank layer 122b is 2 μm or more, it is more preferable in that the insulation between the cathode 12 and the pixel electrode 111 can be enhanced. In this way, the light emitting layer 110 is formed thinner than the bank portion 122.

  Further, an area showing lyophilicity and an area showing liquid repellency are formed around the bank portion 122. The lyophilic regions are the inorganic bank layer 122a and the pixel electrode 111, and lyophilic groups such as hydroxyl groups are introduced into these regions by plasma treatment using oxygen as a reactive gas. Further, the region showing liquid repellency is the organic bank layer 122b, and a liquid repellent group such as fluorine is introduced by plasma treatment using tetrafluoromethane as a reaction gas.

  Next, as shown in FIG. 5, the light emitting layer 110 is stacked on the hole injection / transport layer 110 a stacked on the pixel electrode 111. In the present specification, a configuration including the light emitting layer 110 and the hole injection / transport layer 110a is referred to as a functional layer, and a configuration including the pixel electrode 111, the functional layer, and the cathode 12 is referred to as a light emitting element. The hole injection / transport layer 110a has a function of injecting holes into the light emitting layer 110 and a function of transporting holes inside the hole injection / transport layer 110a. By providing such a hole injecting / transporting layer 110a between the pixel electrode 111 and the light emitting layer 110, device characteristics such as light emission efficiency and life of the light emitting layer 110 are improved. Further, in the light emitting layer 110, the holes injected from the hole injection / transport layer 110a and the electrons from the cathode 12 are combined to generate fluorescence. The light emitting layer 11b has three types, a red light emitting layer that emits red (R), a green light emitting layer that emits green (G), and a blue light emitting layer that emits blue (B). As shown in FIG. 2, the light emitting layers are arranged in stripes.

  Next, as shown in FIGS. 3 and 4, a dummy light emitting layer 210 and a dummy bank unit 212 are formed in the dummy region 5 of the display pixel unit 3. The dummy bank unit 212 is configured by laminating a dummy inorganic bank layer 212 a located on the substrate 2 side and a dummy organic bank layer 212 b located away from the substrate 2. The dummy inorganic bank layer 212a is formed on the entire surface of the dummy pixel electrode 111 ′. The dummy organic bank layer 212b is formed between the pixel electrodes 111 in the same manner as the organic bank layer 122b. The dummy light emitting layer 210 is formed on the dummy pixel electrode 111 ′ via the dummy inorganic bank 212a.

  The dummy inorganic bank layer 212a and the dummy organic bank layer 211b have the same material and the same film thickness as the inorganic and organic bank layers 122a and 122b described above. The dummy light-emitting layer 210 is laminated on a dummy hole injection / transport layer (not shown), and the material and film thickness of the dummy hole injection / transport layer and the dummy light-emitting layer are the above-described hole injection / transport. It is the same as the layer 110a and the light emitting layer 110. Therefore, similar to the light emitting layer 110 described above, the dummy light emitting layer 210 is formed thinner than the dummy bank portion 212.

  By disposing the dummy region 5 around the actual display region 4, the thickness of the light emitting layer 110 in the actual display region 4 can be made uniform, and display unevenness can be suppressed. That is, by disposing the dummy region 5, the drying condition of the discharged composition ink when the display element is formed by the ink jet method can be made constant in the actual display region 4. Therefore, there is no possibility that the thickness of the light emitting layer 110 is uneven.

Next, the cathode 12 is formed on the entire surface of the actual display region 4 and the dummy region 5 and extends to the substrate 2 outside the dummy region 5, and outside the dummy region 5, that is, outside the display pixel unit 3. The light-emitting power supply wiring 103 is opposed to the light-emitting power supply line 103. The end of the cathode 12 is connected over the entire surface of the cathode wiring 12 a formed in the circuit section 11. The cathode 12 serves as a counter electrode of the pixel electrode 111 and plays a role of passing a current through the light emitting layer 110. The cathode 12 is configured, for example, by laminating a cathode layer 12b made of a laminate of lithium fluoride and calcium and a reflective layer 12c. Of the cathode 12, only the reflective layer 12 c extends to the outside of the display pixel unit 3. The reflective layer 12c reflects light emitted from the light emitting layer 110 to the substrate 2 side, and is preferably made of, for example, Al, Ag, Mg / Ag laminate, or the like. Furthermore, an antioxidant protective layer made of SiO ₂ , SiN or the like may be provided on the reflective layer 12b.

  Next, a method for manufacturing the electro-optical device 1 according to this embodiment will be described. 6 to 9 are process diagrams illustrating a method for manufacturing an electro-optical device according to an embodiment of the invention. First, a method for forming the circuit portion 11 on the substrate 2 will be described with reference to FIGS. Each of the cross-sectional views shown in FIGS. 6 to 8 corresponds to a cross section taken along the line AA ′ in FIG. In the following description, the impurity concentration is expressed as an impurity after activation annealing.

  First, as shown in FIG. 6A, a base protective layer 281 made of a silicon oxide film or the like is formed on the substrate 2. Next, after an amorphous silicon layer is formed using an ICVD method, a plasma CVD method, or the like, crystal grains are grown by a laser annealing method or a rapid heating method to form a polysilicon layer 501. Thereafter, the polysilicon layer 501 is patterned by photolithography to form island-like silicon layers 241, 251, 261 as shown in FIG. 6B, and further, a gate insulating layer 282 made of a silicon oxide film is formed. .

  The silicon layer 241 forms a current thin film transistor 123 (hereinafter sometimes referred to as “pixel TFT”) that is formed at a position corresponding to the actual display region 4 and connected to the pixel electrode 111. The layers 251 and 261 respectively constitute P-channel and N-channel thin film transistors (hereinafter sometimes referred to as “driving circuit TFTs”) in the scanning line driving circuit 105.

The gate insulating layer 282 is formed by forming a silicon oxide film having a thickness of about 30 nm to 200 nm covering the silicon layers 241, 251, 261 and the base protective layer 281 by plasma CVD, thermal oxidation, or the like. Here, when the gate insulating layer 282 is formed by using the thermal oxidation method, the silicon layers 241, 251, 261 are also crystallized, and these silicon layers can be formed into polysilicon layers. When channel doping is performed, for example, boron ions are implanted at a dose of about 1 × 10 ¹² cm ⁻² at this timing. As a result, the silicon layers 241, 251, 261 are low-concentration P-type silicon layers having an impurity concentration of about 1 × 10 ⁻¹⁷ cm ⁻³ .

Next, as shown in FIG. 6C, an ion implantation selection mask M ₁ is formed in part of the silicon layers 241 and 261, and in this state, phosphorus ions are ionized at a dose of about 1 × 10 ¹⁵ cm ^−2. inject. As a result, the introduction of a self-alignment manner high-concentration impurity to the ion implantation selection mask M _1, the high concentration source region 241S, 261 s and a high concentration drain region 241 D, 261D are formed in the silicon layer 241,261.

Thereafter, as shown in FIG. 6D, after removing the ion implantation selection mask M ₁ , a thickness of about 200 nm such as doped silicon, silicide film, aluminum film, chromium film, or tantalum film is formed on the gate insulating layer 282. By forming a metal film of a certain degree and patterning this metal film, a gate electrode 252 of a P-channel type driving circuit TFT, a gate electrode 242 of a pixel TFT, and a gate electrode of an N-channel type driving circuit TFT 262 is formed. Further, by the patterning, a part of the scanning line driving circuit signal wiring 105a, the light emitting power supply wirings 103R ₁ , 103G ₁ , 103B ₁ and the cathode wiring 12a are simultaneously formed.

Further, using the gate electrodes 242, 252, and 262 as masks, phosphorus ions are implanted into the silicon layers 241, 251, and 261 at a doping amount of about 4 × 10 ¹³ cm ⁻² . As a result, low-concentration impurities are introduced in a self-aligned manner with respect to the gate electrodes 242, 252 and 262, and as shown in FIG. 6D, the low-concentration source regions 241b and 261b and the silicon layers 241 and 261, and Low concentration drain regions 241c and 261c are formed. In addition, low concentration impurity regions 251S and 251D are formed in the silicon layer 251.

Next, as shown in FIG. 7A, an ion implantation selection mask M ₂ is formed on the entire surface excluding the periphery of the gate electrode 252. Using this ion implantation selection mask M ₂ , boron ions are implanted into the silicon layer 251 with a doping amount of about 1.5 × 10 ¹⁵ cm ⁻² . As a result, the gate electrode 252 also functions as a mask, and the silicon layer 252 is doped with high-concentration impurities in a self-aligning manner. As a result, 251S and 251D are counter-doped and become a source region and a drain region of a TFT for a P-type channel type driver circuit.

Then, as shown in FIG. 7B, after removing the ion implantation selection mask M ₂ , a second interlayer insulating layer 283 is formed on the entire surface of the substrate 2, and the second interlayer insulating layer 283 is further formed by photolithography. By patterning, a hole H ₁ for forming a contact hole is provided at a position corresponding to the source electrode and drain electrode of each TFT and the cathode wiring 12a. Next, as shown in FIG. 7C, a conductive layer 504 having a thickness of about 200 nm to 800 nm made of a metal such as aluminum, chromium, or tantalum is formed so as to cover the second interlayer insulating layer 283. Then, these holes are embedded in the previously formed hole H ₁ to form a contact hole. Further, a patterning mask M ₃ is formed on the conductive layer 504.

Next, as shown in FIG. 8A, the conductive layer 504 is patterned with the patterning mask M ₃ , and the source electrodes 243, 253, 263, the drain electrodes 244, 254, and the light-emitting power supply wirings of the respective TFTs are patterned. Two wirings 103R ₂ , 103G ₂ , 103B ₂ , a scanning line power supply wiring 105b, and a cathode wiring 12a are formed. As described above, the second capacitance C ₂ is formed by forming the first wirings 103R ₁ and 103B ₁ apart from each other in the same layer as the cathode wiring 12a.

When the above steps are completed, as shown in FIG. 8B, a first interlayer insulating layer 284 that covers the second interlayer insulating layer 283 is formed of a resin material such as acrylic. The first interlayer insulating layer 284 is preferably formed to a thickness of about 1 to 2 μm. Next, as shown in FIG. 8C, a portion corresponding to the drain electrode 244 of the pixel TFT in the first interlayer insulating layer 284 is removed by etching to form a contact hole forming hole H ₂ . . At the same time, the first interlayer insulating layer 284 on the cathode wiring 12a is also removed. In this way, the circuit unit 11 is formed on the substrate 2.

Next, a procedure for obtaining the electro-optical device 1 by forming the display pixel unit 3 on the circuit unit 11 will be described with reference to FIG. The cross-sectional view shown in FIG. 9 corresponds to a cross section taken along the line AA ′ in FIG. First, as shown in FIG. 9A, a thin film made of a transparent electrode material such as ITO is formed so as to cover the entire surface of the substrate 2, and this thin film is patterned to provide the first interlayer insulating layer 284. to form a contact hole 111a to fill the holes H _2, to form a pixel electrode 111 and the dummy pixel electrode 111 '. The pixel electrode 111 is formed only in a portion where the current thin film transistor 123 is formed, and is connected to the current thin film transistor 123 (switching element) through the contact hole 111a. The dummy electrode 111 ′ is arranged in an island shape.

Next, as shown in FIG. 9B, the inorganic bank layer 122a and the dummy inorganic bank layer 212a are formed on the first interlayer insulating layer 284, the pixel electrode 111, and the dummy pixel electrode 111 ′. The inorganic bank layer 122a is formed so that a part of the pixel electrode 111 is opened, and the dummy inorganic bank layer 212a is formed so as to completely cover the dummy pixel electrode 111 ′. The inorganic bank layer 122a and the dummy inorganic bank layer 212a are formed of an inorganic film such as SiO ₂ , TiO ₂ , or SiN on the entire surface of the first interlayer insulating layer 284 and the pixel electrode 111 by, for example, CVD, TEOS, sputtering, or vapor deposition. After forming, the inorganic film is formed by patterning.

  Further, as shown in FIG. 9B, the organic bank layer 122b and the dummy organic bank layer 212b are formed on the inorganic bank layer 122a and the dummy inorganic bank layer 212a. The organic bank layer 122b is formed in a mode in which a part of the pixel electrode 111 is opened through the inorganic bank layer 122a, and the dummy organic bank layer 212b is formed in a mode in which a part of the dummy inorganic bank layer 212a is opened. . In this way, the bank part 122 is formed on the first interlayer insulating layer 284.

  Subsequently, a region showing lyophilicity and a region showing liquid repellency are formed on the surface of the bank part 122. In the present embodiment, each region is formed by a plasma treatment process. Specifically, in this plasma processing step, the pixel electrode 111, the inorganic bank layer 122a, and the dummy inorganic bank layer 212a are made lyophilic, and the organic bank layer 122b and the dummy organic bank layer 212b are made lyophobic. At least a liquid repellency step.

That is, the bank unit 122 is heated to a predetermined temperature (for example, about 70 to 80 ° C.), and then plasma processing using oxygen as a reactive gas (O ₂ plasma processing) is performed in an air atmosphere as a lyophilic process. Subsequently, as a lyophobic process, plasma treatment using CF ₄ as a reactive gas (CF ₄ plasma treatment) is performed in an air atmosphere, and the bank 122 heated for the plasma treatment is cooled to room temperature. The lyophilic property and the liquid repellency are imparted to a predetermined location.

  Further, a light emitting layer 110 and a dummy light emitting layer 210 are formed on the pixel electrode 111 and the dummy inorganic bank layer 212a, respectively, by an inkjet method. The light emitting layer 110 and the dummy light emitting layer 210 are formed by ejecting and drying a composition ink containing a hole injection / transport layer material and then ejecting and drying a composition ink containing a light emitting layer material. In addition, it is preferable to perform after the formation process of this light emitting layer 110 and the dummy light emitting layer 210 in inert gas atmospheres, such as nitrogen atmosphere and argon atmosphere, in order to prevent the oxidation of a positive hole injection / transport layer and a light emitting layer.

Next, as shown in FIG. 9C, the cathode 12 covering the bank part 122, the light emitting layer 110, and the dummy light emitting layer 210 is formed. In the cathode 12, the cathode layer 12 b is formed on the bank portion 122, the light emitting layer 110, and the dummy light emitting layer 210, and then the reflective layer 12 c that covers the cathode layer 12 b and is connected to the cathode wiring 12 a on the substrate 2 is formed. Can be obtained. In this manner, the reflective layer 12c is extended from the display pixel portion 3 onto the substrate 2 so as to connect the reflective layer 12c to the cathode wiring 12a, whereby the reflective layer 12c emits light through the first interlayer insulating layer 284. A _first capacitance C ₁ is formed between the reflective layer 12 c (cathode) and the light-emitting power supply wiring 103 so as to face the power supply wiring 103. Finally, a sealing material 13 such as an epoxy resin is applied to the substrate 2, and the sealing substrate 14 is bonded to the substrate 2 through the sealing material 13. In this way, the electro-optical device 1 as shown in FIGS. 1 to 4 is obtained.

  By incorporating electronic components such as an electro-optical device, a motherboard including a CPU (central processing unit), a keyboard, and a hard disk manufactured in this manner into a housing, for example, a notebook personal computer 600 (see FIG. 10) ( Electronic device) is manufactured. FIG. 10 is a diagram illustrating an example of an electronic apparatus including the electro-optical device according to the embodiment of the invention. In FIG. 10, reference numeral 601 denotes a housing, 602 denotes a liquid crystal display device, and 603 denotes a keyboard. FIG. 11 is a perspective view showing a mobile phone as another electronic apparatus. A cellular phone 700 illustrated in FIG. 11 includes an antenna 701, a receiver 702, a transmitter 703, a liquid crystal display device 704, an operation button unit 705, and the like.

In the above-described embodiment, a notebook computer and a mobile phone have been described as examples of electronic devices. However, the present invention is not limited to these, and a liquid crystal projector, a multimedia-compatible personal computer (PC), and an engineering workstation (EWS). It can be applied to electronic devices such as pagers, word processors, televisions, viewfinder type or monitor direct-view type video tape recorders, electronic notebooks, electronic desk calculators, car navigation devices, POS terminals, and devices equipped with touch panels. .
〔The invention's effect〕

As described above, according to the present invention, the cathode wiring extends along a plurality of sides forming the outer periphery of the substrate and is provided between the outer periphery of the substrate and the drive circuit. Thus, there is an effect that a voltage drop generated when the current supplied to the light emitting element through the first electrode flows through the cathode wiring can be suppressed to a small value. As a result, there is an effect that the supply of image signals is stabilized and image display abnormalities such as contrast reduction can be suppressed.

1 is a diagram schematically showing a wiring structure of an electro-optical device according to an embodiment of the present invention. 1 is a schematic plan view of an electro-optical device according to an embodiment of the present invention. It is sectional drawing which follows the AA 'line of FIG. It is sectional drawing which follows the BB 'line of FIG. It is sectional drawing which shows the principal part of the pixel electrode group area | region 11a. FIG. 6 is a process diagram illustrating a method for manufacturing an electro-optical device according to an embodiment of the invention. FIG. 6 is a process diagram illustrating a method for manufacturing an electro-optical device according to an embodiment of the invention. FIG. 6 is a process diagram illustrating a method for manufacturing an electro-optical device according to an embodiment of the invention. FIG. 6 is a process diagram illustrating a method for manufacturing an electro-optical device according to an embodiment of the invention. 1 is a diagram illustrating an example of an electronic apparatus including an electro-optical device according to an embodiment of the invention. It is a perspective view which shows the mobile telephone as another electronic device.

Explanation of symbols

4. Actual display area (effective display area)
5 ... Dummy area 12 ... Cathode (second electrode)
12a …… Wiring for cathode 101 …… Scanning line (control line)
102 …… Signal line (control line)
103, 103R, 103G, 103B... Light emitting power supply wiring 110, 110R, 110G, 110B... Light emitting element 110a... Hole injection / transport layer 110 .. Light emitting layer 111.
112 …… Switching thin film transistor (switching element)
123 …… Current thin film transistor (switching element)

Claims (12)

A first electrode group region in which a plurality of first electrodes and a transistor connected to each of the plurality of first electrodes are provided on a base;
A second electrode provided in common to the plurality of first electrodes;
A light emitting device provided between each of the plurality of first electrodes and the second electrode;
A drive circuit for supplying an electric signal to the transistor, provided outside the first electrode region;
A first wiring for supplying a power supply voltage to the first electrode via the transistor;
A second wiring provided so as to overlap the second electrode over the entire surface , and provided in contact with a region overlapping the second electrode,
The second wiring provided in contact with the second electrode extends along a plurality of sides forming the outer periphery of the base and is provided between the outer periphery of the base and a drive circuit.
A light emitting device characterized by that. The light-emitting device according to claim 1,
The light emitting device according to claim 1, wherein the first wiring extends along a plurality of sides forming an outer periphery of the base body and includes a portion provided between the second wiring and the drive circuit. The light-emitting device according to claim 1,
The light emitting device according to claim 2, wherein the second wiring extends along at least three sides of a plurality of sides forming an outer periphery of the base. The light-emitting device according to any one of claims 1 to 3,
The light emitting device, wherein a line width of the second wiring is formed wider than a line width of the first wiring. The light-emitting device according to claim 4,
The light emitting device according to claim 1, wherein a line width of the second wiring is formed wider than a line width of the first wiring over the entire wiring. The light-emitting device according to any one of claims 1 to 5,
The connection portion between the second wiring and the second electrode is provided between the first electrode group region and a plurality of sides forming the outer periphery of the base. The light-emitting device according to claim 6,
The connecting portion between the second wiring and the second electrode is provided between the first electrode group region and at least three sides among a plurality of sides forming the outer periphery of the base. Light emitting device. The light-emitting device according to any one of claims 1 to 7,
Each of the plurality of light emitting elements is provided between a corresponding first electrode and the second electrode among the plurality of first electrodes, and a voltage is generated between the corresponding first electrode and the second electrode. Has a light emitting layer that emits light by being applied,
The plurality of light emitting elements include a plurality of types of light emitting elements having different emission colors of the light emitting layer,
The light-emitting device, wherein the first wiring is wired for each emission color. The light-emitting device according to any one of claims 1 to 8,
A plurality of control lines for transmitting the electrical signal to the transistor;
The light emitting device, wherein the plurality of control lines are arranged so as not to intersect at least one of the first wiring and the second wiring on at least the base. The light emitting device according to any one of claims 1 to 9,
The light-emitting device, wherein the control line includes a scanning line for supplying a scanning signal to the transistor and a data line for supplying a data signal to the transistor. The light-emitting device according to any one of claims 1 to 10,
The light emitting device is formed by laminating a hole injection / transport layer and a light emitting layer made of an organic electroluminescent material. An electronic apparatus comprising the electro-optical device according to claim 1.

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