JP4692871B2 - Display driving device and display device - Google Patents

Description

The present invention relates to a display driving device and a display device .

  In recent years, as a display device (display) for displaying images, character information, etc. in imaging devices such as digital video cameras and digital still cameras, which are remarkably popular, and portable devices such as mobile phones and personal digital assistants (PDAs), Liquid crystal displays (LCDs) that are thin, lightweight, low power consumption, and have excellent display image quality as monitors and displays for information devices such as computers and video equipment such as televisions. Is frequently used.

Hereinafter, a conventional liquid crystal display device will be briefly described.
FIG. 9 is a block diagram showing a schematic configuration of a conventional active matrix liquid crystal display device, and FIG. 10 is an equivalent circuit diagram showing an example of a main configuration of an active matrix liquid crystal display panel in the conventional technology. .

  As shown in FIG. 9 and FIG. 10, the liquid crystal display device 100P according to the prior art generally includes a liquid crystal display panel (display panel) 110P in which display pixels Px are two-dimensionally arranged (for example, arranged in n rows × m columns). Based on a video signal, a gate driver (scanning driver) 120P that sequentially scans the display pixel Px group in each row of the liquid crystal display panel 110P and sets the selected state to a selected state, and a display pixel Px group in the selected row. A source driver 130P for supplying a display signal voltage, an LCD controller 150P for generating and outputting a control signal (horizontal control signal, vertical control signal, etc.) for controlling operation timing in the gate driver 120P and the source driver 130P, and a video signal Extract various timing signals (horizontal sync signal, vertical sync signal, composite sync signal, etc.) from LC Based on the display signal generation circuit 160P that generates display data composed of luminance signals and outputs the display data to the data driver 130P, and the polarity inversion signal FRP generated by the LCD controller 150P. A common signal driving amplifier (driving amplifier) 170P that applies a common signal voltage Vcom having a predetermined voltage polarity to a common electrode (counter electrode) provided in common to each display pixel Px. ing.

  Here, the liquid crystal display panel 110P includes a plurality of scanning lines SL and a plurality of data lines DL arranged between the opposing transparent substrates, for example, as shown in FIG. And a plurality of display pixels (liquid crystal display pixels) Px arranged in the vicinity of the intersections of the scanning lines SL and the data lines DL. Each display pixel Px includes a pixel transistor TFT composed of a thin film transistor having a source-drain (current path) connected between the pixel electrode and the data line DL, and a gate (control terminal) connected to the scan line SL, and a pixel electrode. And a pixel capacitor (liquid crystal capacitor) Clc composed of liquid crystal molecules filled and held between the common electrode and the pixel electrode provided in common to all display pixels Px, and a pixel capacitor Clc. And an auxiliary capacitor (storage capacitor) Cs for holding the signal voltage applied to the pixel capacitor Clc.

  The scanning lines SL and the data lines DL provided on the liquid crystal display panel 110P are gates provided as IC chips (semiconductor chips) separate from the liquid crystal display panel 110P via connection terminals TMg and TMs, respectively. The driver 120P and the source driver 130P are configured to be connected. In addition, an electrode (auxiliary electrode) on the other end side of the auxiliary capacitor Cs is configured to be applied with a predetermined voltage Vcs (for example, a common signal voltage Vcom) via a common connection line CL.

  In the liquid crystal display device having such a configuration, the display data corresponding to the display pixels for one row of the liquid crystal display panel 110P supplied from the display signal generation circuit 160P is the horizontal control signal supplied from the LCD controller 150P. Based on this, it is sequentially captured and held by the source driver 130P. On the other hand, based on a vertical control signal supplied from the LCD controller 150P, a scanning signal is sequentially applied to each scanning line SL disposed on the liquid crystal display panel 110P by the gate driver 120P, and the display pixels Px group in each row are selected. Set to The source driver 130P supplies the display signal voltages based on the held display data to the display pixels Px simultaneously through the data lines DL in synchronization with the selection timing of the display pixels Px group in each row. By repeating such a series of operations for each row for one screen, desired image information based on the video signal is displayed on the liquid crystal display panel 110P.

  As the mounting structure of the liquid crystal display device, as shown in FIGS. 9 and 10, separately from an insulating substrate such as a glass substrate that forms the liquid crystal display panel 110 </ b> P (where the display pixels Px are formed), In addition to the configuration in which the peripheral circuit gate driver 120P and the source driver 130P are provided and the liquid crystal display panel 110P and the peripheral circuit are electrically connected via the connection terminals TMg and TMs, a polysilicon transistor is applied, A configuration in which a gate driver 120P and a source driver 130P are formed integrally with a display pixel Px on an insulating substrate is also known, and such a display device is disclosed in, for example, Patent Document 1.

JP 2000-267590 (3rd page, FIG. 1)

By the way, the conventional display device described above has the following problems. That is,
(1) As shown in FIGS. 8 and 9, in the configuration in which the liquid crystal display panel 110P, the peripheral circuit gate driver 120P and the source driver 130P are provided as separate IC chips, the liquid crystal is used to improve the display image quality. When the display panel 110P is made high-definition and the number of scanning lines and the number of data lines are increased, the number of terminals of the corresponding gate driver and source driver is increased, and the chip size and the mounting area are increased. In addition to causing an increase, the number of connection terminals for connecting the liquid crystal display panel 110P and each driver is increased, and the pitch between the connection terminals is reduced, thereby increasing the man-hours for connecting each driver to the liquid crystal display panel 110P. At the same time, there is a problem that the manufacturing cost increases because high connection accuracy is required.

(2) Further, as a technique for solving the problem of the mounting area, as shown in the above-mentioned Patent Document 1 and the like, a liquid crystal display panel, a gate driver and a source are formed on a single insulating substrate. A configuration in which a driver is integrally formed by applying a polysilicon transistor is known, but as is well known, a manufacturing technique has already been established for a polysilicon transistor, and good element characteristics (operation characteristics) can be obtained. Compared to amorphous silicon transistors, the manufacturing process is complicated, the manufacturing cost is expensive, and the operating characteristics are insufficient, leading to an increase in the product cost of the liquid crystal display device and obtaining stable display characteristics. Has the problem of being difficult.

Accordingly, in view of the above-described problems, the present invention can reduce the chip area of the driver and reduce the mounting area, and also suppress the increase in the number of connection steps between the display panel and the driver, thereby reducing the manufacturing cost. Another object of the present invention is to provide a display driving device and a display device that can improve operation characteristics (display characteristics).

The invention according to claim 1 controls the first transfer gate corresponding to the first signal line and the second transfer gate corresponding to the second signal line to control the first signal line and the second signal gate. A display driving device that supplies a display signal voltage to a second signal line in a time division manner in one horizontal period, from a first timing in the horizontal period to a second timing in the horizontal period. The first potential that is higher than the ground potential is set, and the second potential that is lower than the ground potential is set from the second timing in the horizontal period to the first timing in the next horizontal period. A first signal output means for outputting a first signal; and a third timing in the horizontal period from a third timing as a timing that is a first time later than the second timing in the horizontal period. The second signal set at the second potential from the fourth timing in the horizontal period to the third timing in the next horizontal period is set to the first potential. Second signal output means for outputting, and a first potential for supplying the first potential as an on potential to the first transfer gate and a second potential as an off potential to the first transfer gate. And a second switch for supplying the second potential to the second transfer gate as an off potential and supplying the second potential to the second transfer gate as an off potential. A control line, a first switch element for controlling the supply of the first signal to the first switch control line, and the second switch control line The second switch element for controlling the supply of the second signal, and the first switch control line once in the first period from the start timing of the horizontal period to the first timing in the horizontal period A second time having a length corresponding to the first period from the second timing in the horizontal period is directly connected to the ground potential and then connected to the ground potential through a predetermined capacitor. In the second period until a later timing, the first switch control line is once connected to the ground potential through the predetermined capacitor and then directly connected to the ground potential. And a second switch in a third period from a timing preceding the third timing in the horizontal period by the second time to the third timing in the horizontal period. The control line is directly connected to the ground potential once and then connected to the ground potential via the predetermined capacitance, and after the fourth timing in the horizontal period by the second time. A second switching means for connecting the second switch control line to the ground potential once through the predetermined capacitance and then directly connecting to the ground potential in a fourth period until timing ; And the first switch element is configured such that the supply of the first signal to the first switch control line stops in the first period and the second period in the horizontal period, and The switching is controlled so as to be maintained in the other period in the horizontal period, and the second switch element is supplied with the second signal to the second switch control line, and the third signal is supplied in the horizontal period. period In fine the fourth period so as to maintain the other periods in and the horizontal period so as to stop, characterized in that it is switching control.

According to a second aspect of the present invention, in the display driving device according to the first aspect, the first time is a time twice or more as long as the second time .

According to a third aspect of the present invention, in the display driving device according to the first or second aspect, the first switching unit directly connects the first switch control line and the ground potential. And a switch for connecting between the first switch control line and the predetermined capacitor .

According to a fourth aspect of the present invention, in the display driving device according to any one of the first to third aspects, the second switching means directly connects the second switch control line and the ground potential. And a switch for connecting between the second switch control line and the predetermined capacitor .

The invention according to claim 5 controls the first transfer gate corresponding to the first signal line and the second transfer gate corresponding to the second signal line to control the first signal line and the second signal gate. A display device that supplies a display signal voltage to a second signal line in a time-division manner within one horizontal period, and is grounded from a first timing in the horizontal period to a second timing in the horizontal period. A first potential higher than the potential and a second potential lower than the ground potential from the second timing in the horizontal period to the first timing in the next horizontal period. First signal output means for outputting a signal of 1 and a fourth timing in the horizontal period from a third timing as a timing after the first time from the second timing in the horizontal period. The second signal set to the second potential is output from the fourth timing in the horizontal period to the third timing in the next horizontal period until imming is set to the first potential. And a first signal output means for supplying the first potential as an ON potential to the first transfer gate and supplying the second potential as an OFF potential to the first transfer gate. And a second switch control for supplying the second potential to the second transfer gate as an off potential and supplying the second potential to the second transfer gate as an off potential. A first switch element that controls the supply of the first signal to the first switch control line, and a front to the second switch control line. The second switch element for controlling the supply of the second signal, and the first switch control line once directly in the first period from the start timing of the horizontal period to the first timing in the horizontal period. And then connected to the ground potential via a predetermined capacitance, and from the second timing in the horizontal period to a second time having a length corresponding to the first period. First switching means for connecting the first switch control line to the ground potential once through the predetermined capacitance and then directly connecting to the ground potential in a second period until a later timing. And the second switch during a third period from the timing before the second time before the third timing in the horizontal period to the third timing in the horizontal period. The control line is once directly connected to the ground potential, and then connected to the ground potential via the predetermined capacitance, from the fourth timing in the horizontal period to the timing after the second time. And a second switching means for once connecting the second switch control line to the ground potential via the predetermined capacitance and then directly connecting to the ground potential during the fourth period. The first switch element is configured so that the supply of the first signal to the first switch control line is stopped in the first period and the second period in the horizontal period and in the horizontal direction. The switching is controlled to maintain in other periods in the period,
The second switch element is configured such that the supply of the second signal to the second switch control line stops in the third period and the fourth period in the horizontal period and in the horizontal period. Switching is controlled so that it is maintained in other periods.

According to the present invention, the chip size of the driver can be reduced, the mounting area can be reduced, and the manufacturing cost can be reduced by suppressing an increase in the number of connection steps between the display panel and the driver. The operating characteristics (display characteristics) can be improved.

Hereinafter, with reference to the drawings, an embodiment of a display driving device, a driving control method thereof, and a display device including the display driving device according to the present invention will be described.
<Overall configuration>
FIG. 1 is a schematic block diagram showing the overall configuration of a display device according to the present invention, and FIG. 2 is a block diagram showing the main configuration of an embodiment of the display device according to the present invention. In these drawings, the same reference numerals are given to components common to the above-described prior art (FIGS. 9 and 10), and the description thereof will be simplified.

  As shown in FIGS. 1 and 2, the display device 100 according to the present embodiment schematically includes a plurality of scanning lines SL and a plurality of data lines (signal lines) DL, similar to the above-described conventional technique (see FIG. 8). A plurality of display pixels Px two-dimensionally arranged in the vicinity of the intersection, a gate driver 120 that sequentially applies a scanning signal to each scanning line SL at a predetermined timing, and each data line DL based on display data. A source driver 130 for applying a display signal voltage, and control signals (vertical control signal, horizontal control signal, multiplexer control) for controlling the operation state of at least the gate driver 120 and the source driver 130 and a transfer switch circuit 140 described later. LCD controller 150 that generates and outputs a signal) and source dry based on the video signal A display signal generation circuit 160 that generates display data to be supplied to 130 and a timing signal to be supplied to the LCD controller 150, and a common electrode provided in common to all the display pixels Px have a predetermined voltage polarity. And a common voltage driving amplifier 170 for applying the common signal voltage Vcom, and serial data output from the source driver 130 between the liquid crystal display panel 110 and the source driver 130 as a configuration unique to the present embodiment. A transfer switch circuit (data distribution means) 140 for distributing and applying a display signal voltage consisting of the above to each data line DL disposed on the liquid crystal display panel 110 is provided.

In this embodiment, as shown in FIG. 2, at least the liquid crystal display panel 110 includes a pixel area PXA in which a plurality of display pixels Px are two-dimensionally arranged in n rows × m columns, a gate driver 120, and a transfer switch circuit. 140 has a configuration integrally formed on an insulating substrate SUB such as a glass substrate. In this case, a pixel transistor (corresponding to the pixel transistor TFT shown in FIG. 9) constituting the display pixel Px and each functional element (thin film transistor or the like) constituting the gate driver 120 and the transfer switch circuit 140 described later are made of, for example, amorphous silicon. Can be formed by the same manufacturing process. Accordingly, it is possible to manufacture a liquid crystal display device at low cost by applying an amorphous silicon manufacturing process that has already been technically established, and to realize a functional element with stable operating characteristics.
The above-described liquid crystal display panel 110 (pixel area PXA) has the same configuration as the configuration shown in the prior art (the liquid crystal display panel 110P shown in FIG. 14), and thus detailed description thereof is omitted. .

<Configuration of each part>
Next, the configurations of the gate driver 120, the source driver 130, and the transfer switch circuit 140 described above will be described with reference to FIGS. FIG. 3 is a block diagram showing the configuration of the gate driver applied to the liquid crystal display device according to this embodiment. FIG. 4 is a block diagram showing a configuration of a source driver and a transfer switch circuit applied to the liquid crystal display device according to the present embodiment. FIG. 5 is a block diagram showing a configuration of a switch driving unit provided in the source driver. FIG. 6 is a block diagram showing a configuration of a driving assistant provided in the source driver.

As illustrated in FIG. 3, the gate driver 120 sequentially outputs shift signals at a predetermined timing based on a gate start signal GSRT and a gate clock signal GPCK (vertical control signal) supplied from the LCD controller 150. And a two-input AND operation circuit (hereinafter referred to as “a”) having the shift signal output from the shift register 121 as one input and the gate reset signal GRES (vertical control signal) supplied from the LCD controller 150 as the other input. 122 (abbreviated as “AND circuit”), a plurality of (two-stage) level shifters 123 and 124 and an output amplifier (amplifier) 125 for setting (boosting) the output signal from the AND circuit 122 to a predetermined signal level. It has the composition provided. Here, the level shifters 123 and 124 and the output amplifier 125 are mainly for driving the shift register 121 at a low voltage, and apply the level of the output signal of the gate driver 120 to the scanning line SL (display pixel Px). The level of the scanning signal is set according to the signal level of the scanning signal, and is appropriately provided at the output stage of the gate driver 120.

In the gate driver 120 having the above configuration, when the gate start signal GSRT and the gate clock signal GPCK are supplied as vertical control signals from the LCD controller 150, the shift register 121 sequentially outputs the gate start signal GSRT based on the gate clock signal GPCK. While shifting, the shift signal is inputted to one input contact of a plurality of AND circuits 122 provided corresponding to each scanning line.

Here, in the state where the gate reset signal GRES is set to the high level (“1”) (the driving state of the gate driver), the “1” level is always input to the other input contact of the AND circuit 122. Based on the start signal GSRT and the gate clock signal GPCK, a high level (“1”) signal is output from the AND circuit 122 at the timing when the shift signal is output from the shift register 121, and the level shifters 123 and 124 and the output amplifier 125 are output. , Scanning signals G1, G2, G3,... Having a predetermined high level are generated and sequentially applied to the scanning lines SL1, SL2, SL3,. As a result, the display pixels Px connected to the scanning lines SL1, SL2, SL3,... Of each row to which the scanning signals G1, G2, G3,.

On the other hand, in a state where the gate reset signal GRES is set to a low level (“0”) (a reset state of the gate driver), the “0” level is always input to the other input contact of the AND circuit 122. Regardless of whether or not a shift signal is output from the AND 122, a low level (“0”) signal is always output from the AND 122, thereby generating scanning signals G1, G2, G3,... Having a predetermined low level. Then, the display pixels Px connected to the scanning lines SL1, SL2, SL3,... Of each row are set to a non-selected state.

As shown in FIG. 4, the source driver 130 outputs a shift register circuit 131 that sequentially outputs a shift signal at a predetermined timing based on the horizontal shift clock signal SCK and the horizontal period start signal STH, and an output from the shift register circuit 131. In response to the shift signal, a plurality of lines of display data supplied in parallel from the display signal generation circuit 160, for example, a red component (R), a green component (G), and a blue component (B) constituting image information. The three display data Rdata, Gdata, and Bdata are sequentially fetched, and the display data fetched in the previous horizontal period is simultaneously output according to the control signal STB, and the latch circuit 132 sequentially fetches and holds the display data. Among the display data Rdata, Gdata, Bdata of multiple systems (3 systems), display data of 2 systems (Rdata and Gdat a, Bdata and Rdata, or parallel data of any combination of Gdata and Bdata) into a single time-divisionally arranged serial data (pixel data), a 2-input multiplexer 133B, and a D / A The configuration includes a converter 134 and an output amplifier 135. Furthermore, the source driver 130 according to the present embodiment has a configuration in which a switch driver SWD and a driving auxiliary device 141 for driving and controlling a transfer switch circuit 140 described later are integrally formed. The switch drive unit SWD and the drive assistant 141 will be described later.

As shown in FIG. 4, the transfer switch circuit 140 is connected in parallel to the connection terminal TMs from which the display signal voltages Vrg, Vbr, and Vgb are output as time-division serial data from the source driver 130 described above. A plurality of signal supply line groups including two signal supply lines DS1 and DS2 for each data line DLn connected to display pixels corresponding to each of the two systems of display data among the three systems of display data; Each of the signal supply lines DS1 and DS2 includes a plurality of switch element groups each including two transfer gates (switch elements) TG1 and TG2, and a switch drive signal SD1 that is individually supplied from a drive auxiliary device 141 described later. According to ', SD2', the transfer gates TG1, TG2 of each switch element group are controlled to be turned on / off. Display signal voltage Vrg supplied as time division serial data, Vbr, depending on the division timing when display data of two systems of Vgb, sequentially applies is distributed to the data lines DLn of the liquid crystal display panel 110.

  As shown in FIG. 5, the switch driver SWD includes a decoder 126 that sequentially outputs decode signals at a predetermined timing based on the multiplexer control signal CNmx and the switch reset signal SDRES supplied from the LCD controller 150, and the decoder 126 2 has a plurality of level shifters (the same configuration as the level shifters 123 and 124 shown in the gate driver 120 described above) and an output amplifier 128 for supplying the output signal 2 to the transfer switch circuit 140. System switch switching signals SD1 and SD2 are generated.

  In the switch drive unit SWD having such a configuration, when the low level (“0”) switch reset signal SDRES is supplied from the LCD controller 150 as shown in the signal logic shown in Table 1, the multiplexer control signal CNmx Regardless of the signal level, the transfer switch circuit 140 is supplied with low-level ("0") switch switching signals SD1 and SD2 and the data lines DL of each column of display signal voltages generated by the source driver 130 described later. The supply to is cut off.

  When the high level (“1”) switch reset signal SDRES is supplied from the LCD controller 150, as shown in Table 1, the multiplexer control signal CNmx is set to the low level based on the signal level of the multiplexer control signal CNmx. At this time, only the switch switching signal SD1 is set to the high level, and when the multiplexer control signal CNmx is at the high level, only the switch switching signal SD2 is set to the high level. As a result, the transfer gates to which the switch switching signals SD1 and SD2 are applied are turned on sequentially (in time series), and the display signal voltage generated by the source driver 130 described later is supplied to the data line DL of each column. The

  On the other hand, when the gate reset signal GRES is set to a low level (“0”) (the reset state of the gate driver 120), the “0” level is always input to the other input contact of the AND circuit 127. Regardless of the signal level of the decode signal output from 126 (that is, the signal level of the multiplexer control signal CNmx and the switch reset signal SDRES), the transfer switch circuit 140 has a low level ("0") switch switching signal SD1, SD2. Is supplied, and the supply of the display signal voltage generated by the source driver 130 to be described later to the data lines DL in each column is cut off.

According to the present embodiment described above, as shown in FIGS. 2 and 4, the pixel area PXA having the plurality of display pixels Px, the gate driver 120, and the transfer switch circuit 140 are made of an insulating substrate SUB such as a glass substrate. A liquid crystal display panel 110 is formed integrally with the liquid crystal display panel 110, and a transfer switch circuit 140 of the liquid crystal panel 110 and a source driver 130 made of a semiconductor chip are connected via a plurality of connection terminals TMs. The number of TMs can be reduced to a fraction of that of the conventional case in which each of the transfer switch circuits 140 is not used, and thus the pitch between the connection terminals can be designed relatively wide. Man-hours in the connection process can be reduced. Moreover, even if it is comparatively low connection precision, it can connect favorably and can reduce manufacturing cost.

Further, in the configuration in which the display signal voltage is supplied in parallel corresponding to each of the plurality of data lines arranged on the liquid crystal display panel as shown in the prior art, display data (as a digital signal) ( It is necessary to provide a D / A converter for converting the pixel data) to analog, an output amplifier for amplifying the analog pixel data to a predetermined signal level, etc. for each data line. Since the number of these components can be reduced to a fraction, the circuit scale of the source driver is reduced, the size of the semiconductor chip (driver IC) of the source driver 130 is reduced, and the mounting thereof The area can be reduced, and the manufacturing cost can be reduced. Furthermore, the power consumed by the output stage (D / A converter, output amplifier, etc.) can be reduced.

Next, with reference to FIGS. 6 to 7, the configuration and operation of the drive assist device 141 provided in the source driver 130 in the present embodiment will be described. As illustrated in FIG. 6, the drive assist device 141 according to the present embodiment includes a switch control circuit SCC, switch elements SWSD1 to SWSD2, switch elements SWG1 to SWG2, switch elements SW1 to SW2, and a capacitor Cp. The switch control circuit SCC has the switch elements SWSD1 to SWSD2 and SWG1 at predetermined timings synchronized with the switch switching signals SD1 and SD2 and the horizontal synchronization signal H-SYNC supplied from the switch driver SWD (see FIG. 5). An on / off control signal for controlling opening / closing of SWG2 and SW1 to SW2 is generated.

The switch element SWSD1 is connected in series to a switch control line SC1 to which a switch switching signal SD1 is supplied, and opens and closes the switch control line SC1 according to an on / off control signal from the switch control circuit SCC. The switch element SWSD2 is connected in series to the switch control line SC2 to which the switch switching signal SD2 is supplied, and opens and closes the switch control line SC2 according to the on / off control signal from the switch control circuit SCC. One end of each of the switch elements SWG1 and SWG2 is connected to each output side of the switch elements SWSD1 and SWSD2, and the other end is grounded, and opens and closes according to an on / off control signal from the switch control circuit SCC. One end of each of the switch elements SW1 and SW2 is connected to the output side of each of the switch elements SWSD1 and SWSD2, and the other end is connected to the ground via a capacitor Cp. The switch elements SW1 and SW2 are opened and closed according to an on / off control signal from the switch control circuit SCC. To do.

Next, the operation of the drive assistant 141 (switch control circuit SCC) will be described with reference to the timing chart shown in FIG. Here, the switch switching signal SD1 has a pulse waveform that is at a high level from timing t3 to timing t4 and is at a low level in other periods, and the switch switching signal SD2 is between timing t9 and timing t10. It is set to have a pulse waveform that becomes high level at, and becomes low level during other periods. Between the timing when the switch switching signal SD1 becomes high level and the timing when the switch switching signal SD2 becomes high level, the gap time (t1 to t3, t4 to t9) in which both the switch switching signals SD1 and SD2 become low level. , T10 to t12). Further, the high level in each switch switching signal SD1, SD2 has a potential higher than the ground potential, and the low level has a potential lower than the ground potential.

First, when the switch switching signals SD1 and SD2 supplied from the switch drive unit SWD (see FIG. 3) are both at the low level, the switch element SWSD1 is turned off at timing t1 synchronized with the rising of the horizontal synchronization signal H-SYNC. The switch element SWG1 is turned on to set the switch control line SC1 to the ground level. Further, the switch element SWSD2 is turned on between t1 and t7, and during this time, the switch control line SC2 is set to a low level.
Next, at the timing t2 after the switch control line SC1 is set to the ground level, the switch element SWG1 is turned off and the switch element SW1 is turned on. As a result, the charge held in the capacitor Cp is discharged toward the switch control line SC1, and the potential of the switch control line SC1 rises.

At timing t3 synchronized with the rise of the switch switching signal SD1, the switch element SWSD1 is turned on and the switch element SW1 is turned off. As a result, the potential of the switch control line SC1 becomes the potential (high level) of the switch switching signal SD1, and is output as the switch drive signal SD1 '. At this time, the potential of the switch control line SC1 is set to a somewhat high potential based on the charge held in the capacitor Cp at timing t2 in the gap time before timing t3 when the potential of the switch switching signal SD1 is supplied. Therefore, the potential fluctuation amount of the switch control line SC1 when the potential of the switch control line SC1 is set to the high level at the timing t3 is relatively small.

Next, at the timing t4 synchronized with the fall of the switch switching signal SD1, the switch element SWSD1 is turned off and the switch element SW1 is turned on to charge (hold) the charge on the switch control line SC1 to the capacitor Cp.
Subsequently, at the timing t5 when the charging of the capacitor Cp is completed, the switch element SWSG1 is turned on, the switch element SW1 is turned off, and the switch control line SC1 is set to the ground level.

Next, at the timing t6 after the switch control line SC1 is set to the ground level, the switch element SWSD1 is turned on and the switch element SWG1 is turned off. As a result, the potential of the switch control line SC1 becomes the potential (low level) of the switch switching signal SD1, and is output as the switch drive signal SD1 '. At this time, the potential of the switch control line SC1 is set to the ground level at the timing t5 in the gap time before the timing t6 at which the potential of the switch switching signal SD1 is supplied. Becomes a relatively small potential difference from the ground level to the low level.

Next, at the timing t7 when the switch drive signal SD1 ′ reaches the low level, the switch element SWSD2 is turned off, the switch element SWG2 is turned on, and the switch control line SC2 is set to the ground level.
Next, at the timing t8 after setting the switch control line SC2 to the ground level, the switch element SWG2 is turned off and the switch element SW2 is turned on. As a result, the charge charged in the capacitor Cp at the previous timings t4 to t5 is discharged to the switch control line SC2, and the potential of the switch control line SC1 rises.

At timing t9 synchronized with the rise of the switch switching signal SD2, the switch element SWSD2 is turned on and the switch element SW2 is turned off. As a result, the potential of the switch control line SC2 becomes the potential (high level) of the switch switching signal SD2, and is output as the switch drive signal SD2 '. At this time, as in the case of the timing t3, the potential of the switch control line SC2 is set to a somewhat high potential based on the electric charge held in the capacitor Cp at the timing t8 in the gap time. When the potential of the switch control line SC2 is set to the high level, the amount of potential fluctuation of the switch control line SC2 becomes relatively small.

Next, at the timing t10 synchronized with the fall of the switch switching signal SD2, the switch element SWSD2 is turned off and the switch element SW2 is turned on to charge (hold) the charge on the switch control line SC2 in the capacitor Cp.
Subsequently, at timing t11 when charging of the capacitor Cp is completed, the switch element SWSG2 is turned on, the switch element SW2 is turned off, and the switch control line SC2 is set to the ground level.

Next, at the timing t12 after the switch control line SC2 is set to the ground level, the switch element SWSD2 is turned on and the switch element SWG2 is turned off. As a result, the potential of the switch control line SC2 becomes the potential (low level) of the switch switching signal SD2, and is output as the switch drive signal SD2 '. At this time, the potential of the switch control line SC2 is set to the ground level at the timing t11 in the gap time before the timing t12 at which the potential of the switch switching signal SD2 is supplied. Becomes a relatively small potential difference from the ground level to the low level. Thereafter, the operations at the timings t1 to t12 described above are repeated.

  In this way, in the drive assist device 141, when the switch switching signals SD1 and SD2 that are periodic and spaced apart from each other by a predetermined time are alternately supplied to the switch control lines SC1 and SC2, on the one switch control line The switch elements SWSD1 to SWSD2, SWG1 to SWG2, and SW1 to SW2 are opened and closed so as to charge the capacitor Cp and discharge the charge charged in the capacitor Cp to the other switch control line side to increase the potential level. By controlling, the switch control lines SC1 and SC2 are driven to high level by the switch switching signals SD1 and SD2 to drive the respective switching elements. The SC2 can be reduced compared to the low level to the high level. That.

Here, when the transfer gates TG1 and TG2 of the transfer switch circuit 140 are configured by amorphous silicon thin film transistors, the switching elements of the transfer gates TG1 and TG2 have the ability to drive the data lines DL of the liquid crystal display panel 110. Therefore, the size of each switching element is relatively larger than the size of the pixel transistor. For this reason, the parasitic capacitance on the gate side of each switching element becomes large, and the parasitic capacitance connected to the switch control lines SC1 and SC2 becomes very large. Driving each switching element with the switch control lines SC1 and SC2 set to a predetermined voltage corresponds to charging the parasitic capacitance connected to the switch control lines SC1 and SC2 to the predetermined voltage.

Therefore, according to the present embodiment, when the switch control lines SC1 and SC2 are set to the high level by the switch switching signals SD1 and SD2 to drive each switching element, before the high-level switch switching signals SD1 and SD2 are supplied. In this gap time, the electric charge charged in the capacitor Cp is discharged to the switch control line, so that the potential of the switch control line is raised to some extent in advance. As a result, the amount of potential fluctuation of the switch control lines SC1, SC2 can be reduced as compared with the case where the switch control lines SC1, SC2 are simply changed from the low level to the high level. The amount of charge required to drive each switch element via the switch control lines SC1 and SC2 can be reduced, and the power consumption related to the drive of the switch element can be reduced.

Further, in the drive assistant 141 described above, when the switch control lines SC1 and SC2 are set to the low level by the switch switching signals SD1 and SD2, during the gap time before the low level switch switching signals SD1 and SD2 are supplied. Since the switch control lines SC1 and SC2 are once set to the ground level and then the switch control lines SC1 and SC2 are set to the low level by the switch switching signals SD1 and SD2, the potential fluctuations of the switch control lines SC1 and SC2 are changed. The amount becomes a potential difference between the ground level and the low level, and it becomes unnecessary to drive the switch control lines SC1 and SC2 to the ground level by the switch switching signals SD1 and SD2, and the amount of charge can be reduced accordingly. Thereby, the power consumption related to the driving of the switch element can be further reduced.

In the above-described embodiment, as described above, the drive assist device 141 includes the switch control lines SC1, SC1, SW2, and the capacitor Cp based on the charges held in the capacitor Cp during the gap time. Although both the configuration for raising the potential of SC2 and the configuration for temporarily setting the potentials of the switch control lines SC1 and SC2 to the ground potential by the switch elements SWG1 and SWG2, the present invention is not limited to this. Instead, it may have a configuration that includes the switch elements SW1 to SW2 and the capacitor Cp, and raises the potentials of the switch control lines SC1 and SC2 based on the electric charge held in the capacitor Cp.

  In the source driver 130 and the transfer switch circuit 140 having the above-described configuration, three lines of display data Rdata, Gdata, and Bdata corresponding to the display pixels of RGB for one row from the display signal generation circuit 160 are converted into parallel data. Sequentially supplied and sequentially received and held by the plurality of latch circuits 132 in accordance with the shift signal output from the shift register 131, and the display data thus acquired is output all at once according to the control signal STB. Is based on a single multiplexer control signal CNmx supplied from the LCD controller 150 for each of two systems of display data (Rdata and Gdata, Bdata and Rdata, or Gdata and Bdata) corresponding to adjacent display pixels Px. By the 2-input multiplexer 133B D / A converter 134 into serial data, the output amplifier 135 via the connection terminal TMs, is output to the transfer switch circuit 140 as the display signal voltage Vrgb.

  At this time, switch switch signals SD1 and SD2 are generated from the switch driver SWD provided in the source driver 130 based on the multiplexer control signal CNmx for controlling the serial conversion processing in the multiplexer 133B. Then, the drive assist device 141 generates switch drive signals SD1 ′ and SD2 ′ that assist the drive potentials of the switch switching signals SD1 and SD2, respectively. The pixel data (1) is generated by the switch drive signals SD1 ′ and SD2 ′. In synchronization with the time division timing of the display signal voltage), the transfer gates TG1 and TG2 provided in the data lines DL1, DL3,... And DL2, DL4. On operation.

  As a result, the switch drive signals SD1 ′ and SD2 based on the predetermined timing at which the switch switching signal SD1 or SD2 is supplied (that is, the time division timing of the display data Rdata, Gdata, and Bdata converted based on the multiplexer control signal CNmx). Each of the transfer gates TG1 and TG2 is selectively turned on by ', so that the display signal voltage Vr based on the red component Rdata of the display data among the display signal voltage Vrg composed of time-division serial data becomes the data lines DL1, DL4, DL7. The display signal voltage Vg based on the green component Gdata is supplied to the data lines DL2, DL5, DL8,... DL (k + 2) and is based on the blue component Bdata. The display signal voltage Vb is supplied to the data lines DL3, DL6, DL9,... DL (k + 3).

  The drive control operation of the liquid crystal display device according to the present embodiment applies the scanning signal Gi from the gate driver 120 to the scanning line SLi (1 ≦ i ≦ n), with one horizontal period (1H) as one cycle, In addition to setting the display pixel Px in the row to the selected state, as shown in the timing chart of FIG. 8, two data lines DL adjacent to each other via the source driver 130 and the transfer switch circuit 140 during the selection period. As a set, the display signal voltages Vr, Vg, and Vb corresponding to the display data corresponding to each display pixel Px are sequentially applied at the application timing of the switch drive signals SD1 ′ and SD2 ′ (the conduction timing of the transfer gates TG1 and TG2). By applying the voltage, an operation of writing predetermined display data to each display pixel Px in the row is executed.

Such a writing operation is sequentially performed with respect to each scanning line SL1, SL2,... SLn (n = 320 in the present embodiment) constituting the liquid crystal display panel 110, and scanning signals G1, G2, G3,. Is applied, the display data for one screen of the liquid crystal display panel is written to each display pixel Px. Thereby, each display pixel Px is set to a gradation state corresponding to the display data, so that desired image information is displayed on the liquid crystal display panel 110.

  In the above embodiment, as shown in FIG. 2, the pixel area PXA and the transfer switch circuit 140 are integrally formed on an insulating substrate SUB such as a glass substrate forming the liquid crystal display panel 110. However, the present invention is not limited to this, and the transfer switch circuit 140 is integrally formed in the source driver 130 so that each of the liquid crystal display panels 110 is connected. It may be configured to be connected to the data line DL. Even in this case, the number of D / A converters for analogizing display data (pixel data), output amplifiers for amplifying the analog pixel data to a predetermined signal level, etc. in the case of the conventional configuration On the other hand, since it can be reduced to a fraction, the circuit scale of the source driver can be reduced, the size of the semiconductor chip (driver IC) of the source driver 130 can be reduced, and the mounting area can be reduced. Thus, the manufacturing cost can be reduced, and further, the power consumed by the output stage (D / A converter, output amplifier, etc.) can be reduced.

  Further, in the present embodiment, from the viewpoint of simplifying the description, the driving assistant 141 (FIGS. 4 and 4) corresponding to the two systems of switch switching signals SD1 and SD2 supplied from the switch driver SWD (see FIG. 5). 6), the gist of the present invention is not limited to this. For example, it is possible to assist driving for the three systems of switch switching signals SD1 to SD3 supplied from the switch driver SWD. In this case, the charge on the driven switch control line is charged in the capacitor Cp within the gap generation time of the switch switching signal, and the charged charge is discharged to the next driven switch control line side to set the potential level. Switching may be performed so that the operation of assisting driving by raising is repeated.

It is a schematic block diagram which shows the whole structure of the display apparatus concerning this invention. It is a block diagram which shows the principal part structure in one Embodiment of the display apparatus concerning this invention. It is a block diagram which shows the structure of the gate driver applied to the display apparatus concerning this embodiment. It is a block diagram which shows the structure of the source driver applied to the display apparatus concerning this embodiment, and a transfer switch circuit. It is a block diagram which shows the structure of the switch drive part with which the source driver in this embodiment is provided. It is a block diagram which shows the structure of the drive assistance device with which the source driver in this embodiment is provided. It is a timing chart for demonstrating the switching operation of the drive auxiliary device in this embodiment. 4 is a timing chart illustrating a drive braking operation of the entire liquid crystal display device according to the present embodiment. It is a block diagram which shows schematic structure of the active matrix type liquid crystal display device in a prior art. FIG. 6 is an equivalent circuit diagram illustrating an example of a main configuration of an active matrix liquid crystal display panel according to a conventional technique.

Explanation of symbols

100 Liquid Crystal Display Device 110 Liquid Crystal Display Panel 120 Gate Driver 130 Source Driver 140 Transfer Switch Circuit 141 Drive Auxiliary Device 141
150 LCD Controller SWD Switch Drive Unit CSG Control Signal Generation Unit

Claims (5)

The first transfer gate corresponding to the first signal line and the second transfer gate corresponding to the second signal line are controlled, and the first signal line and the second signal line are controlled. A display driving device for supplying a display signal voltage in a time division manner within one horizontal period,
From the first timing in the horizontal period to the second timing in the horizontal period is set to a first potential that is higher than the ground potential, and from the second timing in the horizontal period to the second in the next horizontal period. First signal output means for outputting a first signal set at a second potential lower than the ground potential until the timing of 1;
From the third timing as the timing after the first time in the horizontal period to the fourth timing in the horizontal period is set to the first potential and in the horizontal period. Second signal output means for outputting a second signal set at the second potential from the fourth timing to the third timing in the next horizontal period;
A first switch control line for supplying the first potential as an ON potential to the first transfer gate and supplying the second potential as an OFF potential to the first transfer gate;
A second switch control line for supplying the first potential as an ON potential to the second transfer gate and supplying the second potential as an OFF potential to the second transfer gate;
A first switch element for controlling the supply of the first signal to the first switch control line;
A second switch element for controlling the supply of the second signal to the second switch control line;
In the first period from the start timing of the horizontal period to the first timing in the horizontal period, the first switch control line is once directly connected to the ground potential and then passed through a predetermined capacitance. The first switch is connected to the ground potential during a second period from the second timing in the horizontal period to a timing after a second time corresponding to the first period. First switching means for connecting a control line to the ground potential once through the predetermined capacitance and then directly connecting to the ground potential;
The second switch control line is once directly connected in the third period from the timing before the second time before the third timing in the horizontal period to the third timing in the horizontal period. In the fourth period from the fourth timing in the horizontal period to the timing after the second time , connected to the ground potential and then connected to the ground potential through the predetermined capacitor. A second switching means for connecting the second switch control line to the ground potential once through the predetermined capacitance, and then directly connecting to the ground potential;
With
The first switch element is configured so that the supply of the first signal to the first switch control line stops in the first period and the second period in the horizontal period and in the horizontal period. The switching is controlled to maintain in other periods in
The second switch element is configured such that the supply of the second signal to the second switch control line stops in the third period and the fourth period in the horizontal period and in the horizontal period. A display driving device which is controlled to be switched so as to be maintained in another period.   The display driving apparatus according to claim 1, wherein the first time is a time that is twice or more the second time.   The first switching means includes a switch that directly connects the first switch control line and the ground potential, and a switch that connects the first switch control line and the predetermined capacitor. The display driving device according to claim 1, wherein the display driving device is provided.   The second switching means includes a switch for directly connecting the second switch control line and the ground potential, and a switch for connecting the second switch control line and the predetermined capacitor. The display driving device according to claim 1, wherein the display driving device is provided. The first transfer gate corresponding to the first signal line and the second transfer gate corresponding to the second signal line are controlled, and the first signal line and the second signal line are controlled. A display device for supplying a display signal voltage in a time division manner within one horizontal period,
From the first timing in the horizontal period to the second timing in the horizontal period is set to a first potential that is higher than the ground potential, and from the second timing in the horizontal period to the second in the next horizontal period. First signal output means for outputting a first signal set at a second potential lower than the ground potential until the timing of 1;
From the third timing as the timing after the first time in the horizontal period to the fourth timing in the horizontal period is set to the first potential and in the horizontal period. Second signal output means for outputting a second signal set at the second potential from the fourth timing to the third timing in the next horizontal period;
A first switch control line for supplying the first potential as an ON potential to the first transfer gate and supplying the second potential as an OFF potential to the first transfer gate;
A second switch control line for supplying the first potential as an ON potential to the second transfer gate and supplying the second potential as an OFF potential to the second transfer gate;
A first switch element for controlling the supply of the first signal to the first switch control line;
A second switch element for controlling the supply of the second signal to the second switch control line;
In the first period from the start timing of the horizontal period to the first timing in the horizontal period, the first switch control line is once directly connected to the ground potential and then passed through a predetermined capacitance. The first switch is connected to the ground potential during a second period from the second timing in the horizontal period to a timing after a second time corresponding to the first period. First switching means for connecting a control line to the ground potential once through the predetermined capacitance and then directly connecting to the ground potential;
The second switch control line is once directly connected in the third period from the timing before the second time before the third timing in the horizontal period to the third timing in the horizontal period. In the fourth period from the fourth timing in the horizontal period to the timing after the second time , connected to the ground potential and then connected to the ground potential through the predetermined capacitor. A second switching means for connecting the second switch control line to the ground potential once through the predetermined capacitance, and then directly connecting to the ground potential;
With
The first switch element is configured so that the supply of the first signal to the first switch control line stops in the first period and the second period in the horizontal period and in the horizontal period. The switching is controlled to maintain in other periods in
The second switch element is configured such that the supply of the second signal to the second switch control line stops in the third period and the fourth period in the horizontal period and in the horizontal period. A display device which is controlled to be switched so as to be maintained in another period.

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