JP5220992B2 - Apparatus and method for driving a plurality of subpixels from single gradation data - Google Patents

Description

  The present invention relates to a display device such as an LCD (Liquid Crystal Display), and more particularly, a plurality of subpixels from grayscale data for one of the subpixels for minimized power consumption and EMI (Electromagnetic Interference). The present invention relates to a driving display device.

  When viewing a panel display such as an LCD with a wide viewing angle, the image hue displayed on the screen is not clearly visible due to the dispersion of light. One method for solving such light dispersion is a 2-TFT method.

  FIG. 1 shows a 2-TFT pixel 100 that includes a first sub-pixel 102 and a second sub-pixel 103.

  The first sub-pixel 102 includes a first sub-pixel electrode expressed as a first storage capacitor Cst-a, and a liquid crystal capacitor Clc- connected between the first storage capacitor Cst-a and the ground node. a) includes a first TFT (MNA) having a drain connected to it. The second subpixel 104 includes a second subpixel electrode expressed as a second storage capacitor, and a second liquid crystal capacitor (Clc-b) connected between the second storage capacitor (Cst-b) and the ground node. A second TFT (MNB) having a connected drain is included.

  The first and second storage capacitors (Cst-a, Cst-b) are connected to the coupling node (Cst). The first TFT MNA has a gate connected to the first gate line Gate-a, and the second TFT MNB has a gate connected to the second gate line Gate-b. The first and second TFTs (MNA, MNB) have sources connected to the source line 106.

  In order to display grayscale data in the 2-TFT pixel 100, the luminance of FIG. 2 is provided between each storage capacitor (Cst-a, Cst-b) and each liquid crystal capacitor (Clc-a, Clc-b). It is desirable to bias each voltage (ΔV) according to a curve.

  As shown in FIG. 2, the first voltage (ΔV1) is applied to the first storage capacitor (Cst-a) and the first liquid crystal capacitor (Clc-a) with respect to arbitrary gradation data displayed on the 2-TFT pixel 100. ) And a second voltage (ΔV2) lower than the first voltage (ΔV1) is between the second storage capacitor (Cst-b) and the second liquid crystal capacitor (Clc-b). It is desirable to be biased.

  During the operation of the 2-TFT pixel 100, the first gate line (Gate-a) is activated so that the first TFT (MNA) is turned on (the second TFT (MNB) is turned off). The capacitor (Cst-a) and the first liquid crystal capacitor (Cla-a) are biased by the first voltage (ΔV1) of the source line 106, while the coupling node (Cst) is a VCOM voltage (for example, a 2-TFT pixel). The display having 100 is biased with the voltage of the common electrode of the panel.

  Thereafter, the second gate line (Gate-b) is activated such that the second TFT (MNB) is turned on (the first TFT (MNV) is turned on at this time) and the second storage capacitor (Cst-b). The two liquid crystal capacitors (Clc-b) are biased by the respective second voltages (ΔV2) of the source line 106, while the coupling node (Cst) is biased by the VCOM voltage.

  Due to the different biases, the first sub-pixel 102 exhibits a first luminance and the second sub-pixel 104 exhibits a second luminance different from the first luminance. As shown in FIG. 2, the 2-TFT pixel 100 is an average luminance curve displayed by the dotted line of FIG. 2, which is the average of the first and second luminances shown from the first subpixel 102 and the second subpixel 104, respectively. 108 is shown.

  When the conventional 2-TFT method is followed, during the time period of one line for driving the plurality of sub-pixels (102, 104), the two voltages (Δ1, Δ2) are independently timed. The data is transmitted from the controller to a source driver for driving the source line 106 with two voltages Δ1 and Δ2.

  This doubles the data rate and / or the number of data buses, eventually increasing power consumption and EMI. Therefore, a method for driving the sub-pixels 102 and 104 of the 2-TFT pixel 100 with the minimized data transmission rate and the number of data buses is required.

  An object of the present invention is to provide a method for generating a source line voltage of a display device in which a plurality of subpixels can be driven from a single grayscale data for one pixel.

  An object of the present invention is to provide a source driver of a display device in which a plurality of subpixels can be driven from a single grayscale data for one pixel.

  An object of the present invention is to provide a display device in which a plurality of subpixels can be driven from a single grayscale data for one pixel.

  To achieve the above-described object, a method for generating a source line voltage according to an embodiment of the present invention includes receiving gray level data for a first sub-pixel of a pixel, from the gray level data to the first sub-pixel. Generating a first source line voltage for a pixel and generating a source line voltage for a second sub-pixel of the pixel from the grayscale data of the first sub-pixel.

  The source line voltage generation method includes generating the first source line voltage from the gray level data and the first luminance curve, and calculating the second source line from the gray level data and the second luminance curve of the first subpixel. The method may further include generating a voltage.

  The step of generating the first source line voltage includes a first D / A (Digital to Analog) converter for at least one MSB (Most Significant Bit) side bit of the grayscale data from the first luminance curve. Selecting a high and low reference voltage, and using at least one LSB (Least Significant Bit) side bit of the grayscale data using the first high and low reference voltages selected by the D / A converter; Converting from a digital value to an analog value can be included.

  The step of generating the second source line voltage comprises selecting second high and low reference voltages for the D / A converter according to at least one MSB side bit of the grayscale data from the second luminance curve. And converting at least one LSB side bit of the grayscale data from a digital value to an analog value using the selected first high and low reference voltages in the D / A converter. .

  To achieve the above object, a source driver of a display device according to an embodiment of the present invention includes a storage device for receiving and storing grayscale data for a first sub-pixel of a pixel, and the floor. A source line for generating a first source line voltage for the first sub-pixel from tone data and a second source line voltage for the second sub-pixel of the pixel from the grayscale data of the first sub-pixel. Includes voltage generator.

  To achieve the above object, a display device according to an embodiment of the present invention includes a display panel having a plurality of gate lines and source lines, a gate driver for generating a scan signal of the gate lines, and the source. A source driver for generating a source line voltage of the line, each source driver receiving and storing grayscale data for a first sub-pixel of a pixel, and the grayscale data A source line voltage generator for generating a first source line voltage for the first sub-pixel and a second source line voltage for the second sub-pixel of the pixel from the gray level data of the first sub-pixel including.

  Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 3 is a block diagram of a display device 200 including components for driving a plurality of subpixels from single grayscale data for one subpixel according to an embodiment of the present invention.

  The display device includes a display panel 202 comprising an array of pixels having a plurality of subpixels for improved wide viewing angles. FIG. 3 shows an example of one pixel 205 having a first subpixel 204 and a second subpixel 206.

  The first subpixel 204 includes a first TFT (MNA) having a drain connected to a first storage capacitor and a first subpixel electrode expressed as a first liquid crystal (LC-a). The second subpixel 206 includes a second TFT (MNB) having a drain connected to a second subpixel electrode represented as a second storage capacitor (Cst-b) and a second liquid crystal (LC-b). The other nodes of each storage capacitor (Cst-a, Cst-b) and liquid crystal (LC-a, LC-b) are grounded as shown in the embodiment of FIG.

  The first TFT (MNA) has a gate connected to the first gate line (GN), and the second TFT (MNB) has a gate connected to the second gate line (GN + 1). The first and second TFTs (MNA, MNB) have sources connected to the source line 208. The display device 200 includes a gate driver 210 that sequentially activates each signal on a gate line (G1, G2,... GN, GN + 1, etc.) related to the display panel 202.

  The display device 200 includes a source driver block 212. For large display panel 202, source driver block 212 includes a plurality of source drivers 214, 216, 218. Each source driver 214, 216, 218 drives each source line in the display panel 202.

  FIG. 4 is a block diagram illustrating the configuration of an exemplary source driver 214 according to one embodiment of the invention.

  The source driver 214 includes a first latch 222 and a second latch 224 for storing the MSB side portion 226 and the LSN side portion 228. The source driver 214 also includes an S-generator 230, a reference voltage generator 232, a D / A converter 234 and an output buffer 236.

  FIG. 5 is a block diagram illustrating the reference voltage generator 232 of FIG. 4 according to one embodiment of the present invention.

  The reference voltage generator 232 includes an upper A / B selector 242, a lower A / B selector 244, an upper / lower selector 246 and a VH-VL selector 248.

  The reference voltage generator 232 receives a plurality of gamma reference voltages (VUH, VUM1, VUM2, VUM1 ', VUM2', VUL, VLM, VLM1, VLM2, VLM1 ', VLM2' and VLL). The gamma reference voltage is defined by a plurality of luminance curves for the first and second sub-pixels as shown in FIGS.

  The upper gamma reference voltages (VUH, VUM1, VUM2, VUM1 ', VUM2', and VUL) are defined from the second luminance curve 252 for the first subpixel 204 and the second luminance curve 254 for the second subpixel 206. When the polarity signal (POL) indicates a positive polarity, the first luminance curve 252 indicates a desired voltage across the first storage capacitor (Cst-a) and the first liquid crystal (LC-a) for each gradation data. It is a curve shown.

  When the polarity signal (POL) indicates positive polarity, the second luminance curve 254 indicates a desired voltage across the second storage capacitor (Cst-b) and the second liquid crystal (LC-b) for each gradation data. It is a curve shown.

  The lower gamma reference voltages (VLH, VLM1, VLM2, VLM1 ', VLM2', and VLL) are defined from the third luminance curve 256 for the first subpixel 204 and the fourth luminance curve 15 for the second subpixel 206. When the polarity signal (POL) indicates a negative polarity, the third luminance curve 256 indicates a desired voltage across the first storage capacitor (Cst-a) and the first liquid crystal (LC-a) for each gradation data. It is a curve shown.

  When the polarity signal (POL) indicates negative polarity, the fourth luminance curve 258 indicates a desired voltage across the second storage capacitor (Cst-b) and the second liquid crystal (LC-b) for each gradation data. It is a curve shown.

  When the polarity signal (POL) indicates positive polarity, the voltages for the first and second luminance curves 256 and 258 are arranged above the common voltage (VCOM). When the polarity signal (POL) indicates negative polarity, the voltages for the third and fourth luminance curves 256 and 258 are disposed below the common voltage (VCOM).

  For the first and second, and third and fourth voltages driving the sub-pixels (204, 206), the luminance shown by the overall pixel 205 is shown in FIG. 6 when the polarity signal (POL) is positive. Along the first average luminance curve 262 represented by a dotted line, and when the polarity signal (PLO) has a negative polarity, it follows the second average luminance curve 264 shown by a dotted line in FIG.

  As shown in FIG. 6, with respect to the first luminance curve 252, the first linear range R1 is formed between the reference voltages VUH and VUM1, and the second linear range R2 is formed between the reference voltages VUM1 and VUM2. The third linear range R3 is formed between the reference voltages VUM2 and VUL. The fourth linear range R4 is formed between the reference voltages VUH and VUM1 ′ with respect to the second luminance curve 254, and the fifth linear range R5 is formed between the reference voltages VUM1 ′ and VUM2 ′. A six-line range R6 is formed between the reference voltages VUM2 ′ and VUL.

  As shown in FIG. 7, with respect to the third luminance curve 256, the seventh linear range R7 is formed between the reference voltages VLH and VLM1, and the eighth linear range R8 is formed between the reference voltages VLM1 and VLM2. The ninth linear range R9 is formed between the reference voltages VLM2 and VLL. Further, with respect to the fourth luminance curve 258, the tenth linear range R10 is formed between the reference voltages VLH and VLM1 ′, and the eleventh linear range R11 is formed between the reference voltages VLM1 ′ and VLM2 ′. The 12 straight line range R12 is formed between the reference voltages VLM2 ′ and VLL.

  FIG. 8 is a circuit diagram showing a configuration of the VH-VL selector 248 of FIG. 5 according to an embodiment of the present invention.

  The VH-VL selector 248 receives four reference voltages at the output of the upper / lower selector 246. The VH-VL selector 248 includes three pairs of switches including a first switch pair SW11 and SW12, a second switch pair SW21 and SW22, and a third switch pair SW31 and SW32.

  Whether one of the switch pairs is closed depends on whether one of the selection signals (S1, S2, S3) is activated and the high DAC voltage (VH) used by the D / A converter 234 is low. It depends on which of the reference voltages is selected as the DAC voltage (VL).

  FIG. 9 is a table showing the high DAC voltage (VH) and the low DAC voltage (VL) which are the outputs from the reference voltage generator 232 by the signals ABR, POL, S1, S2 and S3.

  The A / B ratio signal (ABR) indicates which one of the first and second sub-pixels 204 and 206 is currently driven. As shown in FIGS. 4 and 5, when the ABR signal is logic “0”, the upper A / B selector outputs VUM1 and VUM2 to the upper / lower selector 246, and the lower A / B selector is upper / lower. VLM1 and VLM2 are output to the selector 246.

  When the ABR signal is logic '1', the upper A / B selector outputs VUM1 'and VUM2' to the upper / lower selector 246, and the lower A / B selector outputs VLM1 to the upper / lower selector 246. 'And VLM2' are output.

  Upper and lower selectors 246 receive an input of a first set of reference voltages driven by voltages above VCOM and a second set of reference voltages driven by voltages below VCOM. When the ABR signal and the POL signal are logic '0', the upper / lower selector 246 outputs a third set of four reference voltages (VUH, VUM1, VUM2, VUL). When the ABR signal and the POL signal are logic ‘1’, the upper / lower selector 246 outputs a fourth set of four reference voltages (VLH, VLM1 ′, VLH2 ′, VLL).

  As shown in FIGS. 8 and 9, the VH-VL selector 248 receives four sets of reference voltages that are the outputs of the upper and lower selectors 246.

  The VH-VL selector 248 selects one of the four reference voltages as VH, and selects one of the four reference voltages as VL. As shown in the table of FIG. 9, this is determined by which one of S1, S2 and S3 is activated by "1" which is a logic high state. As shown in FIGS. 6, 8, and 9, VH and VL selected by the VH-VL selector 248 are upper and lower sections for any one of the ranges R1 to R12.

  As shown in FIGS. 4 and 9, one of the S1, S2, and S3 signals is activated by 2 bits (MSB [2]) on the MSB side of the gradation data (D [N: 1]). . The grayscale data (D [N: 1]) is latched by the first latch 222 and then transmitted to the second latch 224. The VH and VL voltages selected by the VH-VL selector 248 are used by the D / A converter 234.

  FIG. 9 is a circuit diagram showing an embodiment of a D / A converter 234 which is a linear charge redistribution D / A converter.

  The D / A converter 234 includes a first switch S1 connected to VH and a second switch connected to VL. A third switch S3 connected to the first capacitor C1 is connected to the other side of the switches S1 and S2. The fourth switch S4 is connected between the first capacitor C1 and the second capacitor C2. The second capacitor C2 is connected to an initialization switch (Sini). The first and second capacitors C1 and C2 have a capacitor (C) as shown in the embodiment of FIG.

  Assuming that VL is '0' volt and the LSB side portion (LSB [N-2]) of the gradation data (D [N: 1]) is '1101', a linear charge redistribution D / A converter An example of the operation 234 is as follows.

  (1) First, the initialization switch is closed to initialize the output voltage (VO) to 0 volts. The switch is then turned off.

  (2) The first "1" from the LSB side is used as data for adjusting the first and second switches (S1, S2). The third switch S3 is turned on, and the second switch S2 is turned off due to the data, whereas the first switch S1 is turned on. Next, the third switch (S3) is turned off and the fourth switch (S4) is turned on. Therefore, VO = VH / 2.

  (3) The second ‘0’ from the LSB side is used as data for adjusting the first and second switches (S1, S2). The fourth switch (S4) is turned off, the third switch (S3) is turned on, and the second switch (S2) is turned on due to the data, while the first switch S1 is turned off. Next, the third switch (S3) is turned off and the fourth switch (S4) is turned on. Therefore, VO = VH / 4.

  (4) The third '1' from the LSB side is used as data for adjusting the first and second switches (S1, S2). The fourth switch (S4) is turned off, the third switch (S3) is turned on, and the second switch (S2) is turned off due to the data, whereas the first switch S1 is turned on. Next, the third switch (S3) is turned off and the fourth switch (S4) is turned on. Therefore, VO = 5VH / 8.

  (5) The fourth “1” from the LSB side is used as data for adjusting the first and second switches (S1, S2). The fourth switch (S4) is turned off, the third switch (S3) is turned on, and the second switch (S2) is turned off due to the data, whereas the first switch S1 is turned on. Next, the third switch (S3) is turned off and the fourth switch (S4) is turned on. Therefore, VO = 13VH / 16.

  In this manner, the LSB side portion (LSB [N-2]) of the gradation data (D [N: 1]) determines the output voltage (VO) with a value between VH and VL. The MSB side part (MSB [2]) determines the VH and VL values. The MSB side portion (MSB [2]) and the LSB side portion (LSB [N-2]) constitute grayscale data latched by the first and second latches 222 and 224.

  The analog voltage (VO) that is the output of the D / A converter 234 is output to the output buffer 236, and the analog voltage (VO) is used to drive the source line 208 for the pixel 205.

  FIG. 11 is a timing diagram showing signals during operation of the source driver 214 of FIG.

  During the first time period (P1), the POL signal and the ABR signal are respectively logic high to input K-1 grayscale data (D [N: 1]) to the first luminance curve 252 for the first subpixel 204. It will be in state '1'.

  During the first time period (P1), the reference voltage generator 232 uses the MSB side portion (MSB [2]) of the K-1 grayscale data (D [N: 1]) to generate three values of the first luminance curve 252. Select VH and VL to define one of the ranges R1, R2 and R3.

  The D / A converter 234 uses the VH and VL to generate the output voltage (VO) and the LSB side portion (LSB [N-1]) of the K-1 gradation data (D [N-1]). The output voltage VO is used to drive a source line 208 for driving the first subpixel 204 during a second time period P2.

  During the second time period (P2), the POL signal is maintained at the logic high state '1', and the ABR signal is converted to the logic low state '0'. Therefore, during the second time period (P2), the reference voltage generator 232 uses the MSB side portion (MSB [2]) of the K-1 grayscale data (D [N: 1]) to generate the second luminance curve 255. Select VH and VL to define one of the three ranges R4, R5 and R6.

  The D / A converter 234 uses VH and VL to generate the output voltage (VO) and the LSB side portion (LSB [N-2]) of the K-1 gradation data (D [N: 1]). The voltage (VO) is used to drive the source line 208 for driving the second subpixel 206 during the third time period P3.

  During the third time period (P3), the POL signal is converted to a logic low state “0”, and the ABR signal is converted to a logic high state “1”. Therefore, during the third time period (P3), the reference voltage generator 232 uses the MSB side portion (MSB [2]) of the K grayscale data (D [N: 1]) to change the three luminance curves 256. Select VH and VL to define one of the ranges R7, R8 and R9.

  The D / A converter 234 uses VH and VL to generate the output voltage (VO) and the LSB side portion (LSB [N-2]) of the K gradation data (D [N: 1]). VO) is used to drive the source line 208 for driving the first subpixel 204 during the fourth time period P4.

  During the fourth time period (P4), the POL signal maintains the logic low state '0', and the ABR signal is converted to the logic low state '0'. Therefore, during the fourth time period (P4), the reference voltage generator 232 uses the MSB side portion (MSB [2]) of the K grayscale data (D [N: 1]) to change the three values of the fourth luminance curve 256. Select VH and VL to define one of the ranges R10, R11 and R12.

  The D / A converter 234 uses VH and VL to generate the output voltage (VO) and the LSB side portion (LSB [N-2]) of the K gradation data (D [N: 1]). VO) is used to drive the source line 208 for driving the second sub-pixel 206 during the fifth time period (P5).

  The operation is repeated to generate an output voltage (VO) by the respective first, second, third and fourth luminance curves 252, 254, 256, 258. In this manner, one gray level data (D [N: 1]) is used to generate respective output voltages VO for driving the two subpixels 204 and 206. Periods P1 and P2 mean one line time for K-1 grayscale data, and periods P3 and P4 mean another line time for K grayscale data.

  Accordingly, each output voltage (VO) for driving the two sub-pixels 204 and 206 is generated for one line time for transmitting one corresponding grayscale data. Eventually, the data rate / and / or data bus is minimized for the source driver 214 to minimize power consumption and EMI.

  The foregoing is merely an example and should not be limited to this. For example, although the present invention has been described with respect to an LCD, the present invention is an invention that can be generalized to any type of display device. Moreover, each component and range presented in the present invention are merely examples.

  The duty cycle of the ABR signal in FIG. 11 may be changed according to the ratio of the first and second liquid crystal (LC-a, LC-b) regions. For example, if the region of the first liquid crystal (LC-a) is larger than the region of the second liquid crystal (LC-b), the respective voltages for generating the output voltage (VO) for driving the first subpixel 204 are generated. The time periods P1 and P3 may be longer than one time period P2 and P4 for driving the second subpixel 206.

  The present invention relates to a display device for driving a plurality of subpixels from grayscale data for one of the subpixels. After all, the plurality of subpixels are driven with a minimized data transmission rate and the number of data buses. The transmission rate and data bus can minimize power consumption and EMI.

  As described above, the embodiments of the present invention have been described in detail. However, the present invention is not limited thereto, and those who have ordinary knowledge in the technical field to which the present invention belongs can be used without departing from the spirit and spirit of the present invention. The present invention can be modified or changed.

FIG. 2 is an exemplary circuit diagram showing one pixel having two sub-pixels according to the prior art. 2 is a graph illustrating a luminance curve for driving two subpixels of FIG. 1. FIG. 3 is a block diagram illustrating a configuration of a display device for driving a plurality of subpixels from a single grayscale data for one subpixel according to an embodiment of the present invention. 4 is a block diagram illustrating the source driver of FIG. 3 according to one embodiment of the present invention. FIG. FIG. 5 is a block diagram illustrating the reference voltage generator of FIG. 4 according to one embodiment of the present invention. 6 is a graph illustrating upper and lower gamma reference voltage luminance curves used in the reference voltage generator of FIG. 5 according to one embodiment of the present invention. 6 is a graph illustrating upper and lower gamma reference voltage luminance curves used in the reference voltage generator of FIG. 5 according to one embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a configuration of the VH-VL selector of FIG. 5 according to one embodiment of the present invention. 5 is a chart showing VH and VL values generated by the reference voltage generator of FIG. 4 according to one embodiment of the present invention. FIG. 9 is a circuit diagram showing a configuration of the D / A converter of FIGS. FIG. 5 is a timing diagram of signals during operation of the source driver of FIG. 4 according to one embodiment of the present invention.

Explanation of symbols

102, 204 First subpixel 104, 206 Second subpixel 200 Display device 202 Display panel 210 Gate driver 214, 216, 218 Source driver 222 Latch 234 D / A converter 236 Output buffer 248 VH-VL selector

Claims (30)

A method for generating a source line voltage of a display device, comprising: receiving a grayscale data for the first sub-pixel of a pixel having a first sub-pixel and a second sub-pixel by a source driver; The driver does not receive grayscale data for the second subpixel during a time period of one line that receives grayscale data for the first subpixel;
The source line voltage generation method of the display device includes:
Generating, by the source driver, a first source line voltage for the first subpixel from the grayscale data during a first portion of a time period of the one line;
The source driver determines a second source line voltage of the second sub-pixel during the second part of the time period of the one line during the second part of the time period of the one line. Generating the second source line voltage for the second sub-pixel of the pixel from the grayscale data of the first sub-pixel,
The time period of the one line is a time length during which the polarity signal is kept constant,
The method for generating a source line voltage of a display device, wherein the polarity signal repeats a logic high state and a logic low state every time period of the one continuous line. The source line voltage generation method includes:
Generating the first source line voltage from the gradation data and the first luminance curve;
The method of claim 1, further comprising: generating the second source line voltage from the gray level data of the first subpixel and a second luminance curve. Generating the first source line voltage comprises:
Selecting first high and low reference voltages for a D / A converter from at least one MSB side bit of the grayscale data from the first luminance curve;
Converting at least one LSB side bit of the grayscale data from a digital value to an analog value using the selected first high and low reference voltages in the D / A converter. The method for generating a source line voltage of a display device according to claim 2. Generating the second source line voltage comprises:
Selecting second high and low reference voltages for a D / A converter from at least one MSB side bit of the grayscale data from the second luminance curve;
Converting at least one LSB side bit of the grayscale data from a digital value to an analog value using the selected first high and low reference voltages in the D / A converter. The method for generating a source line voltage of a display device according to claim 3 .   The method of claim 3, wherein the D / A converter is linear.   3. The display source of claim 2, wherein the first and second luminance curves are both for a higher gamma reference voltage or both for a lower gamma reference voltage. Line voltage generation method. Wherein said first and second luminance curve is for the upper gamma reference voltage when the polarity signal for the sub Bupikuseru is driven with a positive polarity, when the polarity signal for the sub-pixels are driven with a negative polarity 7. The source line voltage generation method of a display device according to claim 6, wherein the source line voltage generation method is for a lower gamma reference voltage. 7. The first and second luminance curves for the upper or lower gamma reference voltage are used alternately to generate a continuous set of first and second source line voltages. A source line voltage generation method of the display device described. The source line voltage generation method of the display device includes:
Driving the first sub-pixel with the first source line voltage during the second portion of the time period of the one line;
2. The method of claim 1, further comprising: driving the second sub-pixel with the second source line voltage during a time period of one line following the time period of the one line. Source line voltage generation method for display device of the present invention. A source driver of a display device including a storage device for storing receiving transmission of the gradation data for the first sub-pixel of Lupi Kuseru which having a first sub-pixel and second sub-pixel, The source driver does not receive grayscale data for the second subpixel during a time period of one line that receives grayscale data for the first subpixel.
The source driver of the display device is:
A first source line voltage for the first sub-pixel from the grayscale data during a first part of the time period of the one line, and a source of the second part of the time period of the one line. A second source line voltage of the second sub-pixel is determined during the second part of the time period of the one line by a driver during the second part of the time period of the one line. A source line voltage generator for generating a second source line voltage for the second subpixel of the pixel from the grayscale data of the first subpixel;
Including
The time period of the one line is a time length during which the polarity signal is kept constant,
The source driver of a display device, wherein the polarity signal repeats a logic high state and a logic low state every time period of the one continuous line .   The source line voltage generator generates the first source line voltage from the gray level data and the first luminance curve, and generates the second source line voltage from the gray level data and the second luminance curve of the first subpixel. 11. The source driver of the display device according to claim 10, wherein the source driver is generated. The source line voltage generator is
A D / A converter;
From the first and second luminance curves, a first high and low reference voltage and a second high and low reference voltage for the D / A converter are obtained by at least one MSB side bit of the grayscale data. A reference voltage generator for selecting,
The D / A converter converts the at least one LSB side bit of the grayscale data with the selected first high and low reference voltages to generate the first source line voltage, and the selected first and second reference voltages. 12. The source driver of claim 11, wherein the second source line voltage is generated with two high and low reference voltages. The reference voltage generator is
An A / B selector for selecting each set of reference voltages from the first and second luminance curves according to which subpixel is driven;
An upper / lower selector for selecting one of each set of reference voltages from the A / B selector according to which polarity is indicated;
A VH-VL selector for selecting a high and low reference voltage from the set of selected reference voltages according to a selection signal generated from at least one MSB side bit of the grayscale data. The source driver of the display device according to claim 12.   13. The source driver of the display device according to claim 12, wherein the D / A converter is linear.   13. The source driver of a display device according to claim 12, wherein the D / A converter is a charge redistribution D / A converter.   12. The display source of claim 11, wherein the first and second luminance curves are both for a higher gamma reference voltage or both for a lower gamma reference voltage. driver.   The first and second luminance curves are for the upper gamma reference voltage when the polarity signal for the sub-pixel is driven with a positive polarity, and when the polarity signal for the sub-pixel is driven with a negative polarity. 17. The display device source driver according to claim 16, wherein the source driver is for a lower gamma reference voltage.   The display device of claim 16, wherein the luminance curve for the upper and lower gamma reference voltages is used alternately to generate a continuous set of first and second source line voltages. Source driver.   The first pixel is driven with the first source line voltage during a second portion of the time period of the one line, and is a portion of the time period of one line that is continuous after the time period of the one line. The source driver of claim 10, wherein the second subpixel is driven by the second source line voltage. A display panel having a plurality of gate lines and source lines;
A gate driver for generating a scan signal of the gate line;
A source driver for generating a source line voltage of the source line;
Including
Each of the source drivers is
A storage device for receiving and storing grayscale data for a first subpixel of a pixel , wherein the source driver is for a time period of one line for receiving grayscale data for the first subpixel. , No grayscale data is received for the second subpixel , and the respective source drivers receive a first for the first subpixel from the grayscale data during a first portion of the time period of the one line. During the second portion of the time period of the one line, a second source line voltage of the second subpixel is applied by the source driver during the second portion of the time period of the one line. From the grayscale data of the first subpixel as determined during the second portion of the time period of the one line, the second subpixel of the pixel Includes a source line voltage generator, for generating the second source line voltage of the order,
The time period of the one line is a time length during which the polarity signal is kept constant,
The display device, wherein the polarity signal repeats a logic high state and a logic low state for each time period of the one continuous line .   The source line voltage generator generates the first source line voltage from the gray level data and the first luminance curve, and generates the second source line voltage from the gray level data and the second luminance curve of the first subpixel. 21. The display device according to claim 20, wherein: The source line voltage generator is
A D / A converter;
A first high and low reference voltage and a second high and low reference voltage are selected for the D / A converter according to at least one MSB side bit of the grayscale data from the first and second luminance curves. A reference voltage generator for, and
The D / A converter converts the at least one LSB side bit of the grayscale data with the selected first high and low reference voltages to generate the first source line voltage, and the selected first and second reference voltages. The display device of claim 21, wherein the second source line voltage is generated with two high and low reference voltages. The reference voltage generator is
An A / B selector for selecting each set of reference voltages from the first and second luminance curves according to which subpixel is driven;
An upper and lower selector for selecting one of each set of reference voltages from the A / B selector according to which polarity is indicated;
A VH-VL selector for selecting a high and low reference voltage from the set of selected reference voltages according to a selection signal generated from at least one MSB side bit of the grayscale data. The display device according to claim 22 .   The display device according to claim 22, wherein the D / A converter is linear.   The display device according to claim 22, wherein the D / A converter is a charge redistribution D / A converter.   The display device of claim 21, wherein the first and second luminance curves are both for a higher gamma reference voltage or both for a lower gamma reference voltage.   The first and second luminance curves are for the upper gamma reference voltage when the polarity signal for the sub-pixel is driven with a positive polarity, and when the polarity signal for the sub-pixel is driven with a negative polarity. 27. The display device of claim 26, wherein the display device is for a lower gamma reference voltage. The first and second luminance curves for the upper or lower gamma reference voltage are used alternately to generate a continuous set of first and second source line voltages. 26. The display device according to 26.   The display device according to claim 20, wherein the display panel is a liquid crystal display device.   During the second portion of the time period of the one line, the first sub-pixel is driven with the first source line voltage, and the time period of one line following the time period of the one line. 21. The display device of claim 20, wherein the second sub-pixel is driven by the second source line voltage.

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