JP5696510B2 - Epitaxial wafer manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing an epitaxial wafer, and more particularly to a method for manufacturing an epitaxial wafer capable of compensating for a decrease in dopant concentration in a silicon wafer caused by hydrogen baking.

  An epitaxial wafer is usually produced by forming a silicon epitaxial layer having a different impurity concentration from the silicon wafer on the surface of the silicon wafer. For example, an epitaxial wafer is used when it is desired to form a silicon layer having a low impurity concentration on the surface of a silicon wafer having a high impurity concentration. Alternatively, in a semiconductor device in which current flows in a direction perpendicular to the main surface of a silicon wafer, such as an IGBT, silicon layers having different impurity concentrations must be stacked in the vertical direction. A wafer may be used (see Patent Document 1).

JP 2004-327716 A

  Unlike these normal epitaxial wafers, an epitaxial wafer in which the impurity concentration of the silicon wafer is equal to the impurity concentration of the silicon epitaxial layer is also conceivable. This type of epitaxial wafer has the advantage that the surface layer region in which the device is formed can be made defect-free without having a difference in impurity concentration in the vertical direction. In addition, an SOI (Silicon On Insulator) wafer has an advantage that the thickness of the SOI layer can be increased by forming an epitaxial layer having the same impurity concentration on the surface of the SOI layer, which is a device formation region.

  However, in this type of epitaxial wafer, the impurity concentration may decrease at the interface between the silicon wafer and the epitaxial layer, and the resistance value of this portion may increase. Originally, this type of epitaxial wafer is characterized in that the silicon wafer and the epitaxial layer can be identified with each other. However, when the impurity concentration fluctuates at the interface, this characteristic is impaired. In particular, when manufacturing a high-resistance epitaxial wafer, this becomes a more prominent problem.

  Accordingly, an object of the present invention is to provide an epitaxial wafer manufacturing method capable of preventing a decrease in impurity concentration at the interface between a silicon wafer and an epitaxial layer.

  The inventors of the present invention have intensively studied the cause of the decrease in the impurity concentration at the interface between the silicon wafer and the epitaxial layer in the epitaxial wafer in which the impurity concentration of the silicon wafer is equal to the impurity concentration of the epitaxial layer. As a result, normally, before the epitaxial growth process, the silicon wafer is heated to a temperature equal to or higher than the epitaxial growth temperature in a hydrogen gas atmosphere for the purpose of removing the natural oxide film on the silicon wafer surface and cleaning the surface. It was found that heat treatment for a period of time (hereinafter referred to as “hydrogen bake”) was performed, and the decrease in the impurity concentration at the interface was caused by the outward diffusion of dopant from the silicon wafer during hydrogen bake performed before this epitaxial growth. The present invention has been made based on such technical knowledge.

  An epitaxial wafer manufacturing method according to the present invention includes introducing hydrogen gas and a dopant gas containing a dopant of the same conductivity type as a silicon wafer into a reaction furnace to heat-treat the silicon wafer so that the dopant is contained in the silicon wafer. And a second step of forming a silicon epitaxial layer on the surface of the silicon wafer by introducing a silicon source gas into the reactor after performing the first step. The concentration of the dopant gas introduced in the first step is adjusted so that the impurity concentration of the silicon wafer after the formation of the epitaxial layer becomes equal to the impurity concentration of the silicon wafer before the first step. .

  According to the present invention, since a dopant gas containing a dopant having the same conductivity type as the impurity contained in the silicon wafer is introduced into the hydrogen bake performed before the epitaxial growth process, the surface layer of the silicon wafer is lowered due to outward diffusion. Impurity concentration is supplemented. Thereby, it is possible to manufacture an epitaxial wafer in which a decrease in impurity concentration in the surface layer portion of the silicon wafer is suppressed.

  In the second step, the concentration of the dopant gas introduced in the second step may be adjusted so that the impurity concentration of the epitaxial layer becomes equal to the impurity concentration of the silicon wafer before the first step. preferable. According to this, the impurity concentration of the silicon wafer surface layer portion that decreases due to outward diffusion is compensated, the impurity concentration of the silicon wafer and the impurity concentration of the epitaxial layer are equal, and the impurity concentration at the interface between the silicon wafer and the epitaxial layer It is possible to manufacture an epitaxial wafer in which the decrease in the resistance is suppressed.

  In the present invention, “the impurity concentration of the silicon wafer after the formation of the epitaxial layer is equal to the impurity concentration of the silicon wafer before the first step” means that the impurity concentration is completely matched. Instead, it includes the case where the impurity concentration is slightly different in a practically usable range. Specifically, although depending on the specification of the required specific resistance range, the difference in the specific resistance of the silicon wafer after forming the epitaxial layer is generally ± 10 with respect to the impurity concentration of the silicon wafer before the first step. It can be considered that the impurity concentration is equal if it is within the range of the impurity concentration difference that is within%.

  Similarly, the phrase “the impurity concentration of the epitaxial layer is equal to the impurity concentration of the silicon wafer before the first step” does not require that the impurity concentrations completely match, but the silicon wafer and the epitaxial layer If the specific resistance difference is within the range of the impurity concentration difference within ± 10%, it can be considered that the impurity concentration is equal.

  The first step includes a temperature raising step for raising the temperature in the reactor, and a temperature holding step for keeping the temperature in the reactor after the temperature raising step, and introducing the dopant gas Is preferably started from the temperature raising step. According to this, it is possible to compensate for impurities lost due to outward diffusion at the time of temperature rise.

  In the present invention, the silicon wafer is preferably an SOI wafer in which an insulating film is embedded. In an SOI wafer, it is difficult to ensure a sufficient thickness of the SOI layer depending on the manufacturing method. However, according to the present invention, the SOI layer is formed by forming an epitaxial layer without causing a difference in impurity concentration in the vertical direction. It becomes possible to increase the film thickness.

  The method for manufacturing an epitaxial wafer according to the present invention preferably further includes a step of manufacturing the SOI wafer by embedding the insulating film by oxygen ion implantation and heat treatment. The above method is generally called a SIMOX (Separation by Implanted Oxygen) method. When an insulating film is embedded, the depth of the insulating film is limited by the acceleration energy at the time of ion implantation. Since only an SOI layer of about 1 μm can be formed, a thicker SOI layer cannot be formed. However, according to the present invention, even when the insulating film is embedded by such a method, the thickness of the SOI layer can be sufficiently increased by forming the epitaxial layer without causing a difference in impurity concentration in the vertical direction. It can be secured.

  An epitaxial wafer manufacturing method according to the present invention includes a step of implanting an ion-implanted layer in a lower layer of the insulating film by performing ion implantation on the first wafer having the insulating film formed on the surface, and through the insulating film. The method further includes a step of manufacturing a bonded wafer by bonding the first wafer and the second wafer, and a step of manufacturing the SOI wafer by peeling the bonded wafer with the ion implantation layer. It is also preferable. The above method is generally called a Smart Cut (registered trademark) method, and when forming an ion implantation layer, the formation depth of the ion implantation layer is limited by the acceleration energy at the time of ion implantation. Therefore, as in the SIMOX method, it is difficult to form a thick SOI layer. However, according to the present invention, even when the ion implantation layer is formed by such a method, the thickness of the SOI layer can be reduced by forming the epitaxial layer without causing a difference in impurity concentration in the vertical direction. It is possible to ensure sufficient.

  Thus, according to the present invention, it is possible to manufacture an epitaxial wafer in which a decrease in impurity concentration at the interface between the silicon wafer and the epitaxial layer is prevented.

1 is a schematic cross-sectional view showing the structure of an epitaxial wafer 10 according to a preferred first embodiment of the present invention. 4 is a schematic cross-sectional view showing the structure of an epitaxial wafer 20 according to a preferred second embodiment of the present invention. FIG. 3 is a flowchart for explaining a manufacturing process of the epitaxial wafer 10 according to the first embodiment. It is a schematic diagram which shows an example of an epitaxial growth apparatus. It is a typical graph which shows the relationship between the temperature change in a reaction furnace, and each process. It is a schematic diagram for demonstrating an example of the manufacturing process of the epitaxial wafer 20 by 2nd Embodiment. It is a schematic diagram for demonstrating the other example of the manufacturing process of the epitaxial wafer 20 by 2nd Embodiment. It is a graph which shows the resistance profile in the interface of a silicon wafer and an epitaxial layer in a comparative example. It is a graph which shows the density | concentration profile in the interface of a silicon wafer and an epitaxial layer in a comparative example. 4 is a graph showing the relationship between the temperature change in the reaction furnace and each step in Example 1. 2 is a graph showing a resistance profile at an interface between a silicon wafer and an epitaxial layer in Example 1. 5 is a graph showing a resistance profile at an interface between a silicon wafer and an epitaxial layer in Example 2.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic cross-sectional view showing the structure of an epitaxial wafer 10 according to a first preferred embodiment of the present invention.

  As shown in FIG. 1, the epitaxial wafer 10 according to the present embodiment has a silicon wafer body 11 and an epitaxial layer 12 formed on the surface thereof. The type and concentration of impurities contained in the silicon wafer body 11 and the type and concentration of impurities contained in the epitaxial layer 12 are substantially the same. Moreover, there is no large variation in the impurity concentration at the interface 13 between the silicon wafer body 11 and the epitaxial layer 12. A method for manufacturing the epitaxial wafer 10 according to the present embodiment will be described later.

  FIG. 2 is a schematic cross-sectional view showing the structure of the epitaxial wafer 20 according to the second preferred embodiment of the present invention.

  As shown in FIG. 2, the epitaxial wafer 20 according to the present embodiment includes an SOI wafer body 21 and an epitaxial layer 22 formed on the surface thereof. The SOI wafer main body 21 includes an SOI layer 23, a support substrate 24, and a buried insulating layer 25 interposed therebetween. The type and concentration of impurities contained in the SOI layer 23 and the type and concentration of impurities contained in the epitaxial layer 22 are substantially the same. Moreover, there is no large variation in the impurity concentration at the interface 26 between the SOI layer 23 and the epitaxial layer 22. The method for manufacturing the epitaxial wafer 20 according to the present embodiment will also be described later.

  FIG. 3 is a flowchart for explaining a manufacturing process of the epitaxial wafer 10 according to the first embodiment.

First, the silicon wafer main body 11 is prepared and loaded into the reactor of the epitaxial growth apparatus (step S1). The structure of the epitaxial growth apparatus to be used is not particularly limited. An example of the epitaxial growth apparatus is shown in FIG. The epitaxial growth apparatus 30 shown in FIG. 4 includes a reaction furnace 31, a gas introduction pipe 32 for introducing gas into the reaction furnace 31, and a gas discharge pipe 33 for discharging gas from the reaction furnace 31. Hydrogen gas (H ₂ ), dopant gas, and silicon source gas are supplied to the gas introduction pipe 32 via valves 32a to 32c. Typical dopant gases include PH ₃ gas and B ₂ H ₆ gas. Examples of the silicon source gas include SiH ₂ Cl ₂ gas, SiHCl ₃ gas, and SiCl ₄ gas. The gas discharge pipe 33 is connected to the exhaust mechanism 34 via a valve 33a. A stage 35 for placing the silicon wafer main body 11 is provided inside the reaction furnace 31. A heating mechanism 36 for heating the silicon wafer body 11 is provided above and below the reaction furnace 31.

  Next, the silicon wafer body 11 is heated at a predetermined temperature increase rate by using the heating mechanism 36 while introducing the hydrogen gas into the reaction furnace 31 by opening the valve 32a (step S2). Thus, when the silicon wafer body 11 reaches a predetermined temperature, hydrogen baking is performed, and the surface of the silicon wafer body 11 is cleaned (step S3). At this time, in this embodiment, the dopant gas is introduced into the reaction furnace 31 by opening the valve 32b. As a result, the inside of the reaction furnace 31 in the hydrogen baking is a dopant gas atmosphere. The timing at which the valve 32b is opened, that is, the dopant gas introduction start timing may be in the middle of the temperature rise or after the temperature rise is completed.

  When hydrogen baking is performed, impurities contained in the silicon wafer body 11 are diffused outward by the heat, and the impurity concentration in the surface layer is lowered. However, in this embodiment, since a dopant gas containing a dopant having the same conductivity type as the impurities contained in the silicon wafer main body 11 is introduced into the hydrogen bake, impurities lost from the silicon wafer main body 11 due to outward diffusion are eliminated. As a result, a decrease in impurity concentration in the surface layer is prevented. Although the amount of outward diffusion depends on the hydrogen baking conditions (time and temperature), the impurity concentration contained in the silicon wafer body 11 after the epitaxial growth process is equal to the impurity concentration contained in the silicon wafer body 11 before the hydrogen baking. That is, by adjusting the concentration of the dopant gas introduced into the hydrogen bake so that the impurity concentration is constant in the thickness direction of the silicon wafer main body 11, fluctuations in the impurity concentration profile at the interface 13 can be minimized. It becomes possible.

  After the hydrogen baking is completed, the silicon raw material gas is introduced into the reaction furnace 31 by opening the valve 32c (step S4). Thereby, the surface of the silicon wafer main body 11 is epitaxially grown, and the epitaxial layer 12 is formed. At this time, it is preferable to adjust the dopant gas concentration so that the impurity concentration of the epitaxial layer 12 becomes equal to the impurity concentration of the silicon wafer body 11 by adjusting the opening of the valve 32b.

  The dopant gas concentration introduced when forming the epitaxial layer is preferably such that a higher concentration of dopant gas is introduced into the reaction furnace 31 than in the hydrogen baking because the volume is increased by the formation of the epitaxial layer 12. In other words, the concentration of the dopant gas introduced into the reaction furnace 31 during hydrogen baking is preferably adjusted to be lower than the concentration of the dopant gas introduced into the reaction furnace 31 during the epitaxial growth process. When a high-concentration dopant gas introduced during the epitaxial growth process is introduced during hydrogen baking, excess dopant is adsorbed or taken inwardly on the surface of the silicon wafer body 11 and conversely the resistance at the interface 31 is lowered. As a result, the impurity concentration profile varies.

The hydrogen baking must come to remove the natural oxide film present on the surface of the silicon wafer body 11, as the other conditions of the hydrogen ^{bake, 0.3 × 10 5 Pa~1.1 × 10} 5 The conditions etc. which hold | maintain for 15 seconds-5 minutes within the temperature range of 900 degreeC-1190 degreeC in the hydrogen gas atmosphere under the pressure of Pa can be illustrated. In any case, the concentration of the dopant gas introduced at the time of hydrogen baking may be adjusted so that the impurity concentration at the interface 13 between the epitaxial layer 12 and the silicon wafer main body 11 after the epitaxial growth process becomes equal. What is necessary is just to obtain | require gas concentration.

  After the epitaxial layer 12 is thus formed, the temperature of the epitaxial wafer 10 in the reaction furnace 31 is lowered (step S5). After the temperature is lowered to a predetermined temperature, the epitaxial wafer 10 is taken out from the reaction furnace 31 (step S6). . Thus, the epitaxial wafer 10 is completed.

  Thus, in this embodiment, since dopant gas is introduce | transduced in hydrogen baking, the impurity lost from the silicon wafer main body 11 by the outward diffusion at the time of hydrogen baking is carried out by the surface adsorption or inward diffusion of a dopant. This makes it possible to prevent a decrease in impurity concentration in the surface layer. Here, the relationship between the temperature at the time of hydrogen baking and the temperature at the time of epitaxial growth is not particularly limited, and the temperatures of both may be the same as shown in FIGS. As shown in c) and (d), the temperature during hydrogen baking may be higher. In addition, the introduction start timing of the dopant gas may be after the end of the temperature raising step (step S2) as shown in FIGS. 5 (a) and 5 (c). As shown in FIG. 4, it may be in the middle of the temperature raising step (step S2). In any case, the epitaxial growth process (step S4) in which the silicon source gas is introduced is performed in a temperature holding process in which the temperature in the reaction furnace is kept constant. 5A to 5D, the vertical axis represents temperature and the horizontal axis represents time.

  FIG. 6 is a schematic diagram for explaining an example of the manufacturing process of the epitaxial wafer 20 according to the second embodiment.

  In the example shown in FIG. 6, first, a silicon wafer 20a is prepared, and oxygen ions A are ion-implanted from one surface 20b. Next, the silicon wafer 20a after the ion implantation is subjected to, for example, a high-temperature heat treatment for 30 hours or more in an oxidizing gas atmosphere at a temperature of 1300 ° C. or more, thereby forming a buried insulating film 25 below the surface 20b. 21 is completed. Thereafter, the epitaxial layer 22 is formed on the surface of the SOI layer 23 by using the method described with reference to FIG. Thereby, the epitaxial wafer 20 is completed.

  When the epitaxial wafer 20 is manufactured by the above method, the film thickness of the SOI layer 23 is determined by the implantation depth of the oxygen ions A. Here, since the implantation depth of the oxygen ions A is limited by the acceleration energy at the time of ion implantation, it is difficult to form the thick SOI layer 23. However, according to the present embodiment, since the epitaxial layer 22 having the same impurity concentration is formed on the surface of the SOI layer 23, a substantially thick SOI layer can be obtained.

  FIG. 7 is a schematic diagram for explaining another example of the manufacturing process of the epitaxial wafer 20 according to the second embodiment.

  In the example shown in FIG. 7, first, a first wafer 40 having an insulating film 41 formed on the surface is prepared, and predetermined ions B are ion-implanted through the insulating film 41 to ion-implant into the lower layer of the insulating film 41. Embed layer 42. The type of ion B is not particularly limited, but hydrogen ions or rare gas ions are preferably selected.

  Next, the bonded wafer 44 is manufactured by bonding the first wafer 40 and the second wafer 43 through the insulating film 41. Then, the bonded wafer 44 is peeled off by the ion implantation layer 42 to complete the SOI wafer 21. Thereafter, the epitaxial layer 22 is formed on the surface of the SOI layer 23 by using the method described with reference to FIG. Thereby, the epitaxial wafer 20 is completed.

  When the epitaxial wafer 20 is manufactured by the above method, the film thickness of the SOI layer 23 is determined by the ion B implantation depth. Since the implantation depth of the ions B is limited by the acceleration energy at the time of ion implantation, it is difficult to form the thick SOI layer 23. However, according to the present embodiment, since the epitaxial layer 22 having the same impurity concentration is formed on the surface of the SOI layer 23, a substantially thick SOI layer can be obtained.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the present invention, the kind of impurities added to the silicon wafer and the epitaxial layer is not particularly limited, and boron (B) can be selected for p-type, and phosphorus (P) for n-type. Antimony (Sb) or arsenic (As) can be selected. In the present invention, the concentration of impurities added to the silicon wafer and the epitaxial layer is not particularly limited.

  In the present invention, the surface of the silicon wafer may be etched by introducing HCl gas into the reactor during hydrogen baking.

[Comparative example]
In the comparative example, the influence of the outward diffusion of impurities by hydrogen baking was evaluated. First, a phosphorus-doped silicon wafer grown by the Czochralski method and having a diameter of 200 mm and a thickness of 725 μm was prepared. The specific resistance of the silicon wafer is 4 Ωcm. A phosphorus-doped epitaxial layer having a specific resistance of 4 Ωcm was formed on the surface of the silicon wafer.

In the formation of the epitaxial layer, as a pretreatment, hydrogen gas was introduced into the reaction furnace, and the silicon wafer was hydrogen baked at a temperature of 1125 ° C. The baking time was set to three types of 30 seconds, 60 seconds, and 180 seconds, and no dopant gas was introduced into the reactor during hydrogen baking. Thereafter, trichlorosilane (SiHCl ₃ ) gas as a silicon source gas and phosphine (PH ₃ ) as a dopant gas are introduced into the reactor so that a phosphorus-doped epitaxial layer having a specific resistance of 4 Ωcm is formed at 1125 ° C. Epitaxial growth was performed. At this time, the amount of introduced dopant gas is 220 cc.

  After the epitaxial layer was formed, the resistance profile at the interface between the silicon wafer and the epitaxial layer was measured by the CV measurement method. The results are shown in FIG. Further, a concentration profile at the interface was calculated from the obtained resistance value. The results are shown in FIG.

  As shown in FIGS. 8 and 9, it was confirmed that the impurity concentration was lowered at the interface between the silicon wafer and the epitaxial layer, thereby increasing the resistance value. This tendency becomes more prominent as the hydrogen baking time is longer. This is considered to be because impurities contained in the silicon wafer are diffused outward by hydrogen baking.

[Example 1]
In Example 1, the hydrogen baking time was set to 60 seconds, and phosphine was introduced into the hydrogen baking as a dopant gas. The amount of dopant gas introduced during hydrogen baking was three types of 100 cc, 110 cc, and 150 cc. The introduction of the dopant gas was started in the middle of the temperature raising period. More specifically, as shown in FIG. 10, the introduction of the dopant gas is started when the temperature reaches 900 ° C. in the temperature raising period for raising the temperature from 750 ° C. to 1125 ° C., reaches 1125 ° C. and reaches the temperature holding period. After 60 seconds had passed, the introduction of silicon source gas was started. After the introduction of the silicon source gas was started, the amount of dopant gas introduced was adjusted to 220 cc so that the specific resistance of the silicon epitaxial layer to be formed was 4 Ωcm. Other conditions are the same as the comparative example described above.

  After the epitaxial layer was formed, the resistance profile at the interface between the silicon wafer and the epitaxial layer was measured by the CV measurement method. The results are shown in FIG. For comparison, FIG. 11 also shows data when no dopant gas is introduced (data of a comparative example).

  As shown in FIG. 11, it can be seen that when the dopant gas is added to the hydrogen bake, the increase in the resistance value at the interface between the silicon wafer and the epitaxial layer is significantly suppressed. More specifically, when the dopant gas addition amount is 100 cc, a slight increase in the resistance value in the vicinity of the interface remains, and when the dopant gas addition amount is 150 cc, the resistance value in the vicinity of the interface. In both cases, a good resistance profile was obtained. In particular, when the dopant gas addition amount was 110 cc, the resistance profile in the vicinity of the interface could be made almost flat.

[Example 2]
In Example 2, an epitaxial layer was formed under the same conditions as in Example 1 except that an SOI wafer was used and the amount of phosphine as a dopant gas introduced was 110 cc over 180 seconds. The specific resistance of the SOI layer is 4 Ωcm. And after forming an epitaxial layer, the resistance profile in the interface of a silicon wafer and an epitaxial layer was measured by the CV measuring method. The results are shown in FIG. For comparison, FIG. 12 also shows data when no dopant gas is introduced (data of a comparative example). As shown in FIG. 12, even when an SOI substrate was used, the resistance profile in the vicinity of the interface was almost flat.

DESCRIPTION OF SYMBOLS 10 Epitaxial wafer 11 Silicon wafer main body 12 Epitaxial layer 13 Interface 20 Epitaxial wafer 20a Silicon wafer 20b Silicon wafer surface 21 Wafer main body 22 Epitaxial layer 23 SOI layer 24 Support substrate 25 Embedded insulating layer 26 Interface 30 Epitaxial growth apparatus 31 Reactor 32 Gas introduction Tubes 32a to 32c Valve 33 Gas exhaust tube 33a Valve 34 Exhaust mechanism 35 Stage 36 Heating mechanism 40 Wafer 41 Insulating film 42 Ion implantation layer 43 Wafer 44 Wafer

Claims (5)

A first step of in-diffusion of the dopant into the silicon wafer by introducing a hydrogen gas and a dopant gas containing a dopant of the same conductivity type as the silicon wafer into the reaction furnace to heat-treat the silicon wafer;
After performing the first step, a second step of introducing a silicon source gas into the reactor to form a silicon epitaxial layer on the surface of the silicon wafer,
The first step includes a temperature raising step for increasing the temperature in the reaction furnace, and a temperature holding step for holding the temperature in the reaction furnace after the temperature raising step is completed, and the first step Starting the introduction of the dopant gas in the temperature raising step,
The dopant gas concentration introduced in the first step is introduced in the second step so that the impurity concentration of the silicon wafer after the epitaxial layer formation is equal to the impurity concentration of the silicon wafer before the first step. A method for producing an epitaxial wafer, wherein the concentration is adjusted to be lower than the concentration of the dopant gas .   The concentration of the dopant gas introduced in the second step is adjusted so that the impurity concentration of the epitaxial layer becomes equal to the impurity concentration of the silicon wafer before the first step. Epitaxial wafer manufacturing method. The silicon wafer is an epitaxial wafer manufacturing method according to claim 1 or 2, characterized in that the insulating film is a SOI wafer embedded. 4. The method of manufacturing an epitaxial wafer according to claim 3 , further comprising the step of fabricating the SOI wafer by embedding the insulating film by ion implantation of oxygen ions and heat treatment. A step of burying an ion implantation layer in a lower layer of the insulating film by performing ion implantation on the first wafer having the insulating film formed on the surface; and the first wafer and the second wafer via the insulating film 4. The method according to claim 3 , further comprising a step of manufacturing a bonded wafer by bonding together and a step of manufacturing the SOI wafer by peeling the bonded wafer with the ion implantation layer. Epitaxial wafer manufacturing method.

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