JPH0360043A - Manufacture of semiconductor thin film and manufacture of thin film transistor using the semiconductor thin film - Google Patents

Abstract

PURPOSE:To control a production position of a crystal nucleus by forming a fine projecting matter by a polycrystalline thin film semiconductor layer and by forming an amorphous semiconductor thin film thereon for crystal growth around the projecting matter. CONSTITUTION:A low resistance semiconductor layer 4 to form source/drain regions is formed and patterned on a glass substrate 3. Simultaneously, a projecting matter is provided to nearly a middle between two channels. Then, after an amorphous silicon film is formed as an active layer 5 and annealed for polycrystallization, it is islanded to acquire a crystal grain 6 around the projecting matter in the middle of a channel. Film formation is carried out for a gate insulating film 7 and a gate electrode 8 to form a gate electrode pattern. Then, source/drain regions of low concentration is formed self-matchingly by ion implantation using the gate electrode as a mask. After a passivation film is formed, a contact hole is formed. Then, a film of an elec trode metal layer 11 is formed and an electrode pattern is formed. Thereby, it is possible to control a position of a crystal grain and to manufacture a thin film transis tor without grain boundary across a channel inside the channel in a simple process with good reproducibility.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor thin film in which a high-mobility semiconductor thin film is formed on an insulating substrate by a low-temperature process, and a high-mobility semiconductor thin film in which this semiconductor thin film is used. The present invention relates to a method for manufacturing a thin film transistor with high breakdown voltage and low leakage current.

(Prior art) In recent years, thin M on glass substrates! Technology for creating active devices is being applied to a variety of applications, including large-area transmissive liquid crystal displays and contact image sensors, and research is becoming more active.

Among them, a-3t:H, which can be uniformly formed into a film over a large area, is already being applied to the product level. However, a-3
t:H has a very low mobility, which limits its field of application. In other words, it can be applied as an optical sensor or a switching device, but if you try to create peripheral circuits to drive these devices at the same time, the mobility is about 1/1000th that of single-crystal silicon, so it cannot be Currently, such drive circuits are fabricated on silicon wafers and connected to thin film devices using wire bonding.

However, from the viewpoint of manufacturing cost and wiring yield, it will be necessary to make the entire structure thinner in the future.

In order to make the entire film thinner, a means to fabricate a high-mobility thin film on a glass substrate is required. Recently, it has become possible to obtain single-crystal silicon on a glass substrate, but this requires a fairly high-temperature process, and other parts, including the glass substrate, are exposed to high temperatures. As a result, a material with high heat resistance must be used as the glass substrate, which causes problems such as damage to other parts.

Therefore, active research is being conducted to create semiconductor thin films and thin film active devices with uniformly high mobility using low-temperature processes. As one of these, research and development on polycrystalline silicon TPT is being conducted.

FIGS. 5(a) and 5(b) are a plan view and a sectional view showing 13fi of a conventional planar thin film transistor. This structure is obtained through the following manufacturing steps.

That is, first, polycrystalline silicon is formed on the insulating substrate 3,
After forming the polycrystalline silicon 5 which becomes the zero-order active layer forming the source/drain low resistance semiconductor layer 4 into an island and forming the gate insulator 1li7 and the gate electrode 8, the gate electrode is patterned. Thereafter, source/drain regions are formed by ion implantation using the gate'@pole 8 as a mask. Further, an interlayer insulating film 10 is formed, a contact hole is formed, and a metal wiring 11 is formed.

Here, the performance of transistors has been significantly improved by making the thin film semiconductor layer, which becomes the active layer, ultra-thin to 500 Å or less, and recently, the electric field - noodle mobility has been improved to 100 cm at low temperatures.
'/V,s or higher performance can be obtained.

(Problems to be Solved by the Invention) However, in polycrystalline silicon thin film transistors, scattering at crystal grain boundaries is a major factor that impedes mobility, and as long as grain boundaries are included, it is difficult to further improve performance.

Recent research has shown that crystal grain sizes of about 5 μm can be produced using low-temperature solid-phase growth methods for amorphous silicon, and in the case of such large-grain polycrystalline silicon films, even one grain boundary exists inside the channel. It is not impossible to fabricate thin film transistors that do not contain the same.

To achieve this, it is necessary to manufacture transistors that match the crystal grains, but it is currently difficult to control the position of crystal nucleation, so it is not practical to manufacture transistors that do not contain grain boundaries inside the channel. It is difficult to do so. Moreover, as the crystal grains become larger, the number of grain boundaries included within the channel decreases, which also has the disadvantage of increasing variations in transistor characteristics.

Therefore, the present invention provides a film formation method that can control the position of crystal nucleus generation, and uses this film formation method to control the position of crystal nucleus generation so that it always occurs at the center of the transistor channel, thereby reducing the size of the transistor channel. This provides a method of manufacturing a thin film IC without always including crystal grain boundaries in the transistor channel by keeping the thickness within 5 μm.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the method for manufacturing a semiconductor thin film of the present invention deposits amorphous silicon on an insulating substrate,
A method for manufacturing a semiconductor thin film in which crystals are grown by low-temperature annealing at 0° C. or lower, which includes a step of forming minute protrusions using a polycrystalline thin film semiconductor layer, forming an amorphous semiconductor thin film on top of the micro-protrusions, and forming the amorphous semiconductor thin film on top of the micro-protrusions. and a step of growing a crystal.

Furthermore, the method for manufacturing a thin film transistor of the present invention includes forming a low-resistance semiconductor layer on an insulating substrate, and patterning this low-resistance semiconductor layer to form source/drain regions and protrusions that can serve as growth nuclei. a step of growing crystals around the protrusions by annealing the amorphous silicon film formed thereon at a low temperature of 650° C. or less;
A step of forming a channel having a width equal to or less than the grain size of the crystal while avoiding the protrusion so that the protrusion is located in the center of the channel, and a step of forming a gate insulating film and a gate electrode on the upper part of the channel. .

(Effect) It is clear that the nucleus of crystal growth is generated from the interface between the substrate and the silicon film.If the substrate has unevenness, stress will be generated in the film, and there is a high possibility that the nucleus will become there. .

In the present invention, a protrusion is formed in the center of the channel, and the crystal is grown around the protrusion, thereby making it possible to control the position of the crystal. If this protrusion is made at the same time as the layer that forms the low resistance layer of the source and drain, L
4. There is no increase in the number of sheets compared to the manufacturing process of DD structure thin film transistors. In addition, only the inside of the crystal grains that have grown around these protrusions are used as channels, and in order to prevent interlayer leakage, the part with the protrusions is avoided to create a double channel structure, which does not include grain boundaries. Transistors can be manufactured with good controllability.

Note that the boundary between the source and drain silicon layers can also become the nucleus of crystal grains, but microprotrusions have greater stress and nucleation is more likely to occur, and crystal growth occurs from the source and drain boundary. However, by controlling the distance between the channel part and this source/drain semiconductor layer, the channel part can be controlled so as not to include crystal grain boundaries. It is possible to exclude it.

Further, the transistor with this structure has an LDDII structure in which the doping concentration is low only near the drain end, and the withstand voltage between the source and the train is high, and leakage current is also improved compared to conventional transistors. Furthermore, since the drain end does not contain grain boundaries, emissive current via grain boundary traps, which is said to be the cause of leakage current in polycrystalline silicon thin film transistors, is also suppressed, resulting in a considerable improvement in leakage current. As a result, higher speed and lower leakage current can be achieved.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) shows a semiconductor thin film formed by the method for manufacturing a semiconductor thin film according to the present invention.

An amorphous semiconductor film is formed on micro-protrusions 1 of polycrystalline semiconductor formed in advance on an insulating substrate, and heated at 600°C to 650°C.
Annealing is performed at a temperature of
is grown to form a polycrystalline semiconductor thin film in which crystal grains 2 are arranged in an orderly manner.

On the other hand, the same figure (b) shows a polycrystalline semiconductor thin film formed by the conventional solid phase growth method, but since there is no protrusion 1, a polycrystalline semiconductor thin film is created in which the crystal grains are randomly arranged. I understand that.

FIGS. 2(a) to 2(h) are process diagrams showing one embodiment of the manufacturing method according to the present invention, and FIG.

(c), (e), and (g> are plan views of the apparatus in each step, and (b), (d), (f), and (h) are cross-sectional views of the apparatus in each step.

First, as shown in FIGS. 2(a) and 2(b), a low resistance semiconductor layer 4 for forming source/drain regions is formed on a glass substrate 3 and patterned. At this time, a protrusion is simultaneously provided in the 0-order active layer 5 approximately at the center between the two channels.
As a result, 2000 people deposited amorphous silicon, and 600 ~
After annealing at 650° C. to polycrystallize by solid phase growth, it is made into an island. During this growth, since the protrusion at the center of the channel tends to become a nucleus for crystal growth, crystal grains 6 as shown by dotted lines are obtained around this protrusion. As a result, there is no grain boundary that crosses the channel within the channel.At this time, short-circuits between the eyebrows are likely to occur at the point of the protrusion, so the channel has a double channel structure (second Figures (C), (d)).

Then, a gate insulating film 7 and a gate "t[!8" are formed to form a gate electrode pattern. Then, using the gate electrode as a mask, low concentration source/drain regions are formed in a self-aligned manner by ion implantation. (Figure 2(e), (
f)) After forming the passivation film, a contact hole is formed. Thereafter, by depositing and removing the first electrode metal layer and forming an electrode pattern, a transistor containing no crystal grain boundaries inside the channel can be easily obtained (FIG. 2(g)).

(h)) Furthermore, according to the method of the present invention, an LDD structure with low leakage current can be obtained, and furthermore, it does not require a selective etching process and has high controllability and reproducibility.

A characteristic diagram showing the change in drain current due to gate voltage of an actually manufactured thin film transistor is shown in Figure 4.In Figure 4, the solid line is the characteristic of the thin film transistor manufactured by the method of the present invention, and the broken line is the characteristic of the thin film transistor manufactured by the conventional method. These are the characteristics of the manufactured polycrystalline silicon thin film transistor. As is clear from FIG. 4, both field effect mobility and leakage current are greatly improved.

In addition, if you want to obtain a transistor with a large channel width, each channel width should be 5.
If the number of channels is increased by increasing the number of channels while keeping the size smaller than μm, a transistor with any W/L ratio can be manufactured. In this case, as shown in the figure, channels are formed avoiding the protrusion portions and grain boundary portions.

(Effects of the Invention) As detailed above, the thin film manufacturing method according to the present invention enables control of the position of crystal grains. Further, by a method of manufacturing a thin film transistor using this film forming property, a thin film transistor that does not include at least a grain boundary crossing the channel inside the channel can be manufactured with good reproducibility through simple steps.

Furthermore, the thin film transistors obtained by this manufacturing method have small variations in threshold values, etc., allowing a high margin in circuit design.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are diagrams showing semiconductor thin films obtained by the present invention and the conventional method, and FIGS. 2(a) to (h) are plan views of the apparatus in each step of the manufacturing method according to the present invention. 3(a) and 3(b) are diagrams showing an example of obtaining a transistor with a large channel width, and FIG. 4 is a diagram showing characteristics of transistors obtained by the present invention and the conventional method. FIGS. 5(a) and 5(b) are diagrams showing a conventional polycrystalline thin film transistor. DESCRIPTION OF SYMBOLS 1... Protrusion, 2... Semiconductor thin film, 3... Source/drain low resistance semiconductor layer, 5... Semiconductor layer, 6...
・Crystal grain, 7... Gate insulating film, 8... Gate insulating film, 9... Impurity ion, 10... Interlayer insulating film, 1
1... Electrode metal.

Claims (2)

[Claims] (1) Depositing amorphous silicon on an insulating substrate,
A method for producing a semiconductor thin film in which crystal growth is performed by low-temperature annealing at a temperature below 10°C includes a step of forming microprotrusions using a polycrystalline thin film semiconductor layer, forming an amorphous semiconductor thin film on top of the microprotrusions, and growing crystals around the protrusions. 1. A method for manufacturing a semiconductor thin film, comprising the step of growing a semiconductor thin film. (2) A process of forming a low-resistance semiconductor layer on an insulating substrate, patterning this low-resistance semiconductor layer to form source/drain regions, and forming protrusions that can serve as growth nuclei, and forming a film on this layer. The amorphous silicon film was heated to 650°C.
A step of growing a crystal around the protrusion by low-temperature annealing as described below, a step of forming a channel with a width equal to or less than the grain size of the crystal while avoiding the protrusion so that the protrusion is located in the center of the channel; A method for manufacturing a thin film transistor, comprising the steps of forming a gate insulating film and a gate electrode above a channel.