JPH0444238A - Manufacture of electric field transistor - Google Patents

Abstract

PURPOSE:To enable a gate whose section is in T shape or mushroom shape to be formed by forming a groove in reverse taper shape for cladding a gate metal at a second resist on a first resist where a tentative gate exists. CONSTITUTION:First, a tentative gate 12 is formed at a region where a gate is formed on a semiconductor substrate 10 (a). Then, a first resist 14 is spin- coated (b). Then, this first resist 14 is etched so that a specified amount of upper part of the tentative gate is exposed (c). A metal 16 is formed on a surface of this first resist 14 (d). Then, a second resist 18 is spin-coated on this Ni metal film 16 and the groove 20 in reverse taper shape is formed on the tentative gate 12 (e). The Ni metal film 16 within this groove is eliminated by using diluted hydrochloric acid etc. (f). Further, only the tentative gate 12 is eliminated by using buffer fluoric acid etc. (g). Then, a metal gate 22 is clad within the groove 20 (h). Then, only the gate 22 whose section is in T shape remains on the substrate 10 (i).

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a field effect transistor (hereinafter referred to as FET), and particularly to a method for manufacturing a gate having a T-shaped or mushroom-shaped cross section.

[Prior Art] Schottky junction FETs, so-called MESFETs, using compound semiconductors such as GaAs have been developed. This MESFET is suitable for miniaturization of gate length because of its simple structure and manufacturing process, and is widely used in elements with excellent high frequency characteristics and high-speed operation integrated circuits.

However, simply increasing the miniaturization of the gate length increases the electrical resistance of the gate, which on the contrary becomes a factor that impedes high-speed operation. Therefore, a method has been considered to form a gate with a T-shaped or pine mushroom-shaped cross section, with the lower part in contact with the active layer of the semiconductor being thin, and the upper part being thick.

As these methods, for example, a method using a multilayer resist and direct writing using an electron beam, a method using focused ion beam lithography, or a method combining a temporary gate and a planarization technique are known.

On the other hand, in order to realize higher speed FETs, not only miniaturization of the gate length but also reduction of source resistance is an important issue. For this reason, a structure is generally used in which the active layer in the source/drain region is formed deeper and has a higher impurity concentration than the active layer under the gate.

However, the misalignment between the active layer (high concentration layer) in the source/drain region and the gate becomes a problem as the gate length becomes finer as described above. For this reason, self-lined MESFETs in which source/drain regions and gates are configured in a self-aligned manner are widely used.

Such self-lined MESFETs can be manufactured by implanting ions into a highly concentrated layer using the heat-resistant gate as a mask, then performing heat treatment to electrically activate the ion-implanted layer while leaving the heat-resistant gate as is, or using a temporary gate. After forming a high concentration layer ion implantation using this temporary gate as a mask,
It is manufactured by a method in which heat treatment is performed while the temporary gate or an inverted pattern of the temporary gate remains on the semiconductor substrate, and a gate is formed at the position where the temporary gate existed.

[Problems to be Solved by the Invention] However, in order to miniaturize the gate length and reduce gate resistance, when forming the gate with the above-mentioned T-shaped or pine mushroom cross-sectional shape, direct writing using a multilayer resist and an electron beam is difficult. Methods using ion beam lithography and methods using focused ion beam lithography require the use of special equipment such as electron beam or ion beam direct writing equipment.
There was a problem that the manufacturing process became complicated.

In addition, when manufacturing heat-resistant gate type self-line MESFETs, which are most commonly used to reduce source resistance, the gate needs to withstand heat treatment (approximately 800 degrees Celsius) to activate the high concentration layer, as described above. Therefore, gate materials are limited to compounds based on W or Ta, which are high melting point metals, and the resistivity thereof is several tens of times higher than that of ordinary metals.

Therefore, the applicant of the present application previously proposed in Japanese Patent Application No. 1-120989 a method of forming gates by skillfully using image reverse photolithography.

In this manufacturing method, a resist pattern with a constant thickness remains at the bottom and a temporary gate is combined with a gate-forming resist pattern having a groove whose cross-sectional width becomes narrower toward the opening. A gate having a T-shaped cross section can be formed in a process without using a high-resistance heat-resistant material.

However, when forming a gate with a T-shaped cross section using image reverse photolithography, it is necessary to precisely control various parameters of image reverse photolithography, such as exposure amount, baking time, development time, etc. There is.

The present invention has been made in view of the above-mentioned prior art and the manufacturing method proposed by the present applicant, and its purpose is to provide a method for manufacturing an FET that can form a gate with a T-shaped cross section or a pine mushroom shape in a simple process. Our goal is to provide the following.

[Means for Solving the Problems] In order to achieve the above object, a method for manufacturing an FET according to the present invention includes a step of forming a temporary gate in a region on a semiconductor substrate where a gate is to be formed, and a step of forming a temporary gate on a region where a gate is to be formed. applying a first covering resist to the surface of the semiconductor substrate; etching the first resist to expose a predetermined amount of the upper part of the temporary gate; and forming a thin film on the etched first resist surface. a step of applying a second resist on the formed thin film; and a step of applying a second resist on the formed thin film, and forming a reverse tapered shape in which the width becomes wider from the resist surface toward the thin film in a region of the second resist located above the temporary gate. forming a groove, removing the thin film and the temporary gate in the groove, depositing a gate metal thinner than the second resist in the groove, and depositing a gate metal thinner than the second resist in the groove; The method is characterized in that it has a step of removing the resist.

[Operation] As described above, in the FET manufacturing method according to the present invention, an inversely tapered groove for depositing the gate metal is formed in the second resist on the first resist where the temporary gate is present. For example, even if image reverse photolithography is used to form this groove, there is no need to leave any resist at the bottom of the groove because there is a thin film between the first resist and the second resist. Therefore, it is not necessary to precisely control various parameters such as exposure, baking, and development when forming the grooves in the method previously proposed by the present applicant.

Note that in the case of a self-lined MESFET, ion implantation of a high concentration layer is performed using the temporary gate as a mask, and after heat treatment, the gate metal is deposited on the temporary gate region. There is no need to limit it to.

[Example] Hereinafter, a preferred example of the method for manufacturing an FET according to the present invention will be described with reference to the drawings.

FIG. 1 is a partial cross-sectional view illustrating the method of manufacturing the FET in this embodiment.

First, as shown in FIG. 1(a), SiN,
A temporary gate 12 is formed using 5iON, 5i02, etc. This temporary gate 12 can be created by a well-known method, for example, a lift-off method.

Next, as shown in FIG. 1(b), a first resist 14 is applied with a spin code to a thickness that completely covers the temporary gate 12.

Then, the first resist 14 is etched so that a predetermined amount of the upper part of the temporary gate 12 is exposed as shown in FIG. 1(C). As an etching method, for example, 02
Reactive ion etching using plasma (hereinafter referred to as 02R)
(referred to as IE) can be used. It is relatively easy to control the etching rate of this 02RIE,
Therefore, etching to expose a predetermined amount of the upper part of the temporary gate 12 can be performed more easily than with image lithography.

After etching the first resist 14 by RIE, as shown in FIG. 1(d), a thin metal film 16 such as Ni is formed on the surface of the first resist 14 by vacuum evaporation or sputtering. do.

Then, a second resist 18 is coated on this N1 metal film 16 using a spin code, and as shown in FIG. 1(e), a region of this second resist 18 located above the temporary gate 12 is The Ni metal film 16 is removed from the resist surface.
A reversely tapered groove 20 is formed whose width becomes wider toward.

Hereinafter, as a method for forming the full 20, an image reverse photolithography method using a special positive type resist will be described as an example.

First, a positive photoresist as the second resist 18 is spin-coated onto the Ni metal film 16 to a predetermined thickness, for example, about 1 to 5 μm, using a spinner. This positive photoresist is a resist to which a photosensitive agent is added which reduces the rate of dissolution in a developer under a certain amount of exposure and reverse baking conditions.

After applying this positive resist, pre-baking is performed,
Initial exposure is performed with weak light from a light source through a photomask. At this time, the region where the groove 20 is to be formed is not exposed to light.

Then, reverse baking is performed to stabilize the initially exposed portion of the positive photoresist.

Next, flood exposure is performed over the entire surface of the positive photoresist to increase the rate of dissolution of the unexposed portions of the resist in the alkaline developer during the initial exposure. As a result, the initially exposed portion becomes difficult to dissolve in an alkaline developer, while the positive resist in the unexposed portion of the initial exposure becomes easily soluble.

Grooves 20 having a depth reaching the Ni metal film 16 are then formed by development with an alkaline developer.

At this time, as mentioned above, the initially exposed portion has a lower dissolution rate in the developer than the unexposed portion, and the intensity of the light during exposure becomes weaker as it goes below the resist surface, so the grooves 20 formed are As shown in FIG. 1(e), the Ni metal film 16 is removed from the surface of the second resist 18.
It has an inverted tapered shape that gradually increases in width toward the surface.

In this way, after the reversely tapered groove 20 is formed, the first
As shown in Figure (f), the Ni metal film 16 within this groove 20 is removed using dilute hydrochloric acid or the like.

Furthermore, as shown in FIG. 1(g), only the temporary gate 12 is removed using buffered hydrofluoric acid or the like.

After removing the Ni metal film 16 and the temporary gate 12 in the trench 20 in this way, the metal gate 22 is deposited in the trench 20 using a vacuum evaporation method or the like, as shown in FIG. 1(h). . As gate metal, T i / P t / A
u etc. can be used.

Then, the first resist 14 and the second resist 18 are removed using acetone or the like.

Then, as shown in FIG. 1(1), only the gate 22 having a T-shaped cross section remains on the substrate 10, making it easy to manufacture a gate with a shortened gate length and reduced gate resistance. It becomes possible.

As described above, by using the process of this example, it is possible to easily manufacture a gate having a T-shaped cross section.
A self-line MESFET can also be easily manufactured using such a gate having a T-shaped cross section.

Figure 2 shows this self-line type M E S F E
It is a partial sectional view showing the process of manufacturing T.

First, as shown in FIG. 2(a), Si
Temporary gate 12 such as N, S i O2, S i ON, etc.
form.

Then, as shown in FIG. 2(b), a highly concentrated N+ layer bio-ion implantation resist 24 is coated with a spin code, exposed through a photomask, and developed to form grooves in a predetermined area near the temporary gate 12. and create a mask pattern.

Then, as shown in FIG. 2(b), Si ions are implanted into the semiconductor substrate 10 using the resist 24 as a mask pattern.

In FIG. 2(b), the N layer immediately below the temporary gate 12 is previously formed by ion implantation before forming the temporary gate 12 on the GaAs substrate.

After removing the resist 24, the entire surface is coated with SiN or 5iON as shown in FIG. 2(C).

An annealing protective film 26 such as S L 02 is formed, and heat treatment is performed to activate the N layer and the N layer.

Finally, only this annealing protective film 26 is removed by uni-etching or dry etching using plasma, and the source/drain etching is performed through the steps shown in FIGS. 1(b) to 1(i). It is possible to obtain a self-lined MESFET in which the region and the gate are configured in a self-aligned manner, the gate length is shortened, and the gate resistance is reduced.

[Effects of the Invention] As explained above, according to the method for manufacturing an FET according to the present invention, a gate having a T-shaped cross section or a pine mushroom shape can be easily manufactured, and a self-line type ME
SFET etc. can be easily manufactured.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an embodiment of the FET manufacturing method according to the present invention, and FIG. 2 is an explanatory diagram of a self-line type FET manufacturing method using the same embodiment. 10... Semiconductor substrate 12... Temporary gate 14... First resist 16... N1 metal film 18... Second resist 20... Groove 22... Gate

Claims (1)

[Scope of Claims] A step of forming a temporary gate in a region on a semiconductor substrate where a gate is to be formed; a step of applying a first resist to the surface of the semiconductor substrate to cover the temporary gate; a step of etching the first resist to expose a predetermined amount of the upper portion; a step of forming a thin film on the etched surface of the first resist; a step of applying a second resist on the formed thin film; forming a reverse tapered groove that becomes wider from the resist surface toward the thin film in a region of the second resist located above the temporary gate; and removing the thin film and the temporary gate within this groove. A method for manufacturing a field effect transistor, comprising the steps of: depositing a gate metal thinner than the second resist in the groove; and removing the first and second resists. Method.