JPH0452816A - Reference voltage circuit - Google Patents

Abstract

PURPOSE:To attain the set up of various reference voltages on the same substrate without increasing the number of production processes by setting up the reference voltage in accordance with the rate of the conductance coefficient betaof a depression type MOS transistor(TR) to the conductance efficient beta' of an enhancement type MOSTR in a circuit constituted of both MOSTRs. CONSTITUTION:When a reference voltage value is set up in accordance with the rate (beta/beta') of the conductance coefficient beta of a depression type MOSTR 21 to the conductance coefficient beta' of an enhancement type MOSTR 22 in the reference voltage circuit constituted of serially connecting at least one depression type MOSTR 21 and at least one enhancement type MOSTR 22 between two certain potential levels on a semiconductor substrate and setting up their node as the reference voltage point, the reference voltage value can be changed by changing the conductance coefficient in accordance with TR size and various reference voltage values can be set up on the same substrate without increasing the number of production processes.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to the configuration of a reference voltage circuit.

[Prior art 1] First: At least one depletion type MOS transistor and at least one enhancement type MOS transistor are connected in series between two potentials, and the connection point is set as a reference voltage point. Figure 2 shows how the reference voltage value is expressed in the reference voltage circuit.
This is a reference voltage circuit in which one enhanced P-channel MOS transistor 22 is arranged on the low potential side 25 (hereinafter referred to as vSS). The gate, source, and bulk of the depletion type transistor 21 are connected to VDD,
The drain is connected to the reference voltage point 23 and operates in a saturated state. The gate and source of the enhancement transistor 22 are connected to VSS25.

The bulk and drain are connected to the reference voltage point 23 and operate in a saturated state. The current flowing between VDD24 and VsS25 is Id, base 1! If the voltage value is Vreg, the threshold voltage of the depletion type transistor 21 is Vthl, the conductance coefficient is β, the threshold voltage of the enhancement type transistor 22 is Vth2, and the conductance coefficient is β', then the following relational expression is obtained. It works.

Id=-β (0-Vthl)"=-β'(Vreg-Vth2)", and Vreg is 4 of Vthl, Vth2, β, and β".
It is expressed by two variables.

Also, if β=β', then Vreg=Vthl+Vth2 ---■Formula Conventionally, group 1! The setting of the voltage Vreg is as follows: β=β', Vthl, V
It was common to use the sum of th2.

[Problem to be solved by the invention] However, in the conventional case, the threshold voltage is determined by the sum of the threshold voltages, so if a depletion type transistor is used in addition to the reference voltage circuit, the A threshold voltage had to be added, resulting in an increase in manufacturing steps. In particular, when multiple reference voltages are provided on the same semiconductor substrate, a manufacturing process is required to determine the threshold values for the number of reference voltages, which only leads to increased costs, increased manufacturing days, and increased variation. there were.

Therefore, in the present invention, the ratio (β/β') of the conductance coefficient β of the depletion type MOS transistor and the conductance coefficient β' of the enhancement type MO5I-transistor is
The purpose is to set a reference voltage value by changing the , and to supply various reference voltage values on the same substrate without increasing the number of manufacturing steps.

Means for Solving Problem C] The base *W pressure path of the present invention includes at least one depletion type MOS transistor and at least one enhancement type MOS transistor between two potentials on a semiconductor substrate. In a reference voltage circuit in which MOS transistors are connected in series and the connection point thereof is used as a reference voltage point, the reference voltage value is determined by the conductance coefficient β of the depletion type MOS transistor and the conductance coefficient β of the enhancement type MOS transistor. ′ is set by the ratio (β/β′).

[Function] Since the present invention has the above configuration, various reference voltages can be set on the same substrate without increasing the number of manufacturing steps.

[Examples] Hereinafter, the present invention will be described in detail based on Examples.

FIG. 1 is a mask pattern diagram of a reference voltage circuit showing an embodiment of the present invention.

In FIG. 1, a case using a P-semiconductor substrate will be explained.

1 is a high potential side power supply line VDD, 2 is a low potential side power supply line SS, 3.7 is an N- type impurity layer, 4.8 is a P medium impurity layer, and 5.9 is a gate electrode such as Po1y-81. be. In Figure 1, the portion 3.4.5 forms a depletion type MOS transistor, the source, bulk, and gate are connected to VDDI, and the drain is connected to the reference voltage point 6.
It is connected to the. The portions 7, 8, and 9 form an enhancement type MOS transistor, the train and gate of which are connected to VSS2, and the source and bulk of which are connected to reference voltage point 6. 10 is a contact for connecting each wiring and region.

FIG. 1 is the same circuit diagram as FIG. 2.

In FIG. 1, the overlapping portion of the P10 impurity region 4 and the gate electrode 5 becomes the channel portion of the depletion type transistor, and its length and width are Ll and Wl, and the effective charge mobility is μm. Similarly, assuming that the channel length and width of the enhancement type transistor section are L2 and W2, and the effective charge mobility is μ2, the conductance coefficients B and β' are as follows.

Here, tox is the thickness of the gate oxide film, εO is the permittivity of vacuum, and εOX is the dielectric constant of the gate oxide film.

Next, by substituting the above equations (1) and (2) into the above equation 0, it can be expressed as .

Therefore, on the right side of equation (2), by changing the ratio of Wl and W2, the value of Vreg can be changed in a square root manner. Specifically, when Wl/W2=100, the formula 0 becomes as follows.

(Assume μm4μ2.) Vreg=Vth2+l0−Vthl ..0 formula % Formula % ..0 formula, and the reference voltage Vreg can be varied from Vth2 to infinity.

In Equation 0, the case of L1=L2 was described, but W1=W
In the case of 2, Vreg=, and by changing the ratio of Ll and L2, the same result as when W is changed is obtained.

Even in the case of L1≠L2 and Wl≠W2, Wl・L2 and W2・
A similar result can be obtained by changing the ratio of Ll.

Although FIG. 1 describes a combination of a P-channel depletion type transistor and an enhancement type transistor, similar results can be obtained with an N-channel type combination.

FIG. 3 is a graph in which when L1=L2, Wl/W2 is plotted on the horizontal axis and the reference voltage value at that time is plotted on the vertical axis. As mentioned in the explanation of Fig. 1, when Wl/W2 is 0, Vreg cape Vth2, when β1#β2, Vreg=Vth
l+Vth2, and as Wl/W2 increases, Vr
The value of eg increases in a square root manner.

FIG. 4 shows two devices provided on the same substrate to which the present invention is applied.
FIG. 3 is a mask pattern diagram of two reference voltage circuits. The first reference voltage is composed of a depletion type transistor section 32 and an enhancement type transistor section 33, and its reference voltage point is 31. The second base voltage circuit is composed of a depletion type transistor section 35 and an enhancement type transistor section 36, and its reference voltage point is 34. Each reference voltage circuit is the same as in FIG. 2, 37 is a high potential side power supply vSS, 38 is a low potential side power supply VS
It is S. In FIG. 4, the channel widths of the enhancement type transistors are assumed to be Wl and W2, which are equal to the channel length LO of all transistors and the channel width WO of the depletion type transistor.

The threshold voltage of the depletion type transistor is Vth
2. Assuming that the threshold voltage of the enhancement type transistor is Vth2, the effective charge mobility of the depletion type transistor is μl, and the effective charge mobility of the enhancement type transistor is μ2, first, the first The reference voltage value is as follows.

Further, the second reference voltage circuit composed of 35.36 is as follows.

Since the reference voltage value can be changed by changing the reference voltage value, it is possible to supply various reference voltage values on the same substrate without increasing the number of manufacturing steps.

[Effects of the Invention] As described above, according to the present invention, it is possible to change the conductance coefficient of the transistor and change the value of the reference voltage depending on the transistor size. It becomes possible to supply various reference voltage values.

(2) The only difference between the [phase] formulas is the channel width of the transistor, and a wide range of reference voltage values can be set very easily using just the square root arithmetic.

In Figure 4, the reference voltage was set by changing only the channel width of the transistor, but the reference voltage value can be similarly set by simple calculations by setting by channel length or setting by channel length and width. .

As described above, according to the present invention, the transistor size

[Brief explanation of the drawing]

FIG. 1 is a mask pattern diagram of a reference voltage circuit to which the present invention is applied. FIG. 2 is a reference voltage circuit diagram. FIG. 3 is a graph diagram showing changes in the reference voltage value when the present invention is applied. FIG. 4 shows two devices provided on the same substrate to which the present invention is applied.
FIG. 3 is a mask pattern diagram of two reference voltage circuits. 22 ・ ・ 23 ・ ・ 24 ・ ・ 25 ・ 3 l, 32. 34 ・ 35 ・ 33. 36 ・ 37 ・ ・ ・ ・ ・High potential power line VDD ・Low potential power line vSS ・N- type impurity region ・P medium impurity region ・Poly-si gate ・Reference voltage point ・Contact ・P channel depletion type transistor ・P Channel enhancement type transistor, reference voltage point, high potential power supply VDD, low potential power supply ■SS, reference voltage point, depletion type transistor section, enhancement type transistor section, high potential side power supply VDD 38...Low potential side power supply 785 Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Kizobe Suzuki (and 1 other person) Figure 2 Figure 3 Wl/W2

Claims (1)

[Claims] 1) At least one depletion type MOS transistor and at least one enhancement type MOS transistor are connected in series between two potentials on a semiconductor substrate, and the connection point is set as a reference voltage point. In the reference voltage circuit, the reference voltage value is determined by the conductance coefficient β of the depletion type MOS transistor (gate oxide film tox, gate oxide film relative dielectric constant εox, vacuum dielectric constant εo, effective charge mobility μeff, When effective channel width Weff and effective channel length Leff,
β=(ε0*εox*μeff*Weff)/(tox
*Leff). ) and the conductance coefficient β' of the enhancement type MOS transistor (β/β').