JPH0613404A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] High-performance poly-Si TFT with low-temperature process
An element structure and a manufacturing process for manufacturing the same are provided. In an insulated gate semiconductor device, a polycrystalline semiconductor layer 102 including a channel region mainly composed of silicon and doped with impurities such as boron, a gate insulating film 10
3, a gate electrode 104 having a sidewall 105,
It has at least a gate electrode, a semiconductor thin film 106 doped with impurities selectively formed on the polycrystalline semiconductor layer, and a metal thin film 108 selectively formed on the thin film. [Effect] Self-aligned TF with offset structure
T can be formed at a low temperature, and the resistance of the gate electrode and the source / drain region can be reduced at the same time. As a result, a high performance CMOS type poly-Si TFT can be formed on an inexpensive glass substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device on an insulating amorphous material and its manufacturing method.

[0002]

2. Description of the Related Art Attempts for forming low-performance high-performance TFTs (thin film transistors) using polycrystalline silicon as an element material on low-melting-point glass substrates have become active. In particular, low melting glass such as Corning 7059 is used as the substrate,
Practical application of a low temperature process for producing a CMOS type poly-Si TFT having a high mobility and a high on / off ratio at a maximum process temperature of about 450 ° C. or less is desired.

As a conventional method for forming a high-performance poly-Si TFT, there is known a method of forming a poly-Si film by a solid phase growth method and forming a source / drain region by an ion implantation method.

[0004]

However, the conventional TFT structure and manufacturing method as described above have the following problems. (1) Since it is necessary to perform annealing at about 550 ° C. to 650 ° C. for several hours to several tens of hours, it is not possible to use an inexpensive substrate such as 7059 manufactured by Corning Inc. as the substrate. (2) The crystallinity such as the crystallization rate of polycrystalline silicon cannot be sufficiently improved only by performing solid phase growth annealing at about 550 ° C. to 650 ° C., and the field effect mobility of the TFT is 100 cm ^2. It is difficult to form a high-performance TFT near / V · s (Nch). (3) Since the source-drain region is formed by using the gate electrode as a mask by the self-alignment method, an off-leakage current is generated due to a current generated by an electron-hole pair at the drain end, and a sufficient on-off ratio can be obtained. There was a problem such as no. Therefore,
The present invention is a simpler and more practical TFT structure and a manufacturing method thereof. A polycrystalline silicon having high crystallinity is formed at a low temperature with good reproducibility, and a CMOS type poly-Si TFT having a high mobility and a large on / off ratio is formed at 450 ° C. Provided is an element structure which is formed at a low temperature of about a certain degree or less, and a manufacturing method thereof.

[0005]

A semiconductor device according to the present invention is as follows: 1) In a semiconductor device in which a channel region of an insulated gate type semiconductor device is formed of a polycrystalline semiconductor mainly containing silicon, the channel region is a part of the semiconductor device. A polycrystalline semiconductor layer containing silicon as a main component, a gate insulating film, a gate electrode having a sidewall, and a thin film forming a source / drain region formed on at least a part of the polycrystalline semiconductor layer containing silicon as a main component. And at least a thin film on the gate electrode formed of the same material as the thin film, wherein the thin film forming the source / drain regions and the thin film on the gate electrode formed of the same material as the thin film are doped with impurities. It is characterized by having a laminated structure of crystalline silicon and a metal thin film.

2) The metal thin film is made of at least one of Al, W and Cu.

3) The sheet resistance of the thin film forming the source / drain regions and the thin film on the gate electrode formed of the same material as the thin film is 1Ω / □ or less.

4) An impurity such as boron is contained in the polycrystalline semiconductor layer containing silicon as a main component and containing the channel region as a part thereof.

5) The semiconductor device substrate is a glass substrate having a strain point of 600 ° C. or lower.

6) The film thickness of the polycrystalline semiconductor layer containing silicon as a main part, which includes the channel region as a part thereof, is 50.
It is characterized by being Å to 250Å.

7) The crystallization rate of the polycrystalline semiconductor layer is 9
It is characterized by being 9.5% or more. 8) The thin film forming the source / drain regions and the thin film on the gate electrode formed of the same material as the thin film are made of polycrystalline silicon doped with impurities.

9) The resistivity of the polycrystalline silicon layer doped with the impurities is 5 × 10 ⁻⁴ Ω · cm or less.

10) In a method of manufacturing a semiconductor device in which a channel region of an insulated gate semiconductor device is formed of a polycrystalline semiconductor containing silicon as a main component, a silicon containing channel region is mainly contained and impurities such as boron are doped. A step of forming a crystalline semiconductor layer, a step of forming a gate insulating film, a step of forming a gate electrode and a sidewall of a side wall of the gate electrode, and a portion of at least a part of a polycrystalline semiconductor layer mainly containing silicon including the channel region. The method is characterized by at least including a step of selectively forming a thin film forming a source / drain region on the region and a step of selectively forming a metal thin film on the thin film forming the source / drain region.

11) In the step of forming the thin film forming the source / drain regions, the thin film is selectively formed under the condition that the thin film is not formed on at least the sidewall. 12) The semiconductor device It is characterized in that it is formed on a glass substrate having a strain point of 600 ° C. or lower.

13) For the polycrystalline semiconductor layer containing silicon as a main component including the channel region, at least a gas containing at least one element of fluorine and chlorine is used, and a doping gas such as diborane is further added. The method is characterized by having at least a step of exciting and decomposing in a plasma state and forming a film.

14) The substrate temperature in the above step is 300 ° C.-4.
It is characterized by being 50 ° C.

15) A polycrystalline semiconductor layer composed mainly of silicon doped with impurities, which constitutes source / drain regions,
At least a gas containing at least one element of fluorine and chlorine is used, and the gas is excited and decomposed into a plasma state to form a film.

16) The substrate temperature in the above step is 300 ° C.-4.
It is characterized by being 50 ° C.

17) In the step of selectively forming the metal thin film on the thin film forming the source / drain region and on the gate electrode, the metal thin film is selectively formed under the condition that at least the metal thin film is not formed on the sidewall. Is characterized by.

18) The process temperature of the step of selectively forming the metal thin film is 450 ° C. or lower.

[0021]

1 is an example of a sectional view of a semiconductor device according to an embodiment of the present invention.

In FIG. 1, 101 is an insulating amorphous substrate such as glass or quartz, or an insulating amorphous material such as an insulating amorphous material layer such as SiO ₂ ; 102 is a polycrystalline silicon layer;
Reference numeral 03 is a gate insulating film, 104 is a gate electrode, 105 is a sidewall, 106 is a semiconductor thin film that constitutes a source / drain region formed of polycrystalline silicon doped with p-type or n-type impurities, and 107 is formed on the gate electrode. Semiconductor thin film of the same material as the source / drain regions, 108 and 109 are metal thin films formed on the semiconductor thin films 106 and 107, 110 is an interlayer insulating film,
111 is a contact hole and 112 is a wiring. Pol of the present invention
The y-Si TFT is characterized by having a self-aligned structure using sidewalls, and is characterized by having a structure in which source / drain regions are selectively formed. In the present invention, the sidewall can prevent a short circuit between the source / drain region and the gate electrode, and at the same time, the sidewall can form an offset structure. The generation of the off-leakage current is suppressed, and a sufficient on-off ratio can be obtained. Further, by selectively growing the metal thin films 108 and 109, the resistance of the gate electrode and the source / drain region can be reduced, and a large-area and high-definition liquid crystal display panel can be easily formed.

FIG. 2 shows a CMOS according to an embodiment of the present invention.
It is an example of a manufacturing process diagram of a type poly-Si TFT.

In FIG. 2, (a) shows polycrystalline silicon on an insulating amorphous material 201 such as an insulating amorphous substrate such as glass or quartz, or an insulating amorphous material layer such as SiO _2. This is a step of forming the layers 202 and 202 ′ and forming the gate insulating film 203. In the present invention, since the maximum temperature of the process can be set to about 450 ° C. or lower, a low melting point glass such as Corning 7059 can be used. As a method of forming a polycrystalline silicon layer, a method of forming a polycrystalline silicon film with a film thickness of 50 Å to 1500 Å by a plasma CVD method (PCVD method) at a low substrate temperature of about 300 to 450 ° C is effective. In the PCVD method, usually monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used as a reaction gas.
When such a reaction gas is used, amorphous silicon or at most microcrystalline silicon is deposited at a substrate temperature of about 300 ° C. to 450 ° C., and high quality polycrystalline silicon is deposited. It is difficult. However, as a reaction gas, in addition to the above SiH ₄ , Si ₂ H _6, etc., by mixing an appropriate amount of a reaction gas containing elements such as fluorine (F) and chlorine (Cl), a high quality polycrystalline silicon film can be obtained. Can be formed at low temperature. An example of film forming conditions is shown below. As a reaction gas,
Monosilane (SiH ₄ ), Dichlorosilane (SiH ₂ Cl
₂ ) and H ₂ , and the mixing ratio is, for example, SiH ₄ : SiH ₂ C
l ₂ = 1: 20 to 1: 200, SiH ₄ : H ₂ = 1:
The substrate temperature is set to 100 to 1: 1000, and the substrate temperature is set to 300.
C. to 450.degree. C. is maintained, rf power is applied, the reaction gas is decomposed, and polycrystalline silicon is deposited. Regarding the film thickness, it is known that when the polycrystalline silicon layer is thinned, the off current is decreased and Vth (threshold voltage) is decreased. Therefore, the film thickness of the polycrystalline silicon layer is preferably 500 Å or less, and particularly preferably 50 Å to 250 Å. Therefore, it is particularly important to form high-quality polycrystalline silicon with such a thin film. When the substrate temperature is 300 ° C. or lower, the thin film as described above has a low crystallization rate and <2.
20> No orientation is observed, but the substrate temperature is 400 ° C to 4
Even if it is a thin film of 50Å to 250Å at about 50 ℃,
High quality polycrystalline silicon oriented in <220> can be formed with a crystallization rate of 98% or more. As described above, according to the present invention, since a high-quality polycrystalline silicon film can be formed at a low substrate temperature of about 450 ° C. or less, it can be formed on an inexpensive glass substrate such as Corning 7059 (strain point 593 ° C.). A high-performance poly-Si TFT can be formed. In this embodiment, the case where SiH ₂ Cl ₂ is used as the reaction gas is shown, but the present invention is not limited to this. For example, SiCl ₄ , SiH ₂ Cl ₂ , SiHCl ₃ , C
l ₂ , SiF ₄ , SiHF ₃ , SiH ₂ F ₂ , SiH ₃ F, S
i ₂ F ₆ , F ₂ , HCl, and other reactive gases having an etching property containing at least one element of F (fluorine) and Cl (chlorine), and SiH ₄ , Si ₂ H ₆ , Si ₃ H _8, etc. High-quality polycrystalline silicon can be formed at a low temperature by mixing an appropriate amount of reaction gas and sufficiently diluting it with hydrogen gas or the like.

Further, means for controlling the Vth (threshold voltage) by doping impurities into the channel region is extremely effective. Polycrystalline silicon TF formed by solid phase growth method
At T, the N-channel transistor tends to shift Vth in the depletion direction and the P-channel transistor tends to shift in the enhancement direction. Further, when the above TFT is hydrogenated, the tendency becomes more remarkable.
Therefore, doping the channel region with impurities of about 10 ¹⁵ to 10 ¹⁹ / cm ³ can suppress the shift of Vth. Therefore, channel doping can be performed without using ion implantation by mixing a doping gas such as B ₂ H ₆ in addition to a gas containing chlorine or fluorine such as SiH ₄ and SiH ₂ Cl ₂ . As an example of film forming conditions, SiH ₄ + SiH ₂ Cl ₂ : B ₂ H ₆ = 1:
Vth can be controlled by mixing about 0.1 ppm to 0.1%. Especially by optimizing the doping amount,
Vth can be controlled so that the off currents of both the P-channel transistor and the N-channel transistor are minimized. Therefore, even when forming a CMOS type TFT element, Vth can be controlled for both Pch and Nch only by a film forming process of polycrystalline silicon forming a channel portion without selectively channel doping Pch and Nch. Is. Next, an example of a method for forming the gate insulating film will be described. As a method for forming the gate insulating film, a thermal oxidation method is used.
Method of forming at a high temperature of about 0 ° C. to 1200 ° C. (high temperature process), CVD method, plasma CVD method, ECR-PC
450 ° C. to 650 by VD method, photo CVD method, sputtering method, etc.
There is a method (low temperature process) of forming at a low temperature of about ℃ or less. For example, when low melting glass such as Corning 7059 is used as the substrate, the maximum process temperature is 45
Must be below 0 ° C, sputter method, ECR
-The PCVD method is particularly suitable.

(B) shows that after the gate electrodes 204 and 204 'are formed,
In this step, the insulating film 205 is formed on the entire surface, only the Nch region is covered with a resist, the insulating film in the Pch region is etched by anisotropic etching, and the sidewall 206 is formed on the Pch gate electrode. First, the gate electrodes 204, 20
4'is formed of impurity-doped polycrystalline silicon and patterned into a predetermined shape. As a method of forming the polycrystalline silicon layer, a method of forming a polycrystalline silicon film with a film thickness of about 500 Å to 4000 Å by a plasma CVD method (PCVD method) at a low substrate temperature of about 300 to 450 ° C is effective. Below, an example of film-forming conditions is shown. As a reaction gas,
Monosilane (SiH ₄ ), Dichlorosilane (SiH ₂ Cl
₂ ) and H ₂ , and the mixing ratio is, for example, SiH ₄ : SiH ₂ C
l ₂ = 1: 20 to 1: 200, SiH ₄ : H ₂ = 1:
The doping gas is set to about 100 to 1: 1000, and diborane (B ₂ H ₆ ) or phosphine (P) is used as a doping gas.
H ₃ ), arsine (AsH ₃ ) and the like, for example, SiH
₄ : PH ₃ = 1: 0.002 to 1: 0.04 are mixed at a mixing ratio of about. The substrate temperature is maintained at about 300 to 450 ° C., rf power is applied to decompose the reaction gas, and low-resistance polycrystalline silicon doped with impurities is formed. The sheet resistance of the polycrystalline silicon thus formed is 2000Å
The film thickness is 30 to 50 Ω / □, and low resistance polycrystalline silicon can be formed at a low temperature. In addition, by forming a metal thin film or a silicide film on the polycrystalline silicon that forms the gate electrode, it is possible to obtain a good compatibility with the polycrystalline silicon layer doped with impurities that is selectively formed on the gate electrode in a later step. A method of ensuring ohmic contact is also effective.
The method for forming polycrystalline silicon is not limited to this. Subsequently, the sidewall 206 is formed. Atmospheric pressure CVD method, sputtering method, plasma CVD method, ECR-
SiO2,
Insulating film 205 made of SiNX, SiOXNY, etc.
About 0Å is formed, only the Nch region is covered with a resist, and the insulating film is etched by anisotropic etching to form the sidewall 206.

Step (c) is a step of selectively forming an impurity-doped polycrystalline silicon film 207 on the Pch polycrystalline silicon 202 and the gate electrode 204. As a method of forming the polycrystalline silicon layer, a plasma CVD method (PCVD
Method), the method of selectively growing polycrystalline silicon at a film thickness of about 500Å to 3500Å at a low substrate temperature of about 300 ° C to 450 ° C is effective. That is, polycrystalline silicon doped with impurities is selectively grown only on the polycrystalline silicon 202 and 204, and in the other regions (insulating amorphous material 201, sidewall 205, insulating film 204 on Nch). A self-aligned TFT having an offset gate structure can be formed at a low temperature by using a method in which polycrystalline silicon is not formed. In particular, in the present invention, by providing a sidewall and performing selective growth, it is possible to completely prevent a short circuit between the gate electrode and the source / drain region. Below, an example of film-forming conditions is shown. As reaction gas, monosilane (Si
H ₄ ), dichlorosilane (SiH ₂ Cl ₂ ), H ₂
The mixing ratio for _{example, SiH 4: SiH 2 Cl 2} = 1: 20~
About 1: 200, SiH ₄ : H ₂ = 1: 100 to 1:10
00 and using diborane (B ₂ H ₆ ) or the like as a doping gas. For example, SiH ₄ : B ₂ H ₆ = 1:
Mix at a mixing ratio of about 0.002 to 1: 0.04. The substrate temperature is maintained at about 300 ° C. to 450 ° C., rf power is applied to decompose the reaction gas, and impurity-doped low resistance polycrystalline silicon is selectively grown. SiH ₄ and SiH ₂ C
By optimizing the mixing ratio of l _{2 and} the like, only polycrystalline silicon (gate electrode 204, polycrystalline silicon layer 202) is grown, and the other regions (insulating amorphous material 201, sidewall 205, Nch) are grown. Selective growth that does not grow on the upper insulating film 204) is possible. The sheet resistance of the polycrystalline silicon thus formed is 30 to 50 Ω / at a film thickness of 2000Å.
□, and low resistance polycrystalline silicon can be selectively formed at a low temperature. The method for forming polycrystalline silicon is not limited to this. Subsequently, in order to further reduce the resistance of the source / drain regions and the gate electrode, W (tungsten), Al, Cu or the like is formed on the impurity-doped polycrystalline silicon 207 by a selective CVD method or the like. In this embodiment, as an example, a case where W is selectively grown by the CVD method is shown. As an example of film forming conditions, a cold wall type CVD apparatus is used, and the substrate is heated at 350 ° C. to 450 ° C.
The temperature is kept at about ℃, and tungsten hexafluoride (WF ₆ ) and monosilane (SiH ₄ ) are used as reaction gases. SiH ₄ / WF ₆ =
The W film 208 is selectively grown only on the polycrystalline silicon by mixing it to about 0.3 to 1.0. In this case, it is easy to set the sheet resistance of the gate electrode and the source / drain regions to about 1Ω / □ or less. For example, a W film of about 2000 Å can be reduced to about 0.6Ω / □, which is an extremely effective means for realizing a large-screen liquid crystal display panel.

In (d), after the insulating film 209 is formed on the entire surface, P
Only the ch region is covered with a resist, and the Nch is formed by a combination of isotropic etching and anisotropic etching.
This is a step of etching the insulating film in the region to form the sidewall 210 on the Nch gate electrode. First, insulating film 2
09, atmospheric pressure CVD method, sputtering method, plasma CVD method,
At a low temperature of about 450 ° C. or lower by the ECR-PCVD method or the like,
About 00Å to 2000Å is formed, only the Pch region is covered with a resist, about the film thickness of the insulating film 209 is removed by isotropic etching, and then the remaining insulating film is anisotropically etched to form a side film. The wall 210 is formed.

(E) is a step of selectively forming an impurity-doped polycrystalline silicon film 211 on the Nch polycrystalline silicon 202 'and the gate electrode 204'. As a method of forming the polycrystalline silicon layer, a plasma CVD method (PCVD
Method), the method of selectively growing polycrystalline silicon at a film thickness of about 500Å to 3500Å at a low substrate temperature of about 300 ° C to 450 ° C is effective. That is, polycrystalline silicon doped with impurities is selectively grown only on the polycrystalline silicon 202 ′ and 204 ′, and the other regions (the insulating amorphous material 201, the sidewalls 210, and the insulating film 209 on the Pch are formed). By using a method in which the polycrystalline silicon is not formed in (1), a self-aligned TFT having an offset gate structure can be formed at a low temperature. Particularly in the present invention, a sidewall is provided,
The selective growth can completely prevent a short circuit between the gate electrode and the source / drain regions. Below, an example of film-forming conditions is shown. As reaction gas, monosilane (SiH
₄ ), dichlorosilane (SiH ₂ Cl ₂ ), and H ₂ , and the mixing ratio is, for example, SiH ₄ : SiH ₂ Cl ₂ = 1: 20 to
About 1: 200, SiH ₄ : H ₂ = 1: 100 to 1:10
00, and phosphine (PH ₃ ) or arsine (AsH ₃ ) is used as a doping gas.
iH ₄ : PH ₃ = 1: 0.002 to 1: 0.04. The substrate temperature is maintained at about 300 ° C. to 450 ° C., rf power is applied to decompose the reaction gas, and impurity-doped low resistance polycrystalline silicon is selectively grown.
By optimizing the mixing ratio of SiH ₄ and SiH ₂ Cl ₂ , etc., only the polycrystalline silicon (gate electrode 204 ′, polycrystalline silicon layer 202 ′) is grown, and the other regions (insulating amorphous material). 201, sidewall 210, insulating film 209 on Pch
It is possible to select growth that does not grow in the above). The sheet resistance of polycrystalline silicon formed in this way is 2000Å
The film thickness is 30 to 50Ω / □, and low resistance polycrystalline silicon can be selectively formed at low temperature. The method for forming polycrystalline silicon is not limited to this. Then, in order to further reduce the resistance of the source / drain regions and the gate electrode, W (tungsten), Al, Cu or the like is formed on the impurity-doped polycrystalline silicon 211 by a selective CVD method or the like. In this embodiment, as an example, a case where W is selectively grown by the CVD method is shown. As an example of the deposition conditions, using a cold wall type CVD device, the substrate is held in a degree 350 ° C. to 450 ° C., as a reaction gas, tungsten hexafluoride (WF _6), SiH ₄ monosilane (SiH ₄₎ / WF ₆ = 0.3 to 1.0, and the W film 212 is selectively grown only on the polycrystalline silicon. In this case, it is easy to set the sheet resistance of the gate electrode and the source / drain regions to about 1Ω / □ or less. For example, when the W film is about 2000Å, it can be reduced to about 0.6Ω / □.

In (f), the interlayer insulating film 213 is formed by a CVD method, a sputtering method, a plasma CVD method or the like, and subsequently, hydrogen gas or ammonia gas or the like is used for the purpose of reducing defects existing in crystal grain boundaries. This is a step of forming a wiring 215 by exposing a contact hole 214 in the interlayer insulating film 213 by exposing it to a plasma atmosphere of a gas containing at least.

The field effect mobility of the P-channel TFT formed by the method of manufacturing a semiconductor device according to the present invention is 20 to 20.
40 cm ² / V · sec, and off current is 0.05
~ 0.1 pA (drain voltage: 5 V, gate length: 4 μ
m, gate width: about 10 μm) and an on / off ratio of about 9 digits was achieved. The field effect mobility of the N-channel TFT is about 60 to 100 cm ² / V · sec,
Off current is 0.01 to 0.03 pA (drain voltage: 5
V, gate length: 5 μm, gate width: 10 μm) were obtained, and an on / off ratio of about 10 digits was achieved. Further, according to the present invention, since an offset gate structure can be realized, it is effective not only in reducing the above-mentioned off-current but also in improving the drain breakdown voltage, and turning on / off the current even at a drain voltage of about 20V to 30V. Can be controlled. As a result, according to the present invention, it is possible to easily realize a high breakdown voltage switching element. As described above, according to the present invention, a high performance CMOS type poly-Si TFT can be formed at a low temperature.

The present invention is based on the TF shown in the embodiment of FIG.
In addition to T, it can be applied to general insulated gate semiconductor devices.

[0033]

As described above, according to the present invention, a polycrystalline silicon film having a high crystallization rate can be formed at a low temperature by a simpler manufacturing process. Further, according to the TFT structure and the manufacturing method thereof of the present invention, since a self-aligned TFT having an offset structure can be formed at a low temperature, a high-performance CMOS TFT having a high mobility and a high on / off ratio can be manufactured by Corning 7059. Can be formed on an inexpensive glass substrate. Further, by selectively forming W, Al, etc.,
The sheet resistance of the gate electrode can be reduced to about 0.6Ω / □ or less. As a result, a large, high-resolution liquid crystal display panel, a large, high-speed, high-resolution contact image sensor, a three-dimensional I
It became possible to manufacture C etc. at low cost.

The present invention also includes the T shown in the embodiment of FIG.
In addition to FT, it can be applied to all insulated gate type semiconductor devices, and semiconductor devices such as bipolar transistors, electrostatic induction type transistors, photoelectric conversion devices such as solar cells and photosensors are formed using polycrystalline semiconductors as element materials. This is a very effective manufacturing method.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a semiconductor device according to an embodiment of the invention.

[Explanation of symbols]

 101,201 Insulating amorphous material 102,202,202 'Polycrystalline silicon layer 103,203 Gate insulating film 104,204,204' Gate electrode 105,206,210 Sidewall 106,107 Impurity-doped semiconductor thin film 108,109 Metal thin film 207,211 Impurity-doped polycrystalline silicon film 208,212 Tungsten film 110,213 Interlayer insulating film 111,214 Contact hole 112,215 Wiring

Claims (18)

[Claims] 1. A semiconductor device in which a channel region of an insulated gate type semiconductor device is formed of a polycrystalline semiconductor containing silicon as a main component, and a polycrystalline semiconductor layer containing silicon as a main component including a channel region and gate insulation A film, a gate electrode having a sidewall, a thin film forming a source / drain region formed on at least a partial region of the polycrystalline semiconductor layer mainly containing silicon, and a gate electrode formed of the same material as the thin film The thin film forming the source / drain regions and the thin film on the gate electrode formed of the same material as the thin film have a laminated structure of polycrystalline silicon doped with impurities and a metal thin film. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the metal thin film is made of at least one of Al, W and Cu. 3. The thin film forming the source / drain regions and the thin film on the gate electrode formed of the same material as the thin film have a sheet resistance of 1 Ω / □ or less.
Alternatively, the semiconductor device according to claim 2. 4. The semiconductor device according to claim 1, wherein the polycrystalline semiconductor layer containing silicon as a main part and containing the channel region contains impurities such as boron. 5. The semiconductor device according to claim 1, wherein the substrate of the semiconductor device is a glass substrate having a strain point of 600 ° C. or lower. 6. The film thickness of the polycrystalline semiconductor layer mainly composed of silicon including the channel region as a part thereof is 50 Å
The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device has a thickness of about 250Å. 7. The crystallization rate of the polycrystalline semiconductor layer is 99.
It is 5% or more, The semiconductor device of Claim 1 thru | or 6 characterized by the above-mentioned. 8. The thin film forming the source / drain regions and the thin film on the gate electrode formed of the same material as the thin film,
8. The semiconductor device according to claim 1, which is made of polycrystalline silicon doped with impurities. 9. The semiconductor device according to claim 8, wherein the polycrystalline silicon layer doped with the impurities has a resistivity of 5 × 10 ⁻⁴ Ω · cm or less. 10. A method of manufacturing a semiconductor device, wherein a channel region of an insulated gate semiconductor device is formed of a polycrystalline semiconductor containing silicon as a main component, wherein a silicon containing channel region is mainly contained and impurities such as boron are doped. A step of forming a crystalline semiconductor layer, a step of forming a gate insulating film, a step of forming a gate electrode and a sidewall of a side wall of the gate electrode, and a portion of at least a part of a polycrystalline semiconductor layer mainly containing silicon including the channel region. A method of manufacturing a semiconductor device, comprising at least a step of selectively forming a thin film forming a source / drain region on a region and a step of selectively forming a metal thin film on the thin film forming a source / drain region. 11. The semiconductor according to claim 10, wherein in the step of forming the thin film forming the source / drain regions, the thin film is selectively formed under the condition that the thin film is not formed at least on the sidewall. Device manufacturing method. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the semiconductor device is formed on a glass substrate having a strain point of 600 ° C. or lower. 13. A polycrystalline semiconductor layer mainly composed of silicon including a channel region is formed by using at least a gas containing at least one element of fluorine and chlorine, and further adding a doping gas such as diborane. 13. The method of manufacturing a semiconductor device according to claim 11, further comprising at least a step of exciting and decomposing into a plasma state and forming a film. 14. The substrate temperature in the step is 300 ° C. to 450 ° C.
The temperature is ° C.
A method for manufacturing a semiconductor device as described above. 15. A polycrystalline semiconductor layer mainly composed of silicon doped with impurities, which constitutes a source / drain region, uses at least a gas containing at least one element of fluorine and chlorine, and excites the gas into a plasma state. The method further comprises at least a step of decomposing and forming a film.
15. The method of manufacturing a semiconductor device according to claim 1. 16. The process temperature of the step is 300 ° C. to 4
16. The method for manufacturing a semiconductor device according to claim 15, wherein the temperature is 50 ° C. 17. In a step of selectively forming a metal thin film on a thin film forming a source / drain region and on a gate electrode, the metal thin film is selectively formed under the condition that at least the metal thin film is not formed on the sidewall. The method for manufacturing a semiconductor device according to claim 11, wherein 18. The method of manufacturing a semiconductor device according to claim 17, wherein the process temperature of the step of selectively forming the metal thin film is 450 ° C. or lower.