JPH1174776A - Programmable impedance circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control impedance fluctuation in an excessive state of an output buffer by setting the impedance value of an output buffer in accordance with on-resistance of a switching element and the resistance value of a resistance element. SOLUTION: When selection signals S1 and S2 are (0 and 1) and an up signal that is outputted from a sense amplifier is on a high level, MOS transistors Q1 and Q5 are turned on, and the impedance value of an output buffer 4 is set by on-resistance of the transistors Q1 and Q5 and the resistance value of resistance elements R1 and R5. Also, when a down signal that is outputted from the sense amplifier is on a high level, MOS transistors Q2 and Q6 are turned on, and the impedance value of the buffer 4 is set by on-resistance of the transistors Q2 and Q6 and the resistance value of resistance elements R2 and R6. In such cases, the impedance value of the buffer 4 is adjusted in accordance with the impedance value of an exterior dummy resistance element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable impedance circuit which can select any one of a plurality of impedance values according to the logic of a selection signal.

[0002]

2. Description of the Related Art With the recent increase in the speed of semiconductor integrated circuits,
There has been a need to speed up signal transmission between semiconductor integrated circuits. To perform signal transmission at high speed, impedance matching for matching the impedance values of the output buffer and the transmission line is one of the important conditions.

If the impedance value of the transmission line is Z0, the impedance value of the output buffer is Zs, and no termination processing (termination) is performed, the reflectance ρ = (Zs-Z0) / (Zs + Z0) at the end of the transmission line. Reflection occurs.
In order to increase the rise time and fall time of the transmission line, it is necessary to reduce Zs. However, as is apparent from the above-described reflectance equation, when Zs is extremely reduced, data of the opposite phase is reflected. As a result, ringing occurs in which the potential of the transmission line oscillates.

FIG. 11A shows a normal waveform without ringing, and FIG. 11B shows a waveform with ringing. If strong ringing occurs, normal data transmission is no longer possible. In order to transmit a signal at the highest speed without causing ringing, it is necessary to match the impedance value of the transmission line with the impedance value of the output buffer.

Since the impedance value of the transmission line differs depending on the material of the printed circuit board on which the semiconductor integrated circuit is mounted, it is difficult to always match the impedance value of the output buffer of the semiconductor integrated circuit with the impedance value of the transmission line. It is. Even if the two impedance values match, if the output buffer is constituted only by the MOS transistors, the impedance value of the output buffer of the semiconductor integrated circuit depends on the operating conditions of the semiconductor integrated circuit (for example, the outside temperature and the power supply voltage). Changes, and impedance matching cannot be performed.

In order to solve such a problem, there has been proposed a programmable impedance circuit capable of programmably changing the impedance value of an output buffer. This kind of programmable impedance circuit is
By periodically monitoring the impedance value of the external dummy resistor and changing the type and number of MOS transistors to be turned on, the impedance value of the output buffer can be changed to an impedance value R (for example, R = r × 1/5). As a result, the impedance value of the output buffer can be variably controlled by external setting.

FIG. 12 is a circuit diagram of a conventional programmable impedance circuit. The circuit in FIG. 11 includes MOS transistors Q1 to Q6, NAND gates G1 to G4, and inverters INV1 to INV4. In the circuit of FIG. 12, complementary input data up and down and a selection signal S
1, S2, and one of the complementary input data, up, with the impedance value selected by the selection signals S1, S2.
Is output.

The circuit shown in FIG. 11 has three buffer units B1 to B1.
B3, two of which are buffer units B
2-bit selection signals S1 and S2 are input to 2 and B3, and the buffer unit B1 is always activated (ON). By switching the logic of the selection signals S1 and S2, one of the four types of output impedance values is selected. Further, the buffer unit B1 to which the selection signals S1 and S2 are not input.
Sets the maximum value of the output impedance value.

[0009]

The conventional programmable impedance circuit shown in FIG.
Although the output impedance value can be variably controlled by the logic of S1 and S2, the following problems depending on the characteristics of the output buffer occur.

That is, since the output impedance value is adjusted to a value corresponding to the resistance value of the external dummy resistor under a certain bias condition, a desired impedance value is not necessarily obtained in a transient state. For example, FIG.
FIG. 12 is a diagram showing the output voltage-output current characteristics when the signal voltage changes from a high level to a low level when the circuit in FIG. 11 is configured using NMOS transistors. The solid line in the figure is an actual measurement curve of output voltage-output current, and the dotted line is an ideal straight line assuming that the impedance value does not change. As is clear from FIG. 13, the deviation from the ideal straight line increases as the output voltage increases.

Therefore, in a transient state in which the output voltage changes, the impedance value also changes greatly, and ringing occurs due to reflection.

SUMMARY OF THE INVENTION The present invention has been made in view of such a point, and an object of the present invention is to provide a programmable impedance circuit whose impedance value does not fluctuate even in a transient state of an output buffer. .

[0013]

In order to solve the above-mentioned problem, the invention according to claim 1 according to the present invention, according to the logic of a selection signal,
In a programmable impedance circuit having an output buffer capable of setting any one of a plurality of different impedance values, the output buffer has a switching element and a resistance element, and is in a transient state in which an output voltage of the output buffer changes. In the above, the impedance value of the output buffer is set based on the on-resistance of the switching element and the resistance value of the resistance element so that the impedance value of the output buffer does not change.

According to a second aspect of the present invention, there is provided a programmable impedance circuit including an output buffer capable of setting any one of a plurality of mutually different impedance values in accordance with the logic of a selection signal. A plurality of buffer units different from each other, at least one of the buffer units includes a switching element and a resistance element connected to one end of the switching element, and includes the switching element and the resistance element. The impedance value of the buffer unit is set according to the on-resistance of the switching element and the resistance value of the resistance element, and according to the logic of the selection signal, some of the buffer units are selected and the selected one is selected. Setting the impedance value of the output buffer based on the impedance value of the buffer unit; .

According to a third aspect of the present invention, in the programmable impedance circuit according to the second aspect, the switching element is a MOS transistor, and the resistance element is a diffusion resistance formed by diffusing impurity ions into a semiconductor substrate, or The resistance is made of polycrystalline silicon.

According to a fourth aspect of the present invention, in the programmable impedance circuit according to the second or third aspect, at least one of the buffer units is connected to a MOS transistor and a drain terminal or a source terminal of the MOS transistor. A resistance element, and a corresponding impedance value of the buffer unit is set by a total value of an on-resistance of the MOS transistor and a resistance value of the resistance element.

According to a fifth aspect of the present invention, in the programmable impedance circuit according to the fourth aspect, each of the buffer units includes a MOS transistor and a resistance element connected to a drain terminal or a source terminal of the MOS transistor. The ON resistance of the MOS transistor and the resistance value of the resistance element are different for each of the buffer units, and the ratio of the ON resistance of the MOS transistor to the resistance value of the resistance element. And are approximately equal.

According to a sixth aspect of the present invention, in the programmable impedance circuit according to the fourth aspect, at least one of the buffer units includes the MOS transistor in which the resistance element is not connected to any of a drain terminal and a source terminal. And the impedance value of the buffer section is set by the ON resistance of the MOS transistor.

According to a seventh aspect of the present invention, in the programmable impedance circuit according to any one of the second to sixth aspects, complementary input data whose logics are opposite to each other are input to each of the plurality of buffer units, and Are connected to each other, and at least one of the plurality of buffer units has an NMOS corresponding to one of the complementary input data.
A transistor, and a resistance element connected to a drain terminal or a source terminal of the NMOS transistor; and, corresponding to the other of the complementary input data, a PMOS transistor and a drain terminal or a source terminal of the PMOS transistor. One of an NMOS transistor and a PMOS transistor is turned on in accordance with the logic of the complementary input data and the selection signal. A corresponding impedance value of the buffer unit is set according to a resistance value of the connected resistance element. According to an eighth aspect of the present invention, in the programmable impedance circuit according to the seventh aspect, the complementary input data is an output of a sense amplifier for amplifying cell data read from a memory cell.

According to a ninth aspect of the present invention, in the programmable impedance circuit according to the second to sixth aspects, single input data is input to each of the plurality of buffer units, and each output of the plurality of buffer units is Connected to each other, at least one of the plurality of buffer units is a PMOS transistor, a resistance element connected to a drain terminal or a source terminal of the PMOS transistor, an NMOS transistor, and a drain terminal or a source terminal of the NMOS transistor. A resistance element connected to the logic circuit, and one of a PMOS transistor and an NMOS transistor is turned on in accordance with the logic of the single input data and the logic of the selection signal, and the on-resistance of the turned-on MOS transistor; According to the resistance value of the resistance element connected to this MOS transistor, To set the impedance value.

According to a tenth aspect of the present invention, in the programmable impedance circuit according to the second to ninth aspects, a plurality of dummy buffer sections provided corresponding to each of the plurality of buffer sections and having mutually different impedance values are provided. A selection signal output circuit for detecting, from among the dummy buffer units, a dummy buffer unit having an impedance value substantially equal to an externally attached dummy resistor, and outputting the selection signal having a logic corresponding to the detected dummy buffer unit; And.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a programmable impedance circuit to which the present invention is applied will be specifically described with reference to the drawings. The programmable
The impedance circuit is formed on a semiconductor substrate.

FIG. 1 is a block diagram of an embodiment of a programmable impedance circuit according to the present invention. FIG.
Is a dummy resistance element Rd and a reference current detection circuit 1
, An A / D converter 2, a clock generation circuit 3, and an output buffer 4.

The resistance value of the dummy resistance element Rd is set in advance to a predetermined value (for example, 250 to 500 ohm) according to the characteristic impedance value of the printed circuit board. The reference current detection circuit 1 detects a current flowing through the dummy resistance element Rd, and transfers the current to the A / D converter 2. A / D
The converter 2 controls switching of the impedance value of the output buffer 4 as shown in FIG. The configuration and operation of the A / D converter 2 will be described later.

The clock generation circuit 3 generates an operation timing signal CLK1 for the A / D converter 2 based on a reference clock CLK input from the outside, and generates the A / D converter 2
To supply. The output buffer 4 includes selection signals S1 and S2 from the A / D converter 2, as shown in FIG.
The output impedance of the output buffer 4 is connected to the I / O data terminal. The configuration and operation of the output buffer 4 will be described later.

The sense amplifier 5 includes an address decoder 6
The cell data read from the memory cell array 7 in accordance with the decoding result of the above is input via the column selector 8. The sense amplifier 5 amplifies and complements the input cell data and outputs complementary data up and down signals output from the sense amplifier 5 to the output buffer 4.

FIG. 2 is a diagram showing the internal configuration of the A / D converter 2. Inside the A / D converter 2, a plurality of dummy buffer sections DB1 to DB3, a current comparator 9, and a counter & clock 10 are provided.

The dummy buffer section DB1 has a transistor Q11 and a resistance element R11 connected in series. The drain terminal of the transistor Q11 is connected to the power supply terminal Vcc, the source terminal thereof is connected to one end of the resistance element R11, The other end of the element R11 is grounded. Further, the gate terminal of the transistor Q11 is always set to a high level,
Transistor Q11 is always in an active state (ON state).

The dummy buffer sections DB2 and DB3 have the same configuration as the dummy buffer section DB1, except that the selection signal S1 output from the counter & register 10 is input to the gate terminal of the transistor Q12,
The selection signal S2 output from the counter & register 10 is input to the gate terminal 13. The impedance values of the dummy buffer sections DB1 to DB3 are different from each other.

The current comparator 9 includes a dummy buffer DB1
ＤＢDB3 and the current flowing through the dummy resistance element Rd are compared, and a signal corresponding to the current difference between the two is supplied to the counter & register 10.

The counter & register 10 includes a current comparator 9
, The logic of the selection signals S1 and S2 supplied to the dummy buffer units DB2 and DB3 and the output buffer 4 is switched. That is, the counter & register 10 switches the logic of the selection signals S1 and S2 to control the sum of the currents flowing through the dummy buffer sections DB1 to DB3 and the current flowing through the dummy resistance element Rd to be equal.
When the two currents become equal, it is considered that the impedance is matched, and the output buffer 4 sets the output impedance according to the logic of the selection signals S1 and S2 at that time.

FIG. 3 is a block diagram showing the internal configuration of the output buffer 4. In FIG. 3, the same components as those of the conventional output buffer shown in FIG.
3 includes three buffer units B1 to B3.
12 is common to the output buffer of FIG. 12, but the MOS transistors Q1 to Q6 in the buffer units B1 to B3 are provided.
12 is different from FIG. 12 in that resistance elements R1 to R6 are connected to the drain terminal of. The buffer section B1 has NMOS transistors Q1 and Q2 and resistance elements R1 and R2. One end of the resistance element R1 is connected to the power supply terminal Vcc, the other end of the resistance element R1 is connected to the drain terminal of the transistor Q1, and its source terminal. Is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the drain terminal of the transistor Q2, and the source terminal of the transistor Q2 is grounded. The UP signal output from the sense amplifier 5 shown in FIG. 1 is input to the gate terminal of the transistor Q1, and the down signal output from the sense amplifier 5 is input to the gate terminal of the transistor Q2.

The buffer section B2 has a buffer section B1.
In addition to having NMOS transistors Q3 and Q4 and resistance elements R3 and R4 connected in the same manner as
2 and inverters INV1 and INV2. NAND
The up signal is input to one input terminal of the gate G1, and the selection signal S1 is input to the other input terminal. The output of the NAND gate G1 is input to the gate terminal of the NMOS transistor Q3 via the inverter INV1. The down signal is input to one input terminal of the NAND gate G2, and the selection signal S1 is input to the other input terminal. The output of the NAND gate G2 is input to the gate terminal of the NMOS transistor Q4 via the inverter INV2.

The buffer section B3 is connected to the buffer section B1.
In addition to having NMOS transistors Q5 and Q6 and resistance elements R5 and R6 connected in the same manner as
4 and inverters INV3 and INV4. NAND
The up signal is input to one input terminal of the gate G3, and the selection signal S2 is input to the other input terminal. The output of the NAND gate G3 is input to the gate terminal of the NMOS transistor Q5 via the inverter INV3. The down signal is input to one input terminal of the NAND gate G4, and the selection signal S2 is input to the other input terminal. The output of the NAND gate G4 is input to the gate terminal of the NMOS transistor Q6 via the inverter INV4.

Each of the buffer units B1 to B3 in the output buffer 4 shown in FIG. 3 is a dummy buffer unit DB1 shown in FIG.
To DB3, the dummy buffer unit DB2
And the buffer section B2, and the dummy buffer section DB3 and the buffer section B3 are selected as a set according to the logic of the selection signals S1 and S2. On the other hand, the dummy buffer unit DB1
And the buffer section B1 are selected regardless of the logic of the selection signal. The impedance values of the dummy buffer units DB1 to DB3 are set to integral multiples (for example, five times) of the impedance values of the buffer units B1 to B3.

More specifically, the ratio of the on-resistance of the MOS transistors Q1, Q3, and Q5 in each of the buffer units B1 to B3 and the ratio of the resistance elements R1, R3, and R5 are made substantially equal. , Q4, Q6 and the ratio of the resistance elements R2, R4, R6 are made substantially equal.

For example, the dummy resistance element Rd shown in FIG.
When the current flowing through the dummy buffer DB1 is substantially equal to the current flowing through the dummy buffer DB1, the selection signals S1 and S2 become (0, 0), and the impedance value of the output buffer 4 is set by the impedance value of the buffer section B1. .

More specifically, when the selection signals S1 and S2 are (0,
0), when the up signal output from the sense amplifier 5 is at a high level, the MOS transistor Q1 in FIG. 3 is turned on, and the impedance value of the output buffer 4 is determined by the on resistance of the MOS transistor Q1 and the resistance of the resistance element R1. Set by value. If the down signal output from the sense amplifier 5 is at a high level, the MOS transistor Q2 is turned on, and the impedance value of the output buffer 4 is
2 and the resistance value of the resistance element R2.

On the other hand, when the sum of the currents flowing through the dummy buffers DB1 and DB2 is substantially equal to the current flowing through the dummy resistance element Rd shown in FIG. 2, the selection signals S1 and S2 become
(1, 0), and the impedance value of the output buffer 4 becomes
It is set by the sum of the impedance values of the buffer units B1 and B2.

More specifically, when the selection signals S1 and S2 are (1,
0), if the up signal output from the sense amplifier 5 is at a high level, the MOS transistors Q1 and Q3 in FIG. 3 are turned on, and the impedance value of the output buffer 4 is determined by the on resistance of the MOS transistors Q1 and Q3, It is set by the resistance values of the resistance elements R1 and R3. If the down signal output from the sense amplifier 5 is at a high level, the MOS transistors Q2 and Q4 are turned on, and the impedance value of the output buffer 4 is determined by the on resistance of the MOS transistors Q2 and Q4 and the resistance elements R2 and R4. It is set by the resistance value.

On the other hand, when the sum of the currents flowing through the dummy buffers DB1 and DB3 is substantially equal to the current flowing through the dummy resistance element Rd shown in FIG. 2, the selection signals S1 and S2 become
(0,1), and the impedance value of the output buffer 4 becomes
It is set by the impedance values of the buffer units B1 and B3.

More specifically, when the selection signals S1 and S2 are (0,
In 1), if the up signal output from the sense amplifier 5 is at a high level, the MOS transistors Q1 and Q5 in FIG. 3 are turned on, and the impedance value of the output buffer 4 is determined by the on resistance of the MOS transistors Q1 and Q5, It is set by the resistance values of the resistance elements R1 and R5. If the down signal output from the sense amplifier 5 is at a high level, the MOS shown in FIG.
The transistors Q2 and Q6 are turned on, and the impedance value of the output buffer 4 is set by the on-resistance of the MOS transistors Q2 and Q6 and the resistance values of the resistance elements R2 and R6.

FIG. 4 is a diagram showing the relationship between the output voltage of the output buffer 4 and the output current. In FIG. 4, the buffer unit B
This figure shows how the characteristics change when the sum of the on-resistance of the MOS transistor Q1 and the like in 1 to B3 and the resistance element R1 and the like is constant and the ratio of the resistance value of the resistance element R1 and the like to the total is changed. .

As shown in the figure, as the ratio of the resistance values of the resistance elements R1 to R6 increases, the output voltage and the output current change linearly, and the fluctuation of the impedance value in the transient state decreases. However, in order to increase the ratio of the resistance values of the resistance elements R1 to R6, it is necessary to increase the gate width of the MOS transistor and reduce the on-resistance.

FIG. 5 is a diagram showing the relationship between the ratio of the resistance values of resistance elements R1 to R6 and the gate width of MOS transistors Q1 to Q6. The vertical line in FIG. 5 represents the ratio of the gate width of the MOS transistors Q1 to Q4, where the gate width of the MOS transistors Q1 to Q4 when the resistance elements R1 to R6 are not provided is 1.

As is apparent from FIG.
To make the ratio of the resistance value of R6 more than 70%, for example,
It is necessary to make the gate width of the transistors Q1 to Q6 three times or more. However, when the gate width of each of the MOS transistors Q1 to Q6 is increased, there is a problem that the chip becomes large, and practically, it is desirable to set it to about 50 to 70%.

As described above, the programmable impedance circuit according to the first embodiment includes the MOS transistor Q in each of the buffer units B1 to B3 constituting the output buffer 4.
1 to Q6 and resistance elements R1 to R6 are provided, and the impedance value of each buffer section B1 to B3 is set by the on-resistance of the MOS transistors Q1 to Q6 and the resistance values of the resistance elements R1 to R6. Therefore, even in the case where the buffer portion B1 changes, the impedance variation of each of the buffer portions B1 to B3 is reduced, and the impedance matching when mounted on a printed board or the like becomes easy.

When the resistance elements R1 to R6 shown in FIG. 3 are formed on a semiconductor substrate, the amount of impurity ions to be implanted and the width and length of the resistance element vary in the manufacturing process. Although the impedance values of the resistance elements R1 to R6 also vary, in the present embodiment, since the impedance value of the output buffer 4 is adjusted according to the impedance value of the external dummy resistance element Rd, the resistance value of each resistance element is adjusted. , The impedance value of the output buffer 4 can be set.

Incidentally, in the output buffer 4 shown in FIG. 3, although the resistance elements R1 to R6 are connected to the respective drain terminals of the MOS transistors Q1 to Q6, they may be connected to the source terminals.

FIG. 6 is a diagram showing an example of an output buffer 4 'in which resistance elements R1 to R6 are connected to source terminals of MOS transistors Q1 to Q6, respectively. Also in this case, the impedance value of each of the buffer sections B1 to B3 is determined by the on-resistance of the MOS transistors Q1 to Q6 and the resistance values of the resistance elements R1 to R6, and suppresses the impedance fluctuation as in the output buffer 3 of FIG. it can.

In each of FIGS. 3 and 6, MOS transistors Q1 to Q6 each have a resistance element R
Since 1 to R6 are connected, the voltage VDS between the drain and the source can be reduced, so that generation of hot carriers can be prevented.

Further, the resistance elements R2, R4, R6 of FIG.
The resistance elements R1, R3, and R5 of FIG. 6 also function as a protection circuit when a high voltage due to static electricity is externally applied to the output terminal out of the output buffer 4 '. Electric breakdown is less likely to occur.

However, as shown in FIG. 6, when the resistance elements R1 to R6 are connected to the source terminals of the MOS transistors Q1 to Q6, the gate-source voltage VGS is smaller than when the resistance elements are connected to the drain terminals. Therefore, the on-resistance of the MOS transistors Q1 to Q6 may increase.

[Second Embodiment] In the first embodiment,
Although an example has been described in which a resistance element is provided inside each buffer section constituting the output buffer 4, a resistance element may be provided only in some of the buffer sections.

FIG. 7 is a circuit diagram showing the internal configuration of an output buffer 4 "in the second embodiment. The output buffer 4" in FIG. 7 has three buffer units B1 ', B2', and B3 '.
Is provided.

The buffer section B1 'includes an NMOS transistor Q
1, an NMOS transistor Q2, and resistance elements R7 and R8. The source terminal of the NMOS transistor Q1 is connected to a power supply terminal Vcc, the drain terminal is connected to one end of the resistance element R7, and the other end of the resistance element R7 is connected to a resistance element. At one end of R8, a resistor R
The other end of 8 is connected to the drain terminal of the NMOS transistor Q2, and the source terminal of the NMOS transistor Q2 is grounded. The UP signal from the sense amplifier 5 shown in FIG. 1 is input to the gate terminal of the transistor Q1 ', and the down signal from the sense amplifier 5 is input to the gate terminal of the transistor Q2.

The buffer section B2 'includes a PMOS transistor Q3', an NMOS transistor Q4, and a NAND gate G.
1, G2 and an inverter INV2. The up signal is input to one input terminal of the NAND gate G1, and the selection signal S1 is input to the other input terminal. NAND gate G
The output of 1 is input to the gate terminal of the PMOS transistor Q3 '. Also, one input terminal of the NAND gate G2 is
The down signal is input, and the selection signal S1 is input to the other input terminal.
Is entered. The output of the NAND gate G2 is
The signal is input to the gate terminal of the NMOS transistor Q4 via NV2.

The buffer section B3 is connected to the buffer section B2.
A PMOS transistor Q5 ', an NMOS transistor Q6, NAND gates G3, G4, and an inverter INV4, which are connected in the same manner.

When the selection signals S1 and S2 output from the A / D converter 2 in FIG. 1 are (0, 0), if the up signal output from the sense amplifier 5 is at a high level, the NMOS transistor Q1 Is turned on, and the impedance value of the output buffer 4 is set by the ON resistance of the NMOS transistor Q1 and the resistance value of the resistance element R7. If the down signal is at a high level, the impedance value of the output buffer 4 is set by the ON resistance of the NMOS transistor Q2 and the resistance value of the resistance element R8.

On the other hand, when the selection signals S1 and S2 are (1,0), if the up signal is at a high level, the NMOS transistor Q1 and the PMOS transistor Q3 'are turned on, and the impedance value of the output buffer 4 becomes The resistance is set by the on-resistance of the transistors Q1 and Q3 'and the resistance value of the resistance element R7. When the down signal is at a high level, the NMOS transistors Q2 and Q4 are turned on, and the impedance value of the output buffer 4 is set by the on resistance of the NMOS transistors Q2 and Q4 and the resistance value of the resistance element R8.

On the other hand, when the selection signals S1 and S2 are (0, 1), if the up signal is at a high level, the NMOS transistor Q1 and the PMOS transistor Q5 'are turned on, and the impedance value of the output buffer 4 becomes It is set by the on-resistance of the transistors Q1 and Q5 'and the resistance value of the resistance element R7.
If the down signal is at a high level, the NMOS transistors Q2 and Q6 are turned on, and the impedance value of the output buffer 4 is set by the on resistance of the NMOS transistors Q2 and Q6 and the resistance value of the resistance element R8.

The solid line shown in FIG. 8 is an actual measurement curve showing the relationship between the output voltage and the output current when the output of the output buffer 4 changes from the low level to the high level.
This is an ideal straight line when the impedance value is constant. As illustrated, the output buffer 4 ″ of FIG. 7 can control the impedance value to be substantially constant even in a transient state in which the output voltage changes.

As described above, in the second embodiment, of the three buffer units B1 to B3, only one buffer unit B1 has the resistance elements R7 and R8, but the selection signals S1 and S2
Is changed, the impedance value of the output buffer 4 becomes a value dependent on the resistance values of the resistance elements R7 and R8. Therefore, if the impedance values of the resistance elements R7 and R8 are set in advance so that the ratio of the resistance values of the resistance elements R7 and R8 to the impedance value of the output buffer 4 becomes, for example, 50%, the fluctuation of the impedance value in the transient state can be achieved. Becomes smaller.

The resistance elements R7 and R8 in FIG. 7 also function as a protection circuit when a high voltage due to static electricity is externally applied to the output terminal out of the output buffer 4 '. By providing these resistances, Electrostatic breakdown is less likely to occur.

[Third Embodiment] In the first and second embodiments, an example in which complementary input data is input to the output buffer 4 has been described. However, in the present invention, the output buffer 4 to which single input data is input is used. Is also applicable.

FIG. 9 is a circuit diagram showing the internal configuration of the output buffer 4a according to the third embodiment. The output buffer 4a in FIG. 9 includes buffer units B1 "and B2".

The buffer section B1 ″ is connected to the PMOS transistor Q
7, Q8, NMOS transistors Q9, Q10, an inverter INV5, and resistance elements R9, R10. PM
The source terminal of the OS transistor Q7 is connected to the power supply Vcc, the drain terminal is connected to the source terminal of the PMOS transistor Q8, the drain terminal is connected to one end of the resistor R9,
Is connected to one end of the resistor R10, the other end of the resistor R10 is connected to the drain terminal of the NMOS transistor Q9, the source terminal is connected to the drain terminal of the NMOS transistor Q10, and the source terminal of the NMOS transistor Q10 is grounded. ing. The same signal (up signal or down signal) is input to the gate terminals of the PMOS transistor Q7 and the NMOS transistor Q10, and the selection signal S1 is input to the gate terminal of the NMOS transistor Q9.
, The inverted signal of the selection signal S1 is input.

On the other hand, the buffer section B2 ″ includes PMOS transistors Q11 and Q12 and NMOS transistors Q13 and Q1.
4, the inverter INV6, and the resistance elements R11 and R12.
And The source terminal of the PMOS transistor Q11 is connected to the power supply Vcc, and its drain terminal is connected to the PMOS transistor Q12.
Of the resistor R11, the other end of the resistor R11 is connected to one end of the resistor R12, the other end of the resistor R12 is connected to the drain terminal of the NMOS transistor Q13, and the source terminal is connected to the NMOS. Transistor Q
14, and the source terminal of the NMOS transistor Q14 is grounded. Also, PMOS
The same signal as the signal input to the gate terminal of the PMOS transistor Q7 is input to the gate terminals of the transistor Q11 and the NMOS transistor Q14.
The selection signal S2 is input to the gate terminal of No. 3 and the inverted signal of the selection signal S2 is input to the gate terminal of the PMOS transistor Q12.

In FIG. 9, for example, selection signals S1, S
When 2 is (1,0), both the PMOS transistor Q8 and the NMOS transistor Q9 are turned on. At this time, if the single input data is at a low level, the PMOS transistor Q7 is turned on, and the impedance value of the output buffer 4a is set by the on resistance of the PMOS transistors Q7 and Q8 and the resistance value of the resistance element R9. If the single input data is at a high level, the NMOS transistor Q10 turns on, and the impedance value of the output buffer 4 becomes equal to the NMOS transistors Q9 and Q9.
It is set by the on-resistance of 10 and the resistance value of the resistance element R10.

On the other hand, when the selection signals S1 and S2 are (0, 1), the PMOS transistor Q12 and the NMOS transistor Q1
3 are both turned on. At this time, if the single input data is at a low level, the PMOS transistor Q11 turns on, and the impedance value of the output buffer 4 becomes equal to the PMOS transistor Q1.
1, the on-resistance of Q12 and the resistance value of resistance element R11. If the single input data is at a high level, the NMOS transistor Q14 is turned on, and the impedance value of the output buffer 4 is changed to the NMOS transistors Q13 and Q14.
And the resistance value of the resistance element R12.

As described above, even in the case of an output buffer to which single input data is input, an impedance value corresponding to the logic of the selection signals S1 and S2 can be set.

In the first and second embodiments described above,
Although the example in which the output buffer 4 is configured by the three buffer units B1 to B3 has been described, the number of buffer units and dummy buffer units is not limited to three. Similarly, in the third embodiment, three or more buffer units may be provided.

In the first to third embodiments, the circuit elements constituting each of the buffer sections B1 to B3 are not limited to those shown in the drawings. For example, an AND gate may be provided instead of the NAND gate, or the inverter may be removed and a PMOS transistor may be connected instead of the NMOS transistor.

Further, in FIG. 7, although the resistance elements R7 and R8 are provided only inside the buffer section B1, the buffer section B
A resistance element may be provided only inside of B2 and B3.

For example, FIG. 10 is a circuit diagram showing an example in which a resistance element is provided in the buffer sections B2 and B3 instead of providing no resistance element in the buffer section B1. In this case, when the selection signals S1 and S2 are (0,0), the impedance cannot be set by the resistance element.
When 1, S2 is (1,0) or (0,1), the same effect as in FIG. 7 can be obtained.

As shown in FIGS. 7 and 10, when a resistance element is provided only in a part of the MOS transistors Q1 to Q6, it is desirable to connect the resistance element to a MOS transistor having as large a conductance as possible. The reason is that the impedance of the entire circuit is greatly affected by the on-resistance of the MOS transistor having a large conductance.

[0077]

As described above in detail, according to the present invention, a switching element and a resistance element connected in series are provided in an output buffer, and the switching element and the resistance value of the resistance element are changed according to the on-resistance of the switching element and the resistance value of the resistance element. In addition, since the impedance value of the output buffer is set, it is possible to suppress the fluctuation of the impedance in the transient state of the output buffer as compared with the case where the impedance value of the output buffer is set only by the ON resistance of the switching element.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of a programmable impedance circuit.

FIG. 2 is a diagram showing an internal configuration of an A / D converter.

FIG. 3 is a block diagram showing an internal configuration of an output buffer.

FIG. 4 is a diagram showing a relationship between an output voltage and an output current of an output buffer.

FIG. 5 is a diagram showing the relationship between the ratio of the resistance value of a resistance element and the gate width of a MOS transistor.

FIG. 6 illustrates an example of an output buffer in which a resistance element is connected to a source terminal of a MOS transistor.

FIG. 7 is a circuit diagram showing an internal configuration of an output buffer according to a second embodiment.

FIG. 8 is a diagram illustrating a relationship between an output voltage and an output current when an output buffer is driven at a low level.

FIG. 9 is a circuit diagram showing an internal configuration of an output buffer according to a third embodiment.

FIG. 10 is a diagram showing an example in which a resistance element is provided in buffer units B2 and B3 in a modification of FIG. 7;

11A is a normal waveform without ringing, and FIG. 11B is a waveform diagram with ringing.

FIG. 12 is a circuit diagram of a conventional programmable impedance circuit.

FIG. 13 is a diagram illustrating a relationship between an output voltage and an output current when an output buffer is driven at a low level.

FIG. 14 is a diagram illustrating a relationship between an output voltage and an output current when an output buffer is driven at a high level.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reference current detection circuit 2 A / D converter 3 Clock generation circuit 4 Output buffer 5 Sense amplifier 6 Address decoder 7 Memory cell array 8 Column selector 9 Current comparator B1 to B3 Buffer section DB1 to DB3 Dummy buffer section Rd Dummy resistor Q1 to Q6 MOS transistor R1 to R6 Resistance element

Claims (10)

[Claims] 1. A programmable impedance circuit comprising an output buffer capable of setting any one of a plurality of different impedance values according to a logic of a selection signal, wherein the output buffer has a switching element and a resistance element. An impedance value of the output buffer based on an on-resistance of the switching element and a resistance value of the resistance element so that the impedance value of the output buffer does not fluctuate in a transient state in which the output voltage of the output buffer changes. A programmable impedance circuit characterized by setting: 2. A programmable impedance circuit comprising an output buffer capable of setting any one of a plurality of impedance values different from each other according to a logic of a selection signal, wherein the output buffer comprises a plurality of buffers having different impedance values from each other. At least one of the buffer units has a switching element and a resistance element connected to one end of the switching element, and the impedance value of the buffer unit having the switching element and the resistance element Is set according to the on-resistance of the switching element and the resistance value of the resistance element. According to the logic of the selection signal, some of the buffer units are selected, and the impedance value of the selected buffer unit is selected. Setting an impedance value of the output buffer based on Programmable impedance circuit. 3. The switching element is a MOS transistor, and the resistance element is a diffusion resistance formed by diffusing impurity ions into a semiconductor substrate or a poly resistance made of polycrystalline silicon. Item 3. The programmable impedance circuit according to Item 2. 4. The method according to claim 1, wherein at least one of said buffer units is a MOS transistor.
A transistor, and a resistance element connected to a drain terminal or a source terminal of the MOS transistor, and a corresponding impedance value of the buffer unit based on a sum of an on-resistance of the MOS transistor and a resistance value of the resistance element. 4. The programmable impedance circuit according to claim 2, wherein 5. Each of the buffer sections has a MOS transistor and a resistance element connected to a drain terminal or a source terminal of the MOS transistor, and includes an on-resistance of the MOS transistor and a resistance value of the resistance element. 5. The programmable memory device according to claim 4, wherein each of the buffer units is different, and a ratio of an on-resistance of each of the MOS transistors is substantially equal to a ratio of a resistance value of each of the resistance elements.・ Impedance circuit. 6. At least one of said buffer units includes said MOS transistor having neither said drain terminal nor said source terminal connected to said resistance element, and said buffer unit has an on-resistance of said MOS transistor. 5. The programmable impedance circuit according to claim 4, wherein: 7. Complementary input data whose logic is opposite to each other is input to each of the plurality of buffer units, outputs of the plurality of buffer units are connected to each other, and at least one of the plurality of buffer units is , An NMOS transistor corresponding to one of the complementary input data,
A resistor connected to the drain or source terminal of the NMOS transistor, and corresponding to the other of the complementary input data, a PMOS transistor; and a resistor connected to the drain or source terminal of the PMOS transistor. One of an NMOS transistor and a PMOS transistor is turned on according to the logic of the complementary input data and the selection signal, and the on-resistance of the turned on MOS transistor and the MOS transistor connected to the MOS transistor are turned on. 7. The programmable impedance circuit according to claim 2, wherein a corresponding impedance value of said buffer section is set according to a resistance value of a resistance element. 8. The programmable amplifier according to claim 7, wherein said complementary input data is an output of a sense amplifier for amplifying cell data read from a memory cell.
Impedance circuit. 9. A single input data is input to each of the plurality of buffer units, outputs of the plurality of buffer units are connected to each other, and at least one of the plurality of buffer units includes a PMOS transistor. A resistance element connected to the drain or source terminal of the PMOS transistor, an NMOS transistor, and a resistance element connected to the drain or source terminal of the NMOS transistor. Either the PMOS transistor or the NMOS transistor is turned on in accordance with the logic of the selection signal, and the correspondence is determined in accordance with the on resistance of the turned on MOS transistor and the resistance value of the resistance element connected to the MOS transistor. 7. The programmable input device according to claim 2, wherein an impedance value of the buffer section is set. Impedance circuit. 10. A plurality of dummy buffer units provided corresponding to each of said plurality of buffer units and having different impedance values, and an impedance substantially equal to an externally mounted dummy resistor among said dummy buffer units. 10. A programmable signal output circuit according to claim 2, further comprising: a selection signal output circuit that detects a dummy buffer unit having a value and outputs the selection signal having a logic corresponding to the detected dummy buffer unit. Impedance circuit.