JPS5697151A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5697151A
JPS5697151A JP17217879A JP17217879A JPS5697151A JP S5697151 A JPS5697151 A JP S5697151A JP 17217879 A JP17217879 A JP 17217879A JP 17217879 A JP17217879 A JP 17217879A JP S5697151 A JPS5697151 A JP S5697151A
Authority
JP
Japan
Prior art keywords
register
word
shunting
constitution
return
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17217879A
Other languages
Japanese (ja)
Inventor
Hiroyuki Koarai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17217879A priority Critical patent/JPS5697151A/en
Publication of JPS5697151A publication Critical patent/JPS5697151A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To reduce the time required for shunting and restoration and to increase the performance of processing, by using the internal memory of CPU when the operation is made with the program instruction such as the call and return of subroutine.
CONSTITUTION: The internal memory LS of the central processing device is made to a plurality of sets #0W#n, and the constitution is made to stack constitution. Further, the register by a given word is incorporated in each set, and the 0 word is taken as the control word, and the specified word succeeding to it is taken as the register and conventional registers such as program, status and words. During the shunting due to the content of the control word, the display of absence of vacant register can be made in the address of the next vacant set on and after. Further, the pointer PTR indicates the head address of the register set which is active, the register group is operated as one set for subroutine call instruction and return instruction to reduce the time required for the shunting and return and to improve the performance of processing.
COPYRIGHT: (C)1981,JPO&Japio
JP17217879A 1979-12-29 1979-12-29 Information processor Pending JPS5697151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17217879A JPS5697151A (en) 1979-12-29 1979-12-29 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17217879A JPS5697151A (en) 1979-12-29 1979-12-29 Information processor

Publications (1)

Publication Number Publication Date
JPS5697151A true JPS5697151A (en) 1981-08-05

Family

ID=15937014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17217879A Pending JPS5697151A (en) 1979-12-29 1979-12-29 Information processor

Country Status (1)

Country Link
JP (1) JPS5697151A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6151243A (en) * 1984-08-20 1986-03-13 Toshiba Corp Register type operation processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6151243A (en) * 1984-08-20 1986-03-13 Toshiba Corp Register type operation processor
JPH0258649B2 (en) * 1984-08-20 1990-12-10 Tokyo Shibaura Electric Co

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