JPS5717164A - Manufacture of complementary mos semiconductor device - Google Patents

Manufacture of complementary mos semiconductor device

Info

Publication number
JPS5717164A
JPS5717164A JP9185180A JP9185180A JPS5717164A JP S5717164 A JPS5717164 A JP S5717164A JP 9185180 A JP9185180 A JP 9185180A JP 9185180 A JP9185180 A JP 9185180A JP S5717164 A JPS5717164 A JP S5717164A
Authority
JP
Japan
Prior art keywords
mos transistor
transistor
photoresist
gate
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9185180A
Other languages
Japanese (ja)
Inventor
Masahide Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP9185180A priority Critical patent/JPS5717164A/en
Publication of JPS5717164A publication Critical patent/JPS5717164A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To form a complementary MOS transistor integrated circuit by two processes of masking by using a mask covering one channel of the transistor and patterning the other transistor in a complementary transistor. CONSTITUTION:A P well 13 is formed on an N type semiconductor substrate 11 to form a gate oxide film 14, a field oxide film 12, a conductive layer 15 such as poly crystal silicon or the like. Then, the whole P type region 13 surface is covered by using a photoresist 30 to form a gate section 17 and a wiring section 18 on the N type region. Next, boron is implanted in the substrate by ion implantation technique to form the source and drain regions 20 of a P channel MOS transistor. Next, the photoresist 30 is removed to form a photoresist 31 covering the whole P-MOS transistor surface and having a gate and a wiring pattern on an N-MOS transistor formation section and an N channel MOS transistor is formed.
JP9185180A 1980-07-04 1980-07-04 Manufacture of complementary mos semiconductor device Pending JPS5717164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9185180A JPS5717164A (en) 1980-07-04 1980-07-04 Manufacture of complementary mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9185180A JPS5717164A (en) 1980-07-04 1980-07-04 Manufacture of complementary mos semiconductor device

Publications (1)

Publication Number Publication Date
JPS5717164A true JPS5717164A (en) 1982-01-28

Family

ID=14038067

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9185180A Pending JPS5717164A (en) 1980-07-04 1980-07-04 Manufacture of complementary mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS5717164A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6342161A (en) * 1986-08-07 1988-02-23 Toshiba Corp Manufacture of cmos type semiconductor device
US5021353A (en) * 1990-02-26 1991-06-04 Micron Technology, Inc. Split-polysilicon CMOS process incorporating self-aligned silicidation of conductive regions
US5023190A (en) * 1990-08-03 1991-06-11 Micron Technology, Inc. CMOS processes
US5026657A (en) * 1990-03-12 1991-06-25 Micron Technology, Inc. Split-polysilicon CMOS DRAM process incorporating self-aligned silicidation of the cell plate, transistor gates, and N+ regions
US5030585A (en) * 1990-03-22 1991-07-09 Micron Technology, Inc. Split-polysilicon CMOS DRAM process incorporating selective self-aligned silicidation of conductive regions and nitride blanket protection of N-channel regions during P-channel gate spacer formation
US5032530A (en) * 1989-10-27 1991-07-16 Micron Technology, Inc. Split-polysilicon CMOS process incorporating unmasked punchthrough and source/drain implants
US5134085A (en) * 1991-11-21 1992-07-28 Micron Technology, Inc. Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories
US5252504A (en) * 1988-05-02 1993-10-12 Micron Technology, Inc. Reverse polysilicon CMOS fabrication
US6040208A (en) * 1997-08-29 2000-03-21 Micron Technology, Inc. Angled ion implantation for selective doping

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6342161A (en) * 1986-08-07 1988-02-23 Toshiba Corp Manufacture of cmos type semiconductor device
US5252504A (en) * 1988-05-02 1993-10-12 Micron Technology, Inc. Reverse polysilicon CMOS fabrication
US5032530A (en) * 1989-10-27 1991-07-16 Micron Technology, Inc. Split-polysilicon CMOS process incorporating unmasked punchthrough and source/drain implants
US5021353A (en) * 1990-02-26 1991-06-04 Micron Technology, Inc. Split-polysilicon CMOS process incorporating self-aligned silicidation of conductive regions
US5026657A (en) * 1990-03-12 1991-06-25 Micron Technology, Inc. Split-polysilicon CMOS DRAM process incorporating self-aligned silicidation of the cell plate, transistor gates, and N+ regions
US5030585A (en) * 1990-03-22 1991-07-09 Micron Technology, Inc. Split-polysilicon CMOS DRAM process incorporating selective self-aligned silicidation of conductive regions and nitride blanket protection of N-channel regions during P-channel gate spacer formation
US5023190A (en) * 1990-08-03 1991-06-11 Micron Technology, Inc. CMOS processes
US5134085A (en) * 1991-11-21 1992-07-28 Micron Technology, Inc. Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories
US6040208A (en) * 1997-08-29 2000-03-21 Micron Technology, Inc. Angled ion implantation for selective doping

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