JPS5792476A - Cash memory controller - Google Patents

Cash memory controller

Info

Publication number
JPS5792476A
JPS5792476A JP55166075A JP16607580A JPS5792476A JP S5792476 A JPS5792476 A JP S5792476A JP 55166075 A JP55166075 A JP 55166075A JP 16607580 A JP16607580 A JP 16607580A JP S5792476 A JPS5792476 A JP S5792476A
Authority
JP
Japan
Prior art keywords
operand
cash memory
line
storage
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55166075A
Other languages
Japanese (ja)
Inventor
Hiroyuki Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55166075A priority Critical patent/JPS5792476A/en
Publication of JPS5792476A publication Critical patent/JPS5792476A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To achieve IC-implementation and to speed up CPU operation by reducing a data transfer bus in width by providing an operand cash memory with a data storage line between a CPU and the cash memory. CONSTITUTION:An operand storage request is supplied from a CPU1 through an operand readout/storage request line 4 to an instruction cash memory control circuit 7 and an operand cash memory control circuit 10. The circuit 7 checks whether its request address is registered in an instruction cash memory 9 or not and, when so, makes the registration ineffective. The circuit 10, on the other hand, checks whether the request address is registered in an operand cash memory 12 or not and, when so, writes operand information from the CPU1 to a data line 6 in the memory 12 to supply an operand storage address and data to a main storage device 17 through an operand readout/storage request line 14 and a data line 6, thereby storing the operand.
JP55166075A 1980-11-25 1980-11-25 Cash memory controller Pending JPS5792476A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55166075A JPS5792476A (en) 1980-11-25 1980-11-25 Cash memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55166075A JPS5792476A (en) 1980-11-25 1980-11-25 Cash memory controller

Publications (1)

Publication Number Publication Date
JPS5792476A true JPS5792476A (en) 1982-06-09

Family

ID=15824510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55166075A Pending JPS5792476A (en) 1980-11-25 1980-11-25 Cash memory controller

Country Status (1)

Country Link
JP (1) JPS5792476A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6116350A (en) * 1984-07-02 1986-01-24 Nec Corp Buffer storage device of information processor
JPS61500861A (en) * 1983-12-27 1986-05-01 フオ−ド　モ−タ−　カンパニ− Filter trap regenerator

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61500861A (en) * 1983-12-27 1986-05-01 フオ−ド　モ−タ−　カンパニ− Filter trap regenerator
JPH0530964B2 (en) * 1983-12-27 1993-05-11 Ford Motor Co
JPS6116350A (en) * 1984-07-02 1986-01-24 Nec Corp Buffer storage device of information processor

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