JPS5835935A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

Info

Publication number
JPS5835935A
JPS5835935A JP56135172A JP13517281A JPS5835935A JP S5835935 A JPS5835935 A JP S5835935A JP 56135172 A JP56135172 A JP 56135172A JP 13517281 A JP13517281 A JP 13517281A JP S5835935 A JPS5835935 A JP S5835935A
Authority
JP
Japan
Prior art keywords
container
solder
pads
insulating plate
interconnection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56135172A
Other languages
Japanese (ja)
Other versions
JPH0258793B2 (en
Inventor
Nobuhiko Mizuo
水尾　允彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56135172A priority Critical patent/JPS5835935A/en
Publication of JPS5835935A publication Critical patent/JPS5835935A/en
Publication of JPH0258793B2 publication Critical patent/JPH0258793B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10424—Frame holders
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発＃４は半導体装置、特に半導体素子収納容器を配線
基体へ相互接続パッドにより接合させた組立体の接合構
成及び方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention #4 relates to improvements in the bonding structure and method of a semiconductor device, particularly an assembly in which a semiconductor device storage container is bonded to a wiring substrate by interconnection pads.

高集積度の半導体ＩＣのパッケージ乃至は組立体の形式
としてチップキャリアと称されるものが公知であるが、
これはＩＣ素子を対人する通常はセラミック製の容器に
相互接続用ノくラドをメタライズパターンによつて設け
ておき、これをプリント板への実装用接続ビンを有する
通常セラミック龜の配−基体（マザーボートンへ半田に
よつて接合する形式のものである０このチップΦヤリア
と配線基体との接合は、夫々圧設は喪相互接続用）くラ
ドの少なくとも一方に半田揚は又は印刷等の手法で半田
を付着しておき、これによシ予め所謂半田のタマリを形
成しておいて、しかる後両者を重ね合せて熱処理を施す
ことによって行なっているＯかかる従来技術においては
、パッドへの半田の付着量が一定せず、半田不足や過剰
によって相互接続の不完全な箇所やｒｉｓ接パッド間が
シ四−トしてしまう箇所ばしばしは発生するという欠点
を生じていた。％にテップキャリア形式は高集積夏ＩＣ
を高密１ｆ＋実装する目的で使われることが多いので、
相互接続面には数１００μ角の徽小なパッドを多数密集
させておくことが要求されるようになっており、上記原
因による不良は益々増加する傾向にあるＯ 従って本発明はかかる半導体収納容器と配線基板との相
互接続パッド半田付けによる接合を行なうに当り、上記
した従来のような接続不完全或いはショートによる不良
発生を解消し、また製作工程もむしろ簡潔化し得る構造
及び製法を提供せんとするものである。A type of package or assembly for highly integrated semiconductor ICs is known as a chip carrier.
In this method, interconnection holes are provided by a metallized pattern in a container, usually made of ceramic, in which the IC elements are placed, and then this is mounted on a mounting base (usually a ceramic plate) having connection holes for mounting on a printed circuit board. This chip is connected to the motherboard by soldering.The bonding between this chip and the wiring substrate is done by soldering or printing on at least one of the two pads (for mutual connection). In this conventional technique, the solder is applied to the pad, a so-called solder ball is formed in advance, and then the two are overlapped and heat treated. The amount of solder deposited is not constant, and insufficient or excessive solder often results in incomplete interconnections or gaps between RIS contact pads. %Tip carrier format is highly integrated summer IC
It is often used for the purpose of high-density 1F+ implementation.
It has become necessary to have a large number of small pads of several hundred square micrometers closely packed together on the interconnection surface, and the number of defects caused by the above-mentioned causes tends to increase more and more. When bonding interconnection pads and wiring boards by soldering, it is desirable to provide a structure and manufacturing method that eliminates the occurrence of defects due to incomplete connections or short circuits as described above in the past, and also simplifies the manufacturing process. It is something to do.

本発明の王たる特徴は、容器と配１ＩＩＩ基体との間に
絶縁板を介在させ、この絶縁板には各対応ノクツド関の
相互接続部において半田が貫通する孔を設けた構造にあ
り、またその製法上の１ｌｉＰ黴は、各相互接続部分に
対応し九位置に貫通孔１有し且つ線貫通孔に半田が挿入
された接続用絶縁板を用意して、これを容器と配線基体
との間に挾んで重ねた状態で熱処理し、接合させる工程
にある。The main feature of the present invention is that an insulating plate is interposed between the container and the wiring board, and this insulating plate is provided with holes through which the solder passes through at the interconnection portion of each corresponding notch. The 1liP mold used in the manufacturing method is to prepare a connection insulating plate with nine through holes corresponding to each interconnection part and with solder inserted into the wire through holes, and connect this between the container and the wiring base. The process involves heat-treating the stacked layers sandwiched in between and joining them together.

以下本発明を実施例により詳細に説明する０第１図は本
発明において使用する接続用絶縁板の製造方法の１例を
示す図である。絶縁板ｌとしては、例えはボリイきドの
如き耐熱性のある樹脂のシート（例えば厚さ１００μ）
を用い、このシートｌに対し、容器と配線基板の相互接
続パッドのパターンに一致した位置に貫通孔２をパンチ
ングによって形成しておく０−万、直径５００μ程表の
半田ホール３を予め形成しておき、これを第１図（ａ）
の如く貫通孔２上に配置し、上方より平板にて押圧して
各貫通孔２内に半田ボール３を圧入する０４　ｉＪ圧入
用補助具で、半田ボール３を受ける凹部５が形成されて
おり、これにより半田ボール３は圧潰されることなく第
１図（ｂ）の如くに貫通孔へ圧入される。The present invention will now be described in detail with reference to examples. FIG. 1 is a diagram showing one example of a method for manufacturing a connection insulating plate used in the present invention. As the insulating plate l, for example, a sheet of heat-resistant resin such as bolywood (for example, 100μ thick)
Solder holes 3 with a diameter of approximately 500 μm are preformed on this sheet L by punching a through hole 2 at a position that matches the pattern of interconnection pads between the container and the wiring board. Figure 1(a)
The solder balls 3 are placed over the through holes 2 as shown in FIG. As a result, the solder ball 3 is press-fitted into the through hole as shown in FIG. 1(b) without being crushed.

半田ボール３は、１箇所の相互接続部分に対して適量の
半田量分だけのサイズとするものである。The solder ball 3 is sized to accommodate an appropriate amount of solder for one interconnection portion.

ｍ１図（Ｉ））の如き相互＊続用の耐熱性シート１を用
意したなら、これを７８２図（ａ）の如く、容器１０と
配線基体２０との間に介在させて重ね合わせる。After preparing the mutually compatible heat-resistant sheet 1 as shown in Fig. 782 (I)), it is interposed between the container 10 and the wiring substrate 20 and overlapped as shown in Fig. 782 (a).

第２１ｉｌｌＩにおいて、１１は容ｉｉｉ！１０１１の
相互接続用パッドであり、例えば金のペーストで印刷形
成されたものである。セラミック製の容器１０は、本例
では典聾的なチックキャリア形式のものでおり、１２は
封入されたＩＣ素子、１３はリードワイヤ、１４はコバ
ール製の封止用キャップ板である。本発８１１はこのテ
ップギヤリアの内部構造には関係していないので詳創は
省略しであるｏ２１は配線基体（マず−ボード）２０１
１１１に設けられた相互接続用パッドである。配線基体
２０も構造詳細の図示は省略するが、これは例えはセラ
ミック製の基体であってスクリーン印刷によるメタライ
ズ配線層が単層又は多層に形成され、必要に応じてＪ！
にプリント板への実装のための接続ビンを付設したもの
である。In the 21st ill I, 11 is yongiii! 1011 interconnection pads, for example printed with gold paste. In this example, the ceramic container 10 is in the form of a deaf tick carrier, and 12 is an encapsulated IC element, 13 is a lead wire, and 14 is a sealing cap plate made of Kovar. Since the present invention 811 is not related to the internal structure of this tip gearbox, the details are omitted. o21 is the wiring board (mass board) 201
111 is an interconnection pad provided at 111. The detailed structure of the wiring base 20 is also omitted, but this is a base made of ceramic, for example, and has a single or multilayer metallized wiring layer formed by screen printing.
It is equipped with a connection pin for mounting on a printed board.

＠　２　＠（ａ）の如く絶縁シート１、容器１０、及び
配線基体２０をムねた状態で熱処理を施すと、半田ボー
ル３は熔融し、各パッド１１．２１と合金化して第２図
（ｂ）の如く相互接続が行なわれる０ここで、各半田ボ
ール３は、従来の如く半田量や印刷で半田のタマリを作
成する場合と比べると、一定量とするのが容易であり、
各相互接続ノ（ラドに対」７て常に適量の半田を与える
ことができるため、全てのパッドにおいて再現性良く良
好な半田接続を行なうことができる。しかも絶縁シート
ｌは半田との濡れが悪いので熔融半田の周囲への孤が９
を抑制すると共に、容器１０と配融基＠２０との間隔を
常に一足に保つスペーサとしての効果も期待でき、それ
によつて余分な半田の拡がりによる隣接パッド間のショ
ートも起し難いという効果も得られる０ 以上のように本発明によれば、各相互接続）くラドに対
して常に適量２の半田を与えることができるため、従来
経験場れたような半田の過不足によるショートや接続不
良事故を減らすことができ、更には絶縁板の介在によつ
で相互接続部の対向ノくラド間隔が常に一定に保たれて
再現性の扱い接合を実現できるものである。そして製造
上程においても、本発明でに相互接続用絶縁板を予め〃
１！に用意しておけは、接合工程自体はむしろ従来よシ
短縮されることになり、組立工程所要時間は短縮される
効果がある〇 μｊ１接続用半田シートとしては上記実施例で説明した
ｍ１図に示すもの以外にも、例えば耐＃１ａ絶縁シート
に設けた貫通孔にリベット形状の半田を挿入固足した形
態のものや、或いはかがる絶縁シートの貫通孔に銅のよ
うな良導金属の７・トメ乃至リベットを固足し、その表
義に半田を半球状に付着させたもの等を用いることがで
きる０@2 When heat treatment is applied to the insulating sheet 1, the container 10, and the wiring base 20 in a pressed state as shown in @(a), the solder balls 3 are melted and alloyed with each pad 11 and 21, as shown in FIG. The interconnection is carried out as in b). Here, it is easier to make each solder ball 3 a constant amount compared to the conventional case of creating a solder ball by soldering or printing,
Since the appropriate amount of solder can always be applied to each interconnection pad, good solder connections can be made with good reproducibility on all pads.Moreover, the insulating sheet l has poor wetting with solder. Therefore, the arc around the molten solder is 9
In addition to suppressing this, it can also be expected to act as a spacer to always keep the distance between the container 10 and the fusion group @ 20 at one foot, thereby preventing short circuits between adjacent pads due to the spread of excess solder. As described above, according to the present invention, it is possible to always apply an appropriate amount of solder to each interconnection board, so that short circuits and poor connections caused by excess or insufficient solder, which have been experienced in the past, can be avoided. Accidents can be reduced, and furthermore, due to the presence of the insulating plate, the spacing between opposing rads of the interconnection parts can always be kept constant, making it possible to achieve reproducible handling and joining. Also, during the manufacturing process, the insulating plates for interconnection are prepared in advance according to the present invention.
1! If prepared in advance, the bonding process itself will be shortened compared to the conventional method, and the time required for the assembly process will be shortened. As a solder sheet for μj1 connection, use the m1 diagram explained in the above example. In addition to what is shown, for example, rivet-shaped solder may be inserted into a through hole in a #1A insulating sheet, or a conductive metal such as copper may be inserted into a through hole in an insulating sheet. 7. A tome or rivet can be fixed and solder attached in a hemispherical shape can be used as a representation.0

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明実施例に使用する相互接続用絶縁板の製
作工程を示す図、第２図は本発明実施例の半導体装置及
びその製造上程を示す図である。 ｌ・・・・・・絶縁板 ３・・・・・・半田ホール １０・・・・・・半導体素子収納容器 １１．２１・・・・・・相互接続用パッド２０・・・・
・・配？に蕪体FIG. 1 is a diagram showing a manufacturing process of an interconnection insulating plate used in an embodiment of the present invention, and FIG. 2 is a diagram showing a semiconductor device according to an embodiment of the present invention and its manufacturing process. l...Insulating plate 3...Solder hole 10...Semiconductor element storage container 11.21...Interconnection pad 20...
・・Distribution? Turnip body

Claims (1)

【特許請求の範囲】 １、半導体素子を収容する容器と、該容器を搭載する配
！１Ｉｌｆ１体とに夫々対応する接続用パッドを設けて
おき、各対応するパッドを半田により相互接続した装置
において、前記容器と前記配線基体との間に絶縁板が介
在し、練絶縁板には前記各対応するパッドを相互接続す
る半田が貫通する孔が各相互接続部分に形成されている
ことを特徴とする半導体装置。 ２、半導体素子を収容する容器と、該容器を搭載する配
線基体とに夫々対応する接続用パッドを設けておき、各
対応するパッドを半田により相互接続することによシ前
記！！器を前記配線基体へ接合するに当シ、各相互接続
部分に対応した位置に貫通孔を有し且つ該貫通孔に半田
が挿入された接続用絶縁板を、前記容器と前記配線基体
との関に介在させ、熱処理を施すことにより両者１接合
させることを特徴とする半導体装置の粂遣方法。[Claims] 1. A container for accommodating a semiconductor element, and a mounting arrangement for mounting the container! In a device in which connection pads are provided for each of the 1Ilf units and the corresponding pads are interconnected by soldering, an insulating plate is interposed between the container and the wiring base, and the insulating plate is provided with the A semiconductor device characterized in that a hole is formed in each interconnect portion through which solder interconnects each corresponding pad. 2. By providing connection pads corresponding to the container that accommodates the semiconductor element and the wiring base on which the container is mounted, respectively, and interconnecting the corresponding pads with solder, it is possible to do the above! ! When joining the container to the wiring base, a connection insulating plate having through holes at positions corresponding to each interconnection part and solder inserted into the through holes is inserted between the container and the wiring base. A method for bonding a semiconductor device, characterized in that the two are bonded together by interposing the bond and applying heat treatment.
JP56135172A 1981-08-28 1981-08-28 Semiconductor device and its manufacturing method Granted JPS5835935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56135172A JPS5835935A (en) 1981-08-28 1981-08-28 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56135172A JPS5835935A (en) 1981-08-28 1981-08-28 Semiconductor device and its manufacturing method

Publications (2)

Publication Number Publication Date
JPS5835935A true JPS5835935A (en) 1983-03-02
JPH0258793B2 JPH0258793B2 (en) 1990-12-10

Family

ID=15145513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56135172A Granted JPS5835935A (en) 1981-08-28 1981-08-28 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JPS5835935A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60123093A (en) * 1983-12-07 1985-07-01 富士通株式会社 Method of attaching semiconductor device
JPS60182189A (en) * 1984-02-29 1985-09-17 キヤノン株式会社 Soldering method
DE3818894A1 (en) * 1987-06-05 1988-12-22 Hitachi Ltd SOLDER CARRIER, METHOD FOR THE PRODUCTION THEREOF AND METHOD FOR ASSEMBLY OF SEMICONDUCTOR ARRANGEMENTS UNDER THE USE THEREOF
EP0673188A1 (en) * 1994-03-15 1995-09-20 Siemens Nixdorf Informationssysteme AG Belt for providing solder depots for soldering components on a printed circuit board
EP0804056A3 (en) * 1996-04-26 1999-02-03 NGK Spark Plug Co. Ltd. Improvements in or relating to connecting board
EP0804057A3 (en) * 1996-04-26 1999-02-10 NGK Spark Plug Co. Ltd. Improvements in or relating to connecting board for connection between base plate and mounting board
US6278183B1 (en) 1999-04-16 2001-08-21 Ming-Tung Shen Semiconductor device and method for manufacturing the same

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03132692A (en) * 1989-10-18 1991-06-06 Matsushita Electric Ind Co Ltd Method for driving liquid crystal display device and its driving circuit
JPH0450998A (en) * 1990-06-15 1992-02-19 Matsushita Electric Ind Co Ltd Liquid crystal display device and driving method and driving device thereof
TW415050B (en) 1999-04-16 2000-12-11 Shen Ming Dung Semiconductor chipset module and the manufacturing method of the same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60123093A (en) * 1983-12-07 1985-07-01 富士通株式会社 Method of attaching semiconductor device
JPS60182189A (en) * 1984-02-29 1985-09-17 キヤノン株式会社 Soldering method
DE3818894A1 (en) * 1987-06-05 1988-12-22 Hitachi Ltd SOLDER CARRIER, METHOD FOR THE PRODUCTION THEREOF AND METHOD FOR ASSEMBLY OF SEMICONDUCTOR ARRANGEMENTS UNDER THE USE THEREOF
US4906823A (en) * 1987-06-05 1990-03-06 Hitachi, Ltd. Solder carrier, manufacturing method thereof and method of mounting semiconductor devices by utilizing same
EP0673188A1 (en) * 1994-03-15 1995-09-20 Siemens Nixdorf Informationssysteme AG Belt for providing solder depots for soldering components on a printed circuit board
EP0804056A3 (en) * 1996-04-26 1999-02-03 NGK Spark Plug Co. Ltd. Improvements in or relating to connecting board
EP0804057A3 (en) * 1996-04-26 1999-02-10 NGK Spark Plug Co. Ltd. Improvements in or relating to connecting board for connection between base plate and mounting board
US6278183B1 (en) 1999-04-16 2001-08-21 Ming-Tung Shen Semiconductor device and method for manufacturing the same
US6420210B2 (en) 1999-04-16 2002-07-16 Computech International Ventures Limited Semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
JPH0258793B2 (en) 1990-12-10

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