JPS5873129A - Method and apparatus for inspection of semiconductor element - Google Patents

Method and apparatus for inspection of semiconductor element

Info

Publication number
JPS5873129A
JPS5873129A JP17142281A JP17142281A JPS5873129A JP S5873129 A JPS5873129 A JP S5873129A JP 17142281 A JP17142281 A JP 17142281A JP 17142281 A JP17142281 A JP 17142281A JP S5873129 A JPS5873129 A JP S5873129A
Authority
JP
Japan
Prior art keywords
solder
electrodes
electrode
substrate
inspection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17142281A
Other languages
Japanese (ja)
Inventor
Kazuo Hirota
和夫 廣田
Masaru Sakaguchi
勝 坂口
Muneo Oshima
大島 宗夫
Ichiro Ishi
石 一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP17142281A priority Critical patent/JPS5873129A/en
Publication of JPS5873129A publication Critical patent/JPS5873129A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To eliminate remedy after mounting and to practice high-density mounting by a method wherein heating is applied from the rear of a probe card and projected electrodes at the upper face are abutted to solder balls on the electrodes of a semiconductor element for melting and connection and after inspection, the solder balls are again melted for partial fusion. CONSTITUTION:Projected electrodes 12 of W with Ni plating of an alumina ceramic made probe card 11 are positioned to the electrodes of a semiconductor substrate 7 and the temperature of the projected electrodes 12 is risen by applying heating from the rear of the card and after exceeding solder melting point, the projected electrodes 12 are abutted to the solder balls 9 on the electrodes of the substrate 7 for connection and heating is stopped. The solder balls will not be melted as far as the bases. A predetermined inspection is performed through a power wire 13 and signal wires 14 contained in the card and heating is done again and heating is stopped when the solder around the electrodes is melted and separated each other. Therefore, the solder on an element will scarcely be decreased and the bases of the solder balls do not melt and undesired heat hysteresis will not be given to the element. In this way, when a substrate like practically used wiring substrate is used for the prober, high-speed inspection is available and with the length of the electrodes 12, tip shape and solder ball diameter selected, solder correction after mounting becomes unnecessary.

Description

【発明の詳細な説明】 本発明は、はんだ溶融接続に供する半導体素子の検査方
法及び装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method and apparatus for inspecting semiconductor elements to be subjected to solder fusion bonding.

半導体素子は、実際に基板に実装されるまでにいくつか
の電気特性検査を経由してく侶。ウェハー上で電極まで
形成された段階、ダイシング、ダイボンド、ワイアボン
ド、パッケージングされた段階などである。そして、使
用される場合は、通常第6図に示すように半導体素子5
はプリント基板乙に実装される。
Semiconductor devices go through several electrical property tests before they are actually mounted on a board. These include the stage where electrodes are formed on the wafer, dicing, die bonding, wire bonding, and packaging. When used, a semiconductor element 5 is usually used as shown in FIG.
is mounted on the printed circuit board B.

しかし、プリント基板に実装された場合と第1図、第2
図に示したウェハ一段階での電気特性は一般に異なる。
However, when mounted on a printed circuit board and in Figures 1 and 2,
The electrical characteristics of the wafers shown in the figure are generally different at one stage.

すなわち、第1図、第2図において、半導体素子を形成
したウエノ\1は、プローブカード2より出たタングス
テンなどのプローブ4により、その上の電極と接触をと
りその電気特性が検査される。なお、第1図、第2図に
おいて3はプローブカード穴である。
That is, in FIGS. 1 and 2, a wafer 1 on which a semiconductor element is formed is brought into contact with an electrode thereon by a probe 4 made of tungsten or the like coming out of a probe card 2, and its electrical characteristics are tested. Note that 3 in FIGS. 1 and 2 is a probe card hole.

しかし、プローブ4の形状から、そこでの集中インダク
タンスが大きく、高速信号での検査に限界がある。すな
わち、プローブカード上での信号線の特性インピーダン
スをR,プローブの集中インダクタンスをLとすると、
時定数はL / Rとなり、R=50Ω、 L=50n
Hの場合で1nSで、この程度の高速信号を扱うと波形
がなまり正確な検査ができない。したがって通常は直流
的な特性検査が主になっている。
However, due to the shape of the probe 4, the lumped inductance there is large, and there is a limit to inspection using high-speed signals. That is, if the characteristic impedance of the signal line on the probe card is R, and the lumped inductance of the probe is L, then
The time constant is L/R, R=50Ω, L=50n
In the case of H, it is 1 nS, and when handling such a high-speed signal, the waveform becomes dull and accurate inspection cannot be performed. Therefore, direct current characteristic testing is usually the main method.

次に、このような半導体素子を第6図のようにパッケー
ジングした時、半導体素子5内の電極からはワイアボン
ドのワイア、パッケージ内5配線、リードを経由してプ
リント基板6のパターンに接続される。しだがってウエ
ノ・上で高速信号特性が検査できたとしても、実際にパ
ッケージされるとリードのインダクタンスやキャパシタ
ンスの影響が出てくる。
Next, when such a semiconductor element is packaged as shown in FIG. 6, the electrodes inside the semiconductor element 5 are connected to the pattern on the printed circuit board 6 via wirebond wires, wiring inside the package 5, and leads. Ru. Therefore, even if high-speed signal characteristics can be tested on Ueno, when it is actually packaged, the effects of lead inductance and capacitance will appear.

これに対し、はんだ溶融によるチップ接続では、第4図
に示すようにセラミック多層基板などの配線基板8の表
面の電極と半導体素子7上の電極とをはんだ9で接続し
ており、この両者の電極間距離、すなわち、はんだ高さ
は100μm〜300μmであシ、この部分での集中イ
ンダクタンスは極めて小さい。したがって第3図に示し
たパッケージのようにリードその他の影響がほとんど無
く、半導体素子の本来の特性が、基板表面電極上に出る
ことになる。さらに、この接続方法は、高密度実装1歩
留りの高い1括ボンデイングに適することから、その応
用が拡がりつつある。しかし、本半導体素子の検査には
、第1図、第2図と同様のブローバが用いられる。
On the other hand, in chip connection by melting solder, as shown in FIG. The distance between the electrodes, that is, the solder height is 100 μm to 300 μm, and the concentrated inductance in this portion is extremely small. Therefore, as in the package shown in FIG. 3, there is almost no influence from leads or other factors, and the original characteristics of the semiconductor element are exposed on the substrate surface electrode. Furthermore, since this connection method is suitable for high-density packaging and one-shot bonding with a high yield, its application is expanding. However, a blower similar to that shown in FIGS. 1 and 2 is used to test this semiconductor device.

第5図は、プローバ4の先端が半導体素子Z上の電極に
形成されているはんだボール9に接触している状態を拡
大して示したものである。
FIG. 5 is an enlarged view showing the state in which the tip of the prober 4 is in contact with the solder ball 9 formed on the electrode on the semiconductor element Z.

したがって、高密度実装、高歩留り1括ポンディング、
そしてパッケージの高速特性への影響もないという利点
をもったはんだ溶融接続法ではあるが、プローバとして
従来のワイアボンド用半導体素子に用いるブローバを用
いていたのでは、やはり高速特性が、チップ状態で測定
できない。そこで基板上に実装して、特性の悪いものを
補修したりする必要を生じる。
Therefore, high-density mounting, high-yield bulk bonding,
Although the solder fusion bonding method has the advantage of not affecting the high-speed characteristics of the package, the high-speed characteristics can still be measured in the chip state by using the conventional blower used for wire-bonding semiconductor devices as a prober. Can not. Therefore, it becomes necessary to mount them on a board and repair those with poor characteristics.

本発明の目的は、上記した従来技術の欠点を無くし、は
んだ溶融接続用半導体素子の高速電気特性検査を可能と
する、半導体素子検査方法及び検査装置を提供するもの
である。。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device testing method and testing device that eliminates the drawbacks of the prior art described above and enables high-speed electrical characteristic testing of semiconductor devices for solder fusion bonding. .

これにより、基板への素子搭載後の補修を無くし、はん
だ溶融接続による高密度実装実用化に寄与できる。
This eliminates the need for repairs after the elements are mounted on the board, and contributes to the practical application of high-density packaging using solder fusion connections.

本発明では、上記目的を達成するために、原理的には、
実際に用いる配線基板と同様の基板をプローバとして用
い、半導体素子上のはんだボールを溶かすための熱源を
基板裏面に持っている。さらに、半導体素子のはんだ量
を変化させないために、又、基板の反りを吸収するため
に、基板上の電極は突起状となっている。・さらに、高
速電気特性を精度良く検査するには、各信号電極まで一
定の特性インピーダンスで配線をし、反射雑音などを防
ぐ必要がある。
In order to achieve the above object, the present invention, in principle,
A board similar to the wiring board actually used is used as a prober, and a heat source is provided on the back side of the board to melt the solder balls on the semiconductor element. Furthermore, the electrodes on the substrate are protruded in order to not change the amount of solder on the semiconductor element and to absorb warpage of the substrate. -Furthermore, in order to accurately test high-speed electrical characteristics, it is necessary to wire with a constant characteristic impedance to each signal electrode to prevent reflection noise.

このため、従来のプローブのように、すべての電極への
プローブが同等に扱われるのではなく、信号電極は信号
配線に電源電極は、上記信号配線のレファレンス層とな
る電源層に接続される。
Therefore, unlike conventional probes, probes to all electrodes are not treated equally, but signal electrodes are connected to signal wiring, and power supply electrodes are connected to a power supply layer that is a reference layer for the signal wiring.

以下、図面により本発明の詳細な説明する第6図におい
て、11はその内部に信号配線、電源層を有する多層配
線基板からなるプローブカードで、通常アルミナセラミ
クスで作られる。
In FIG. 6, the present invention will be explained in detail with reference to the drawings. In FIG. 6, reference numeral 11 denotes a probe card consisting of a multilayer wiring board having signal wiring and a power supply layer therein, and is usually made of alumina ceramics.

12は、このグローブカードよりほぼ直角に突き出た突
起電極で、第7−図の断面図に示すように内部の信号配
線14や電源層16と接続されている。、ここで、信号
配線14は電源層16をレファレンス層としたストリッ
プ線路又はマイクロストリップ線路となっており、一定
の特性インピーダンスを有している。したがって、従来
のプローブのような集中インダクタンスは持たず、信号
配線長に応じた遅延はあるが、波形のなまりは生じない
。又、電源に対応する電極は、電源層に直接接続されて
いる。これは、基板を汎用とするために、電源電極も信
号配線と同様に、電源層に対し1定インピーダンスの配
線に接続し、基板の外で、あるいは端面で電源層に接続
した場合、直流的には、同じ結果であるが、高速パルス
では、この配線に信号が誘起され、反射雑音などとなっ
て高速電気特性が検査できない。
Reference numeral 12 denotes a projecting electrode projecting from the glove card at a substantially right angle, and is connected to the internal signal wiring 14 and power supply layer 16, as shown in the sectional view of FIG. Here, the signal wiring 14 is a strip line or a microstrip line with the power supply layer 16 as a reference layer, and has a constant characteristic impedance. Therefore, unlike conventional probes, it does not have lumped inductance, and although there is a delay depending on the signal wiring length, the waveform does not become rounded. Further, the electrode corresponding to the power source is directly connected to the power layer. In order to make the board general-purpose, the power supply electrodes are connected to the power supply layer with a constant impedance wiring in the same way as the signal wiring, and if they are connected to the power supply layer outside the board or at the end surface, the DC The results are the same, but with high-speed pulses, signals are induced in this wiring, resulting in reflection noise and the like, making it impossible to test high-speed electrical characteristics.

尚、これら信号配線層、電源層は基板としてアルミナセ
ラミクスを用いた場合、タングステンなどの導体が用い
られる。したがって突起電極も同じタングステンを用い
ることが好ましい。
Note that when alumina ceramics is used as the substrate, a conductor such as tungsten is used for these signal wiring layers and power supply layers. Therefore, it is preferable to use the same tungsten for the protruding electrodes.

しかし、タングステンだけでは、はんだに濡れないため
、比較的はんだに濡れ、かつ、くり返し使用に対しても
信頼性の高いニッケルメッキを行なう。この突起電極に
は、3つの目的がある。その一つは、大きいウェハ7上
の一つの半導体素子の検査をする場合、プローブカード
基板の反シによシ、ウェハ士の他の素子のはんだボール
に接触しないように十分な長さが必要である。第2番目
に電極を通常の基板上電極と同様の大きさにした場合検
査後、はんだボールのはんだが一部基板側に残り、その
後の半導体素子の接続信頼性を低下させないように、対
向面積を小さくする必要がある。第3には、加熱により
半導体素子上のはんだボールを済かし接続するが、その
熱は、この突起電極を経由してはんだボールに伝えられ
る。したがって、突起状にすることによシ乙の部分の熱
容量を小さくしはんだボールの底面側まで溶けないよう
にし、半導体素子に不要な熱履歴を与えない。この6つ
の目的を満たすために先端直径は、はんだボールの最大
直径の1/3以下、長さは、はんだボール高さ以上が好
ましい。このような突起電極は、前記した焼結したタン
グステンの他に銅メッキなどによっても形成できる。1
0はプローブカード11の裏面より熱を印加する熱源で
ホットジェット、赤外線照射、あるいは通常の発熱体か
らの熱伝導などが可能であるが、本発明の目的のために
は、前二者が好ましい。
However, since tungsten alone does not wet the solder, nickel plating is performed which is relatively wettable with the solder and has high reliability even after repeated use. This protruding electrode has three purposes. One of these is that when testing a single semiconductor device on a large wafer 7, the probe card board needs to be long enough to prevent it from touching the solder balls of other devices on the wafer. It is. Second, if the electrode is made to be the same size as a normal electrode on a board, the opposing area is needs to be made smaller. Thirdly, the solder balls on the semiconductor element are heated and connected, and the heat is transferred to the solder balls via the protruding electrodes. Therefore, by forming the solder ball into a protruding shape, the heat capacity of the solder ball is reduced to prevent it from melting to the bottom side of the solder ball, thereby preventing unnecessary heat history from being imparted to the semiconductor element. In order to meet these six objectives, it is preferable that the diameter of the tip is 1/3 or less of the maximum diameter of the solder ball, and the length is greater than or equal to the height of the solder ball. Such protruding electrodes can be formed not only from the sintered tungsten described above but also from copper plating. 1
0 is a heat source that applies heat from the back side of the probe card 11, and hot jet, infrared irradiation, or heat conduction from a normal heating element is possible, but for the purpose of the present invention, the former two are preferable. .

以下、本発明装置での検査方法を順を追って説明する。Hereinafter, the inspection method using the apparatus of the present invention will be explained step by step.

まず、突起電極と半導体素子電極の位置合わせがされ、
熱源10によりプローブカード11が加熱される。その
結果、プローブカードの突起電極12の温度が上昇し、
これがはんだ溶融温度を越えた後、ウエノ・とプローブ
カードを近づけ、突起電極をはんだボールに押しあては
んだを溶かし、全電極が接続のとれる所定量まで近づけ
た後、加熱を停止する。その結果、はんだボール底面ま
で溶けることはない。この状態で、所定の電気特性検査
を行なった後、再度熱源により加熱する。この時、ウエ
ノ・7とプローブカード11との間を引き離す方向にわ
ずかの力を加えておくことにより、突起電極周辺のはん
だが溶けた段階で分離されるため、半導体素子上のはん
だが減ることはほとんどなく、この時にも、はんだボー
ル底面は溶けないため、半導体素子に不要な熱履歴を与
えない。
First, the protruding electrode and the semiconductor element electrode are aligned,
Probe card 11 is heated by heat source 10 . As a result, the temperature of the protruding electrode 12 of the probe card rises,
After this exceeds the solder melting temperature, the Ueno probe card is brought close to the solder ball, the protruding electrode is pressed against the solder ball to melt the solder, and after all the electrodes are brought close to a predetermined distance where a connection can be established, heating is stopped. As a result, the bottom of the solder ball does not melt. In this state, after a predetermined electrical characteristic test is performed, it is heated again by a heat source. At this time, by applying a slight force in the direction of separating the Ueno 7 and the probe card 11, the solder around the protruding electrodes will be separated when it melts, reducing the amount of solder on the semiconductor element. Since the bottom surface of the solder ball does not melt even at this time, unnecessary heat history is not imparted to the semiconductor element.

以上述べた如く、本発明では、実際に用いる配線基板と
ほぼ同じ基板をプローノ(とじて用いているため、実際
の実装に近い形での高速電気特性の検査が可能であり、
突起電極により、半導体素子のはんだ量の減りを少なく
できる。その結果、はんだ溶融接続用半導体素子を高速
パルス回路等に使用する場合、実装後の補修もなくなり
、はんだ量に関する信頼性も確保できる。
As described above, in the present invention, a board that is almost the same as the wiring board that is actually used is used as a probe, so it is possible to test high-speed electrical characteristics in a form that is close to the actual mounting.
The protruding electrodes can reduce the loss of solder in the semiconductor element. As a result, when the semiconductor element for solder fusion connection is used in a high-speed pulse circuit or the like, there is no need for repairs after mounting, and reliability regarding the amount of solder can be ensured.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は従来技術の検査用プローバ第3図は従
来のDIL半導体素子の実装、第4図ははんだ溶融接続
の半導体素子の実装、第5図ははんだ溶融接続用半導体
素子のプロービングの様子を示す図、第6図は本発明に
よる検査装置、第7図は本発明のプローブカードの断面
図である。 1・・・半導体素子のウェハ 2・・・プローブカード 4・・・プローブ 9・・・はんだボール 10・・・熱源 12・・・突起電極 第1 回 第づ 巧
Figures 1 and 2 show a conventional inspection prober; Figure 3 shows a conventional DIL semiconductor device mounted; Figure 4 shows a solder-fused semiconductor element mounted; and Figure 5 shows a solder-fused semiconductor element mounted. 6 is a diagram showing the state of probing, FIG. 6 is a cross-sectional view of the inspection device according to the present invention, and FIG. 7 is a sectional view of the probe card of the present invention. 1...Semiconductor element wafer 2...Probe card 4...Probe 9...Solder ball 10...Heat source 12...Protruding electrode 1st episode

Claims (1)

【特許請求の範囲】 1、 はんだ溶融接続に供するはんだ゛ポールをその電
極上に有する半導体素子の検査において上記電極に対応
する位置に突起電極を有する多層基板を、その突起電極
を有する面とは逆の面から加熱し、上記突起電極を上記
はんだボールに押しあて、はんだの少なくとも一部溶融
によシ、半導体素子電極と突起電極間の導通をとり、上
記突起電極につながる多層基板内配線により検査のだめ
の信号の授受を行ない、半導体素子の検査を行なった後
、再度上記多層基板を加熱しはんだを溶かし上記半導体
素子と突起電極を引きはなすことを特徴とする半導体素
子検査方法。 2、 半導体素子の電源電極に接続されるべき突起電極
が、多層基板内信号線を経由せずに、基板内の対応する
電源導体層に接続されており、他の信号用電極に対応す
る突起電極は、基板内の信号用導体配線に接続されてお
り、該信号用導体配線は、上記電源導体層をレファレン
ス層とした一定の特性インピーダンスをもつラインとな
っており、同一基板上、又は、コネクタ等により接続さ
れた検査回路につながっていることを特徴とする特許請
求範囲第1項記載の半導体素子検査方法のだめの検査装
置。 3 突起電極が、タングステンを母体とし、その上にニ
ッケルメッキを施したものを用いることを特徴とする特
許請求範囲第2項記載の検査装置。 4、突起電極が、その先端部の直径がはんだボールの最
大径の3分の1以下、長さがはんだボール高さより長い
形状を有するものであるととを特徴とする特許請求範囲
第2項記載の検査装置。
[Claims] 1. In the inspection of a semiconductor element having a solder pole on the electrode for solder fusion connection, a multilayer substrate having a protruding electrode at a position corresponding to the electrode is used, and the surface having the protruding electrode is Heat is applied from the opposite side, the protruding electrode is pressed against the solder ball, at least a portion of the solder is melted, and conduction is established between the semiconductor element electrode and the protruding electrode, and the wiring in the multilayer board is connected to the protruding electrode. A method for testing a semiconductor device, characterized in that, after transmitting and receiving a test signal and testing the semiconductor device, the multilayer substrate is heated again to melt the solder and separate the semiconductor device and the protruding electrodes. 2. The protruding electrode to be connected to the power supply electrode of the semiconductor element is connected to the corresponding power conductor layer in the multilayer board without going through the signal line in the multilayer board, and the protrusion corresponding to the other signal electrode The electrode is connected to a signal conductor wiring in the substrate, and the signal conductor wiring is a line having a constant characteristic impedance with the power supply conductor layer as a reference layer, and is connected to the signal conductor wiring on the same substrate, or 2. A test device for testing a semiconductor device according to claim 1, wherein the test device is connected to a test circuit connected by a connector or the like. 3. The inspection device according to claim 2, wherein the protruding electrodes are made of tungsten and nickel plated thereon. 4. Claim 2, characterized in that the protruding electrode has a shape in which the diameter of the tip thereof is one-third or less of the maximum diameter of the solder ball, and the length is longer than the height of the solder ball. Inspection equipment as described.
JP17142281A 1981-10-28 1981-10-28 Method and apparatus for inspection of semiconductor element Pending JPS5873129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17142281A JPS5873129A (en) 1981-10-28 1981-10-28 Method and apparatus for inspection of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17142281A JPS5873129A (en) 1981-10-28 1981-10-28 Method and apparatus for inspection of semiconductor element

Publications (1)

Publication Number Publication Date
JPS5873129A true JPS5873129A (en) 1983-05-02

Family

ID=15922833

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17142281A Pending JPS5873129A (en) 1981-10-28 1981-10-28 Method and apparatus for inspection of semiconductor element

Country Status (1)

Country Link
JP (1) JPS5873129A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4931726A (en) * 1987-06-22 1990-06-05 Hitachi, Ltd. Apparatus for testing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4931726A (en) * 1987-06-22 1990-06-05 Hitachi, Ltd. Apparatus for testing semiconductor device

Similar Documents

Publication Publication Date Title
US5795818A (en) Integrated circuit chip to substrate interconnection and method
US6094060A (en) Test head for applying signals in a burn-in test of an integrated circuit
JP2000304773A (en) Packaging and interconnecting of contact structure
JP2000111576A (en) Packaging and mutual connection of contact structure
JP2001159642A (en) Contact structure with silicon finger contactor and total assembly structure using it
JPH07221104A (en) Method for manufacturing semiconductor device, semiconductor device, mask for forming electrode pin, and test method using mask for forming electrode pin
JP2012520572A (en) Microelectronic assembly with impedance controlled wire bond and reference wire bond
JPH06140484A (en) Probe card
US20030116863A1 (en) Semiconductor chip-mounting board
JP2000221210A (en) Packaging-mutual connection for contact structure
KR100193903B1 (en) Circuit boards and wire bonding devices to detect broken wires in bonding wires
CN109786265B (en) A packaged device, preparation method and signal measurement method
JP2715793B2 (en) Semiconductor device and manufacturing method thereof
JP2004347591A (en) Probe card for integrated circuit
US20020146920A1 (en) Method of soldering contact pins and the contact pins
JPH04338648A (en) Bump electrode formation method for semiconductor device, display device and electronic printing device
JPS5873129A (en) Method and apparatus for inspection of semiconductor element
JPS5811741B2 (en) probe board
JPH08220140A (en) Probe card and manufacture thereof
JP2001242195A (en) Contact structure
JPS6276733A (en) Wafer probe head
JP3249865B2 (en) Method for manufacturing semiconductor integrated circuit device
JPS63122140A (en) Semiconductor element inspecting device and manufacture thereof
JPS63122141A (en) Semiconductor element inspecting device
JPH0233960A (en) Semiconductor device