JPS5918679A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device, and more particularly to a field effect transistor made of a compound semiconductor, and particularly to the structure of an integrated circuit device including the field effect transistor.

(b) Technology background To further improve the capabilities of information processing equipment, etc.

There is a strong demand for higher speed, lower power consumption, and larger capacity of semiconductor devices used for this purpose.

Currently, most silicon (St) semiconductor devices are in practical use, but the speedup of St semiconductor devices is limited by 81 physical properties such as carrier mobility. Efforts are being made to realize semiconductor devices with higher speed and lower power consumption using large compound semiconductors.Currently, the compound semiconductors used in semiconductor devices are mainly made of ■-V group compounds, such as gallium.・Arsenic (GaAs)
, binary compound crystals such as indium/phosphorous (InP), and aluminum, gallium, arsenic (AlGaAs)
, indium, gallium, arsenic, phosphorus (InGaAsP
) and other ternary or higher compound mixed crystals.

■-As a transistor using a V group compound semiconductor,
Due to the short lifetime of minority carriers in these compound semiconductors, field effect transistors (
(hereinafter abbreviated as FET).

In particular, Jottky barrier type FETs or junction gate type FETs, which take advantage of the advantage of having a semi-insulating substrate to reduce ground capacitance, are mainly used.

(C) Conventional technology and problems To improve the uniformity and reproducibility of the semiconductor device mentioned above.

In addition, in order to ensure reliability, it is necessary to eliminate defects in the semiconductor crystal and to sufficiently control impurity concentration and the like. However, 1 For example, in a semi-insulating GaAs substrate, chromium (Cr), which is currently introduced to make it semi-insulating during single crystal growth, deteriorates over time during growth.
Furthermore, since a concentration difference occurs within the growth plane, if impurities were introduced directly into the substrate, the carrier concentration in that region would be likely to fluctuate due to the influence of the Cr concentration difference, making it difficult to satisfy the above requirements. I can't.

For this reason, the active region of a compound semiconductor device is often provided in an epitaxial growth layer formed on a substrate, and a buffer layer is often interposed between the epitaxial growth layer serving as the active layer and the substrate. Therefore, the active region of a compound semiconductor device is arranged in a laminated structure of epitaxially grown layers having different impurity concentrations, conductivity types, or compound compositions formed according to the purpose.

Q: What is a specific example of a conventional semiconductor device?
Schottky Hariake using aAs compound semiconductor
), Enhance-men)
t) Shape and debrisi, :y (, [)eplet
FIG. 1 shows a cross-sectional view of an example in which a 1on) type FET is formed on the same substrate.

In the figure, 1 is a semi-insulating QaAs substrate, 2 is a non-doped GaAs buffer layer formed by, for example, vapor phase epitaxial growth, 3 is an n-type GaAs layer with an impurity concentration of about 0.8×10 (α) formed in the same way, and 4 is a semi-insulating QaAs substrate. is the impurity concentration 1 formed in the n-type GaAS layer 3
．． 5X 1017 (crn-”: n-type region of about l, 5
is an element isolation region, 6 and 6' are gate electrodes, and 7 and 7' are
is a source electrode, and 8 and 8' are drain electrodes.

In the m1 diagram, n-type QaAs is formed by the gate electrode 6.
The FET in which the layer 3 is controlled as a channel layer is an enhancement type, and the FET in which the n-type region 4f is controlled as a channel layer by the gate electrode 6' is a depletion type.

In the structure of this conventional example, as a method for forming enhancement type and depletion type channel regions with different impurity concentrations in the same epitaxial growth layer, 1. When epitaxially growing the normal n-type GaAs layer 3, the impurity concentration of this layer is is set to the lower value of the impurity concentrations that suit the desired image shape, which is the value that is compatible with the ennosisment shape, and the impurity ions are implanted into the entire region where the depletion type FET tube is to be formed. In this process, the semiconductor substrate is subjected to heat treatment to activate the implanted impurities and provide an impurity concentration compatible with the depletion type.

However, in crystals into which impurities are introduced by ion implantation, collisions with the implanted ions cause damage to the crystal lattice and disturbance of the bonding interface.

Furthermore, since the impurity concentration is distributed with a statistical fluctuation range, it is inferior in terms of uniformity and the like compared to the distribution of impurities introduced during epitaxial growth.

Damage to the crystal due to collisions with implanted ions.

Although the problem is cured by heat treatment after ion implantation, it is not always completely cured, and furthermore, the entire semiconductor substrate is thermally denatured by this heat treatment.

Due to these problems, compound semiconductor devices, especially FETs,
It is judged that an improvement in the method for selectively forming regions with controlled carrier concentration is necessary for integrated circuit devices including the following.

(d) Purpose of the Invention The present invention relates to compound semiconductor devices, particularly integrated circuit devices including field effect transistors, by limiting damage to crystals and interfaces and impurity concentration deviations caused by ion implantation. The purpose of this research is to improve the characteristics of source and drain regions such as resistivity and transfer conductance, particularly their reproducibility, and reduce failure rates.

(e) Structure of the Invention The object of the present invention is to include a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, and a gate electrode, a source electrode, and a drain electrode disposed on the semiconductor layer; This is achieved by a semiconductor device in which the semiconductor layer region in contact with the electrode has a different impurity concentration than the semiconductor layer region in contact with the source and drain electrodes.

(') EXAMPLES OF THE INVENTION Examples of the present invention will be specifically described below along with manufacturing steps.

FIGS. 2(a) to 2(d) are cross-sectional views showing an embodiment in which the present invention is applied to an integrated circuit device including a QaAs Schottky barrier type FET.

Refer to FIG. 2(a), a semi-insulating QaAs substrate 11 with a thickness of 1.5 [μ+
n) non-doped G a A S buffer M4
12. A semiconductor substrate on which an n-type GaAs layer 13 of about 1.5×10 17 [crn-31 and a thickness of about 0.3 C μml is epitaxially grown with impurities is used.

However, in two cases, the impurity concentration of the n-type GaAs layer 13 in this embodiment is 1.
5×1017[on-3] is the selected impurity concentration '1r suitable for forming a depletion type FET.

First, in contact with the surface of the n-type GaAS layer 13, a protective film 14 made of aluminum nitride (AIN) or the like is formed to a thickness of about 50 (nm).

See Figure 2(b) To form an enhancement type FFJT.

The carrier concentration in the channel region is controlled by the method described below.

In other words, at the position where the gate electrode of the enhancement type FET is to be formed, for example, oxygen (0) ions are dosed only in the region 15, which is the length of the gate electrode plus the margin required for mask alignment. Amount lXl0 [cm
], ion implantation is performed by applying an energy of I8 of about 100 CKeV).

Note that n-type GaAs other than this carrier concentration control region 15
In order not to damage the layer 13, in this embodiment, it is used as a mask during ion implantation.

A mask having a laminated structure consisting of a photoresist (for example, Az1350J) film 16°, a titanium (T + ) film 17, and a gold (Ate) film 18 is used. This mask is used to remove the photoresist film 16 using a stripping solution or the like.
: It is easily removed.

Next, in order to heal damage to the carrier concentration control region 15 caused by ion implantation, the temperature was 600 ['c] for 20 hours.
Heat treatment is performed for about a minute. This heat treatment temperature is much lower than the conventional heat treatment temperature, which reaches about 800 degrees Celsius (approximately 800 degrees Celsius), which is conventionally performed for activation after silicon (Si) ion implantation, so it causes thermal denaturation in the semiconductor substrate. does not occur.

As a result of the carrier concentration control described above, the carrier concentration in this region 15 is approximately 7×1016' (cm-3).

See Figure 2 (C) Element isolation regions 19 are formed as described below.

Photoresist HK16'+ Tr BrA17/ and Au ll in the same village as the mask explained earlier.
QaAs
Reach a depth that is at least I/2 of the thickness of the buffer layer! Finally, multistage implantation of oxygen ions is performed. In this example, for example, 200 [KeV] and 1
00 [: KeV ], each with a dose of 1
．． A two-stage injection of 5×10(w) was performed.

Referring to FIG. 2(d), after peeling off the mask, source electrodes 20 and 21. The drain electrodes 22 and 23 are made of, for example, gold/germanium (AuQe)/gold (All), and the gate electrodes 24 and 25 are made of, for example, titanium (T).
i)-platinum (pt)-gold (Au).

In the integrated circuit device formed as described above, unlike the conventional method described above, ion implantation is localized directly under the gate electrode, and furthermore, because the heat treatment temperature is low, the source/drain region is The epitaxially grown layer in the channel region and its vicinity is maintained in good condition.

As a result, characteristics such as resistivity and transfer conductance of the source/drain regions, especially their reproducibility, are improved, and the failure rate is reduced.

Note that, as in the above embodiment, gate 1! Ama 1 just below pole 24
[Limited region] The carrier concentration in only the source region 5 is reduced, and the carrier a degree in the source region and drain region is kept at a high concentration.

It also has the effect that the contact resistance of the drain region with the resistor instep and both canopies is reduced compared to the conventional one.

Furthermore, this carry 70 degree distribution restricts the spread of the gate depletion layer in the lateral direction, particularly in the direction of the drain electrode 22, suppressing the generation of gun domains near the end face of the drain electrode 22 on the gate electrode 24 side. The withstand voltage is also improved.

Further, in the above embodiment, the maximum value of the oxygen ion concentration profile is determined by the n-type QaAs RE 1 which is the channel layer.
-3 is set at the center position in the depth direction fi￥K, but
By setting a large concentration of oxygen ions on the upper surface of the n-type GaAsI branch 13, the carrier concentration in the carrier C degree control area 15 is set to a smaller concentration on the upper surface. If we assume a profile in which the density increases gradually in the depth direction.

It is possible to obtain the required gate voltage and voltage-source-drain current characteristics and further improve the gate withstand voltage. .

In the embodiment described above, the n-type GaAs layer 1
3f, epitaxial growth to an impurity concentration compatible with depletion type F'ET [2nd, carrier concentration is reduced for enhancement type FET, but n
An effect similar to the above example can also be obtained by epitaxially growing the GaAs layer 13 to an impurity concentration suitable for an enhancement-type FET and adding impurities to the gate electrode forming region of the depletion-type FET.

(g) As described in detail, according to the present invention, impurities are removed by ion implantation, which inevitably causes damage to the epitaxial growth layer and the junction interface, which have excellent crystallinity and excellent uniformity of impurity concentration distribution. By keeping the introduction to the minimum necessary and further reducing the heat treatment temperature, it is possible to improve the characteristics, especially the reproducibility of characteristics, and reduce the failure rate of compound semiconductor FETs, especially for integrated circuit devices containing them. becomes.

[Brief explanation of drawings]

2(a) to 2(d) are cross-sectional views showing a manufacturing process of a semiconductor device according to the present invention; FIGS. In the figure, 111 semi-insulating QaAs substrate. ]2 is GaAS buffer 71J 13tjn type QaASI
4.15 is a carrier gamma concentration control region, 191d is an element isolation region Q, 20 and 21ij are source electrodes, 22 and 23 are drain electrodes, and 24 and 25 are gate electrodes. No. 1 Tabin 2 Diagram

Claims (1)

[Scope of Claims] A semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, and a gate electrode disposed on the semiconductor layer. 1. A semiconductor device comprising a source electrode and a drain electrode, wherein the semiconductor layer region in contact with the gate electrode has an impurity concentration different from that in the semiconductor layer region in contact with the source electrode and the drain electrode.