JPS5957479A - Manufacturing method of MOS type semiconductor nonvolatile memory device - Google Patents

Abstract

PURPOSE:To prevent the concentration of electric field at the edge part of the crossing angle of a control gate electrode as well as to contrive improvement in memory holding characteristics of a logic signal by a method wherein the crossing angle of the bottom face and side face located on the side of the floating gate electrode of a control gate electrode is obtusely formed. CONSTITUTION:Silicon oxide films 2, 3 and 5 and polycrystalline silicon films 4 and 6 are formed on a P type silicon substrate 1. Then, a control gate electrode 6a and the second gate oxide film 5a are successively left below a phtoresist film 7 by performing an etching. At this time, the crossing angle of the bottom face and the side face located on the side of the second gate oxide film 5a on the control gate electrode 6a is to be obtusely formed. Then, a floating gate electrode 4a and the first gate oxide film 3a are successively left by performing an isotropic etching and, at the same time, the main surface of the P type silicon substrate 1 is partially exposed. At this stage, as the side etching performed on the side face of the control gate electrode 6a does not make progress as approaching the upper part of the side face by the help of the hang- down part of the photoresist film 7, the crossing angle theta of the bottom face and the side face on the side of the floating gate electrode 4a on the control gate electrode 6a is formed making obtuse angle.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an ultraviolet erasing MO6 type semiconductor nonvolatile memory device [hereinafter 1'-FAMO8J (Flaa, ti
ng gateavalanche 1njectio
n MOS)].

jii Figures 1 (A) to 1 (D) are cross-sectional views showing the main stages of an example of a conventional FAMOS memory cell manufacturing method.

First, as shown in FIG. 1 (70), a silicon oxide film +21k for the element portion 91F that surrounds and isolates the element formation portion is placed in the U:, 1lfi portion of the p-type silicon substrate fil.
irJ is selectively formed, and then a relatively thick film 1. First gate oxidation) A silicon oxide film (3) for good formation is formed. Next, T81 diagram C
As shown in B), silicon oxide+fi+2+, (
3) Floating gates 'l'i!' over each surface of the 'l'i! A polycrystalline silicon film (4) for forming a pole is formed, and then impurities such as phosphorus are implanted or thermally diffused in order to set the resistivity of the polycrystalline silicon (IQ 14+) to a desired value. Next, the surface portion of the polycrystalline silicon film (4) is oxidized to form a silicon oxide film (5) for forming a second gate oxide film,
A control gate 11 is placed on the surface of this silicon oxide film (5).
A film of polycrystalline silicon 11 or (6) for forming the pole is formed, and then this polycrystalline silicon IP=! Impurities such as phosphorus are implanted or thermally diffused to bring the specific resistance of (s) to the desired value. Thereafter, a 7-photoresist Jli +71%- for an etching mask is selectively formed on the remaining portion of the polycrystalline silicon film t131 which will become the control gate fit pole. Next, as shown in FIG. 1(C), the resist film (7) is entirely masked with etching gold (1) in a self-aligned manner to form a polycrystalline silicon film (L61), a silicon oxide film (fit), and a polycrystalline silicon film (4). Then, a photoresist film (71) is applied to the silicon oxide film (3) and a control gate 71 is sequentially formed under the photoresist film (71).
tI (6a), +42 gate oxide film (5a,
), floating gate? 1 is left as the pole (4a) and the first gate oxide film (h) fK: and a part of the main surface of the p-type silicon plate [1] is exposed.

Next, as shown in FIG. 1 (1), the photoresist film (71) is removed, and then n-type impurities are selectively ionized onto the exposed main surface of the p-type silicon (plate 11.1). N-type source/drain regions (8
a), (8b) are formed. Next, as shown in FIG. 1(K), the source/drain 1llll 1m (''), (εlb), gate oxide film (aa) of 41 + floating gate 11 shield (4a ) + 2nd
Gate I agility film (anti) and control goo 11℃ pole (6a
) on each surface ((with a thin silicon oxide film 1
9), and further, using vapor phase growth method etc., 1'
A silicon oxide film (11) containing phosphorus is formed over each surface of the silicon oxide film (0) and the silicon oxide film (2)
form. After that, an aluminum wiring film (1ll) ffi is formed on the surface of the silicon oxide film + IT1, and finally, a passivation film (12
1f: When formed, a MOB memory cell is obtained using this conventional method.

Next, the operation of the FAMOFI memory cell [shown in FIG. 11] according to this conventional method will be described.

For example, by simultaneously applying a relatively high voltage to the n-type source/drain region (8a) and the control gate electrode (68), avalanche failure 11 occurs in the channel portion near the source/drain region (8a). Hot elect rJ
(hot electrons) (hereinafter abbreviated as "electrons"). The terminal child of tI generated at this time is the control gate electrode (6
a) Due to the tunneling phenomenon caused by the high voltage applied to
Floating game h tIj pole (4Q,) injected into huff storage village i
Be it. In this way, the LFC gate electrode (4a)
A logic signal is written by injecting and accumulating electrons in tut'. In general, system 4a (I f l
・The pole (6a) is connected to the ITI VC along with the control gate electrode of other memory cells, so when applying a logic signal to another memory cell, VX is connected to the control gate at the same time. Is it high even in the first season (60)? ! ,,: Pressure is applied. Therefore, I+) has already been applied to the floating gate electrode (
Is there a stone storage member Nf inside Z)? In order to prevent it from being pulled out by the 1l-1i voltage applied to the control gate electrode (6a), the control gate electrode (6a, ) 1 floating electrode (4a) The control between them is sufficient [it is necessary to be together, and it is chiru].

By the way, in this conventional method, Gisu 1 (c) V
Isotropic etching was used in step 7 as shown in c. 1
In case b, the floating gate electrode (4) of the control gate electrode (6a)
8) Angle where the bottom and side surfaces intersect [11th Ta (C)
θ] is an acute angle, and even when anisotropic etching is used, the angle θ is approximately a right circle. Therefore, when a positive crystal force is applied to the control gate 1) 1 pole (6a), Ill < δ11 the angle θ of the gate 11 (pole 68)
There is a serious crime in the edge part of 111, and the withstand voltage between both 'f' poles (6a1° (48)) decreases due to this serious crime, so in order to suppress this decrease in withstand voltage, the first
At the stage shown in FIG.
(by hitting the corresponding partial 1 bass, 1-
By rounding this edge part,
′- concentration was alleviated. However, the silicon oxide film (9
) becomes thicker, the thickness of the silicon oxide film (9) in the area between the two electrodes (fia) and (tilt) also becomes thicker, causing strain at the periphery of the control gate'/li electrode (6a). Because it occurs,
The thickness of the silicon oxide film (9) could not be made sufficiently thicker. Therefore, the floating gate 71' pole (4a) K
Electrons that have already been accumulated are used as control gate electrodes (68)
It has been difficult to prevent the signal from being pulled out due to the high voltage applied to it, and it has not been easy to improve the memory retention characteristics of the logic signal.

This invention is based on the above-mentioned points, and is based on 111
1 n11 gate l (, pole floating one piece gate (lj electrode)
111 and the sacral j plane 'fK: Obtuse angle
The manufacturing method of O8 is 1. 'A The purpose is to provide.

The 21st part 1 (A) to (F) is -'! of this invention! Mu
FIG. 2 is a 1-plane view, not showing the states f1 and f13, of the main steps of the example FAMos memory cell manufacturing method.

In the figure, the child number of the fe sample shown in the 11th bacterium,! :
ll11i1? Post the equivalent part.

First, L4) 21゛'Il (A) As shown in K,
941 +・, <t (A) F; Similar to the steps shown in (B), ((,■) shaped silicon plate (11)・; silicon oxide film for child molecules (2' ＋ 'n 1
Gate...Silicon oxide flu for forming a bowl film (3)
, floating gate electrode type! Polycrystalline silicon 11 Samurai (4
I, Yanagi 2 gate 1" rye silica for forming 1" 7
11K (5+ and 711IJnill) After forming a polycrystalline silicon layer (6) for forming 11 gates, bake it at a temperature of 100°C and 7°C on the portion of the polycrystalline silicon film (6) that is to be replaced with the control gate electrode. A photoresist for an etching mask made of, for example, a positive photoresist is formed by blowing.

Next, as shown in FIG. 2 (F3) K, etching is performed on the polycrystalline silicon film (6) and the silicon oxide film (5) using the photoresist film (71) as a mask to remove the area under the photoresist film (7). a control gate electrode (6a) and a second
gate oxide films (5a) are left in sequence. At this time, the second gate oxide film (
5) The bottom and side edges of the tortoise side form an acute angle θrat.

Next, as shown in Figure 21 (0), when the first resist film (71) is baked at a temperature of more than 100 degrees Cc3, the photoresist film (7) softens and Both ends of the photoresist film (7) sag.The photoresist film (7) is placed in such a way that the sagging of both ends of the photoresist film (7) does not reach the bottom surface of the control gate electrode (6a) on the second gate oxide film (gap) side.
Set a baking time of 1Km. Next, Figure 2 (D
), the polycrystalline silicon film is etched by isotropic etching using the photoresist film (7:) with both ends hanging down, and the suppressing gate'ilt pole (6a) and the second gate oxide film (edge) as masks. (41 and the silicon oxide film (3) to leave the floating gate electrode (4a) right and the first gate oxide film (3a) under the second gate oxide film (5a) in sequence, also using p-type silicon. A part of the main surface of the substrate (11) is exposed. At this stage, the side etching to the side surface of the control gate electrode (6a) is protected by the sagging portion of the photoresist film (7) toward the upper part of the side surface. Since the 1tilJ control gate electrode (6a) intersects the bottom and side surfaces of the floating gate stack (4th) side, the angle θ is an obtuse angle.

Next, after removing the photoresist film (71), the p-type silicon base &
fit ) i+4 N-type impurities are selectively introduced into the excavated surface to create type II source/drain regions (8!1.)
, (sb) is formed. Next, as shown in the first I/in part (F), the source do I/in head area (Bal, (8
b).

First gate oxide film C”) + floating gate small pole (4A)
.

Second gate oxide film (5a) and control gate electrode (6
A silicon oxide film +91 is formed over each surface of a), and a silicon oxide film (u) containing phosphorus is formed over the surface of silicon oxide IN+91 (21).
Form a shadow.

After that, an aluminum wiring film (II) is formed on the surface of the silicon oxide film (II), and finally, a passivation film (II) is formed on the surface of the silicon oxide film (FIG. When 121'i is formed, a FAMOS memory cell according to the method of this embodiment is obtained.

In the method of this example, the angle θ where the bottom surface of the sub-1 gate pole (6a) on the floating gate small pole (5a) side intersects with I10 is made obtuse, so the frozen silicon film (9 ) membrane'＋
'l-'Fr that... L doesn't have to be too thick, it's ffII
'#llIkeb 'il! Pole (”) CD MO・/-
) It is possible to prevent the electric field from concentrating on the edge portion. Therefore, the withstand voltage between both wheels and the poles (6a) and (4a,) is higher than 6' in the case of the method shown in Figure 1, IC'/B/Z-216. control gate '11
Even if a high voltage is applied to the pole (6a), the floating gate °11ζ pole (hammer) rt-J ~ (l
This accumulation type (1, so that there is no electron/bar pullout or Jt (
This can be done by understanding the memory retention characteristics of the ill signal.

JiJ % In this example, P-type silicon substrate (11) was used, but when using an n-type silicon substrate ((also; Melon use-1-'S). can.

As explained above, in the FAMOS manufacturing method of the present invention, the intersection angle between the bottom surface and the side surface on the floating and floating gate electrode side of the control gate electrode is made obtuse, so that the edge part of the intersection angle of the control gate electrode The electric field is 1! (It is possible to prevent this from happening during the first part, b). Therefore, the withstand voltage t'' between the control gate electrode and the floating gate electrode is better than that of the conventional method. IJ1. I will be +l16 'l-
By preventing the tIL element accumulated in the floating gate electrode at t from being pulled out due to the IF pressure, the memory retention characteristics of the marginal signal can be improved. can be achieved.

[Brief explanation of drawings]

g J Figure (A) ~ (lc) kj Jumei (7) FAM
FIGS. 2A to 2F are cross-sectional views of the main stages of an example of the 15IJ manufacturing method for an OS memory cell, and FIGS. 1fli (++i diagram showing the state of the 4g floor.
substrate (first conductivity type silicon substrate), (21 is a silicon oxide film for element isolation, (the blade is a silicon oxide film for forming the gate oxide film of coffin l, (3a) is the gate oxide film), (4)
) is a polycrystalline silicon film for forming a floating goo 11tt electrode, (4
a) id' is a floating gate electrode, (5) is a silicon oxide film for forming a second gate oxide film, (5a) is a second gate oxide film, ((+) is a polycrystalline silicon film for forming a control gate electrode) , (6a) is the control gate electrode, +71) is the etching mask photo/cyst film, (8a) and (81)
)) 1-1n type source/drain region (U2 transmission:
Table 6) Source/drain region). l? In the drawings, the same numbers 1' and 1 indicate the same parts. Agent Makoto Kuzuno - (foreign name) - Praise figure 1 figure 1 figure 2 figure 2

Claims (1)

[Claims] A first step of selectively forming a silicon oxide pattern for element isolation surrounding the element formation 11≦ on the main surface of a silicon substrate of Ill FA 1 conduction type, the element molecules 1tcm on the main surface of the silicon substrate A silicon oxide film for forming a first gate oxide film, a polycrystalline silicon film for forming a floating gate electrode, a silicon oxide film for forming a second gate oxide film, and a silicon oxide film for forming a second gate oxide film are formed on the portion separated by the atomized silicon film.
J #Gate m Polycrystalline silicon pattern film 71 for forming It type
The second step of forming 11th order, the above control game) 'rli
Is a photoresist film for an etching mask, which is softened by baking at a predetermined temperature, formed on the portion of the polycrystalline silicon film for electrode formation that should be on the control gate electrode? Step 43, using the photoresist film as a mask, etching is performed on the polycrystalline silicon film for forming the control gate electrode layer and the silicon oxide film for forming the second gate oxide film to form an 1IflJ layer under the photoresist film. In step @4, which leaves the gate electrode and the second gate oxide film, the photoresist film is coated with the above predetermined amount. = +ty baking to soften the photoresist film so that both ends of the photoresist film hang down so as not to touch the bottom surface of the second gate 1 fluoride film 4 of the control gate electrode. step, the first resist film with both ends hanging down, the control gate electrode and the gate 1 of the p\S2 JI
Isotropic etching using K as a mask is applied to the above floating gate.
The polycrystalline silicon film for forming the 1χ pole and the 17th) silicon oxide film for forming the gate oxide film 11! ! a sixth step of sequentially leaving a floating gate electrode and a first gate oxide film under the second gate oxide film and exposing a part of the main surface of the silicon substrate; and exposing the silicon substrate. A seventh step of selectively introducing impurities of the second conductivity type into the main surface portion to form source/drain regions of the second conductivity type.
Method for manufacturing H.