JPS596407B2 - Initial program loading method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an initial program loading method that allows an initial program to be loaded from the central processing unit CPU side to a channel device at an arbitrary address and capacity.

An example of the configuration of a conventional terminal control device is shown in FIG.

That is, the initial program in the main memory 2 is loaded from the CPU to the channel device CMC3 via the common bus. The CMC3 includes a microprocessor MPUII and a fixed memory R, as detailed in the embodiment of the invention in FIG.
Consists of 0M12 and volatile memory RAM13, conventionally C
Sends the initial program loading IPL command from the PUI to the MPUII, and based on this command the MPUI
I processes an initial program placed in a fixed area in the main memory 2 or placed in an arbitrary area by a predetermined program in the ROM 12 to be loaded into the RAM 13 in the CMC 3. Then, line adapters (LA0) 40, (L
One of AI)42...(LAT)43 is selected, and the I/O is driven and controlled by its output. In such initial program loading, the memory 1 of the initial program to be loaded is
Since the storage start address and the size (capacity), that is, the length of No. 3, are fixedly stored in the ROM 12 in the channel device 3, when the number of programs to be loaded increases, for example, when I/O is added, the ROM 12
It is necessary to change the loading program for the area, which has the disadvantage that it cannot be easily implemented.

SUMMARY OF THE INVENTION An object of the present invention is to provide an initial program loading method that allows even additional programs to be easily loaded from the CPU side to a channel device.

In order to achieve the above object, the initial program loading method of the present invention loads a program stored in the main memory of a central processing unit CPU into a channel memory of a channel device connected to the CPU by a common bus. The start address of the area in the main memory where the program to be loaded is stored, the start address of the area in the channel memory to be loaded, and the length indicating the size of the area.
means for instructing the channel device from U, and a circuit for loading the program into a storage area of the channel memory corresponding to the start address and length in the channel device, and the channel device loads the program into the storage area instructed by the CPU. It is characterized by loading a program.

The present invention will be described in detail below with reference to examples.

FIG. 2 is an explanatory diagram showing the configuration of an embodiment of the present invention.

In the figure, CPU1 and main memory 2 are connected to CMC3 of the channel section via a common bus, and further connected to (LAO) 41 to (LA7) of the subchannel section via the channel bus.
) 43 to control /O as shown in FIG.

As mentioned above, CMC3 is a microprocessor MPUll.
and stores a control program on its data bus.
In addition to connecting OMl2 and RAMl3, there is a receiver RCl4 for data input/output between the common bus and the data bus.
and a driver DRl6, and a write control register WCRl5 for CPU command instruction and a read control register RCRl7 for CPU command completion notification, which are the main parts of the present invention, are inserted outside the direct path.

Further, a driver/receiver DR/RC2O is provided between the data bus and the channel bus. Furthermore, CMC3
Interrupt control circuit 1 when transferring data to CPU1
8, and the main memory 2 and RAM by the MPUll command.
DM that controls direct data transfer between l3
A control circuits 19 are each connected to the data bus.

Now, the initial program in the area of address A of length L of main memory 2 is transferred to R of CMC3 by the command of CPU1.
If loading ends in the area of address B of AMl3,
First, as shown in FIG. 3, the address B area of the RAM 13 of the external channel device of the command type, the address A area of the main memory 2, and the number of bytes indicating the program length L are written in the WCRl5. The MPUll decodes this, issues a command instruction, activates the DMA control circuit 19, and performs the RO
By controlling the address and length of the loading program to be applied in M12, address A and length L of main memory 2 are loaded to address B of RAM I3. Please note that the line adapter (
LAO) 41 to (LA7) 43 each use a configuration in which driver/receivers DR/RC are provided on both sides of a line control circuit.

As explained above, according to the present invention, a write control register is provided so that an arbitrary address and length can be specified for an initial program to a channel device from the CPU side, and loading can be performed at a variable position. By performing this processing, whereas the address and length of a conventional ROM control program are fixed, variable loading becomes possible, so that the initial program can be loaded with great flexibility.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a conventional example, FIG. 2 is an explanatory diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of main parts of the embodiment of FIG. Central processing unit CPUl2 is a main memory, 3 is a channel device CMCl4l-43 is a line adapter, 11 is a microprocessor MPUll2 is a fixed memory ROMll3 is a non-volatile memory RAMll4 is a receiver, 15 is a write control register, 16 is a driver, 1
7 is a read control register, 18 is an interrupt control circuit, 19
indicates a DMA control circuit, and 20 indicates a driver/receiver.

Claims (1)

[Claims] 1 In a system in which a program stored in the main memory of a central processing unit CPU is loaded into a channel memory of a channel device connected to the CPU by a common bus, the program to be loaded in the main memory is stored. means for instructing a channel device from a CPU the starting address of an area, the starting address of an area to be loaded in the channel memory, and a length indicating the size of the area; a circuit for loading the program into a storage area of a channel memory corresponding to the program;
An initial program loading method characterized in that a channel device loads the program into a storage area instructed by a CPU.