JPS6057673A - MOS type semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to an MO8 type semiconductor device, and particularly to an MO8 type semiconductor device including a nonvolatile semiconductor memory device.

[Prior art]

Conventionally, in a non-volatile semiconductor memory device configured using MOS transistors/MOS transistors, high voltage is applied to the diffusion layer or gate when storing and erasing information. When a high voltage is applied to one of the adjacent diffusion layers and the other diffusion layer is kept at a lower potential, if a high voltage is applied to the wiring layer that intersects with both diffusion layers through an insulating film, , parasitic MIS) transistors become conductive, and a leakage current flows, resulting in a decrease in the potential of the diffusion layer.

As an example, Fowler-Nordheim A (Fowler-Nordheim A) has a floating gate structure and has a thin insulating layer in a part of the gate insulating film.
An array of memory transistors that electrically performs writing and erasing using type tunneling current will be described.

FIG. 1 is a wiring diagram of a memory transistor and a select transistor for one bit of a conventional nonvolatile semiconductor memory device.

In FIG. 1, 1 to 3 are select transistors, 4 is a memory transistor, Xi is connected to a word line, and Yi is connected to a bit line. When electrons are injected into the floating gate of the memory transistor 4 (referred to as erasing here), the gate terminal of the transistor 4 is injected. A high voltage is applied to the drain terminal VI) (I
: Ground.

Conversely, when extracting electrons from the floating gate (herein referred to as writing), a high voltage is applied to the drain terminal VD and the gate terminal ■. By grounding G, a high electric field is fully applied to the thin gate insulating film, and electrons move in each direction.

2(a) and 2(b) are a plan view and a sectional view taken along the line AA' of the circuit shown in FIG. 1 realized on a semiconductor substrate. However, the transistor l in FIG. 1 is omitted.

In FIGS. 2(a) and (b), 5 is a P-type silicon substrate, 6 is a gate insulation layer, 8 is an interlayer insulation film, and 10.1
1 is a Nm diffusion layer, 12 is a floating gate, 13 is
14 is a control gate i, 14 is a gate in the first wiring layer, 15 is a contact hole, and 16 is a metal wiring in the second wiring layer.

In this semiconductor device, when erasing a transistor, the diffusion layer 11 is grounded and a high voltage is applied to the control gate 13, but it is also necessary to apply a high voltage to the diffusion layer 10 and the gate 14 at the same time. Unfortunately, at this time Gate 1
4, the parasitic M with the diffusion layers to and 11 as the drain and source, respectively, and the field insulating film 7 as the gate insulating film.
When the ISI-transistor exceeds its threshold voltage and becomes conductive, a leakage current flows between the diffusion layer 11, which is the drain, and the diffusion layer 11, which is the source. In some cases, it may become impossible to apply a sufficiently high voltage to 13. Similar leakage also occurs in the parasitic MIS transistor caused by the control gate 113.

This phenomenon occurs especially in large-capacity denomination chairs.
When all memory transistors are erased at the same time, the effect cannot be ignored.

Here, in order to increase the threshold voltage of the parasitic MIS transistor and prevent the current from flowing <<L when it becomes conductive, it is necessary to increase the impurity concentration of the channel stopper in the element isolation region, or to prevent the current from flowing. It is possible to increase the thickness of the film, but the effects of conventional extension techniques are minimal, and damage may occur such as a decrease in fcP-N junction breakdown voltage and difficulty in separating fine elements. The problem with this was very rare.

[Purpose of the invention]

The object of the present invention is to eliminate the above-mentioned drawbacks, increase the threshold voltage of parasitic M and IS transistors, and prevent leakage current.
An object of the present invention is to provide an 8-type semiconductor device.

[Structure of the invention]

The MO8 type semiconductor device of the present invention is a nonvolatile semiconductor memory device having two or more wiring layers, and has a first diffusion layer to which a high voltage is applied for writing or erasing information, and a lower potential than the first diffusion layer. A first interconnection layer is arranged such that the first and second diffusion layers are adjacent to each other via an element isolation region and intersect with the first and second diffusion layers via an insulating film. The first region and the second region are separated by two at a position between the second diffusion layers, and the second wiring layer is located above the first wiring layer. The first region and the second region of the separated first wiring layer are electrically coupled to each other.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to drawings.

FIGS. 3(a) and 3(b) are a plan view and a sectional view taken along line B-B/ of an embodiment of the present invention.

The P-type silicon substrate 5 has a first diffusion layer 10 to which a high voltage is applied for writing or erasing information, and a second diffusion layer 11 having a lower potential than the first diffusion layer 10, which is a field insulating film serving as an element isolation region. Gate wiring 1 of the first wiring layer is formed adjacent to each other with 7 layers interposed therebetween, and is arranged so as to intersect with the first and second diffusion layers 10 and 11 with a field insulating film 7 interposed therebetween.
4 is cut and separated at the position of the field insulating film 7 between the first diffusion layer 10 and the second diffusion layer 11, and the separated first
The region 14a and the second region 14b are electrically connected by a metal wiring 16' which is a second wiring layer located above the first wiring layer. Here, 8 is an interlayer insulating film, and 15 is a contact hole provided in the interlayer insulating film.

In the structure of the embodiment of the present invention described above, the combined film thickness of the field insulating film 7 and the interlayer insulating film 8 becomes the insulating film thickness of the parasitic MIS transistor, so it can be easily realized without affecting other elements. It has become possible to dramatically increase the threshold voltage and prevent leakage current.

〔Effect of the invention〕

As explained above, according to the present invention, parasitic MI8)
M that increases the transistor threshold voltage and prevents leakage current.
, 08 type semiconductor device can be easily obtained.

[Brief explanation of drawings]

Figure 1 is a wiring diagram of the memory transistor and select transistor for 1 bit of a conventional non-volatile semiconductor device, and Figure 2
Figures (a) and (b) are a plan view and a cross-sectional view of the circuit shown in Figure 1 realized on a semiconductor substrate, and Figure 3 (a),
(b) is a plan view and a sectional view of one embodiment of the present invention. 1 to 3...Select transistor, 4...
... Memory transistor, 5 ... P-type silicon substrate, 6 ... Gate insulating film, 7 ... Field insulating film, 8 ... Interlayer insulating film, 10...
. . . 1st diffusion layer, 11 . . . 2nd diffusion layer 1. l 2...Floating gate, 13
...Control gate, 14...Gate (first
wiring layer), i4a, l4b..., -
- Gate (first region and second region of first wiring layer),
15... Contact hole, 16... Metal wiring (second wiring layer), 16'... Metal wiring (
14a and 14b). Plan 2 Figure 3

Claims (1)

[Claims] In a non-volatile semiconductor memory device having two or more wiring layers, a first diffusion layer to which a high voltage is applied for writing or erasing information and a second diffusion layer having a lower potential are isolated from each other. A first wiring layer that is adjacent to each other with a region in between and intersects the first and second diffusion layers with an insulating film interposed therebetween is a first wiring layer that is arranged to intersect the first and second diffusion layers with an insulating film interposed therebetween. The first wiring layer is cut and separated into two regions, a first region and a second region, at a position between the second diffusion layers, and the second wiring layer is located above the first wiring layer.・M characterized in that the first region and the second region of the separated first wiring layer are electrically coupled.
O8 type semiconductor device.