JPS6296671A - Sputtering electrode - Google Patents
Sputtering electrodeInfo
- Publication number
- JPS6296671A JPS6296671A JP23520285A JP23520285A JPS6296671A JP S6296671 A JPS6296671 A JP S6296671A JP 23520285 A JP23520285 A JP 23520285A JP 23520285 A JP23520285 A JP 23520285A JP S6296671 A JPS6296671 A JP S6296671A
- Authority
- JP
- Japan
- Prior art keywords
- target
- film
- wafer
- facing
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
- C23C14/3407—Cathode assembly for sputtering apparatus, e.g. Target
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- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Physical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はスパッタリング番こより物体の表面に被覆物を
形成する方法に係り、特にIC基板であるウェハ面の様
な凹凸のある面に薄膜を形成する際1.均一な厚さの膜
を形成するのに好適なスパッタ電極に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for forming a coating on the surface of an object by sputtering, and particularly for forming a thin film on an uneven surface such as a wafer surface of an IC substrate. When doing 1. The present invention relates to a sputter electrode suitable for forming a film of uniform thickness.
従来の円形平板マグネトロン電極によるスパッタ成膜で
は、セミコンダクターワールド(SEMICONDUC
TORWORLD) 1cp84年9月号P125〜1
31に記載の様に、被膜基板であるウェハの外周部分に
あるパターン段差においてウェハ中心方向と反対の、外
向き段差での膜被覆率が低下することが指摘されている
0段差部における膜被覆率は一般にステップカバレジと
呼ばれ、このステップカバレジが悪いと配線の抵抗が増
え、形成された素子の寿命が短くなったり、極端な場合
には配線が断線し、ウェハ上iこできる回路素子の歩留
りが低下する。In sputtering film formation using conventional circular flat magnetron electrodes, Semiconductor World (SEMICONDUC)
TORWORLD) 1cp September 1984 issue P125-1
As described in 31, it has been pointed out that in pattern steps on the outer periphery of a wafer, which is a coated substrate, the film coverage at the outward step opposite to the wafer center direction decreases. This rate is generally referred to as step coverage, and if this step coverage is poor, the resistance of the wiring will increase and the life of the formed device will be shortened, or in extreme cases, the wiring will break and the circuit elements that can be printed on the wafer will be damaged. Yield decreases.
そこで、ステップカバレジの改善を一計る為、近年、月
刊紙[真空41985年第28巻第5号P181〜18
3に見られる様なターゲット構造及びスパッタ電極が提
案された。本提案によるとウェハの外周部分の外向段差
への膜付着量を増大させる為、ウェハ径よりもかなり大
きなスパッタ蒸着源(ターゲット)を配し、かつこのス
パッタ蒸着源に円錐状のテーパを付けている。Therefore, in order to improve step coverage, in recent years the monthly paper [Shinku 4, 1985, Vol. 28, No. 5, P181-18
A target structure and sputter electrode as shown in No. 3 was proposed. According to this proposal, in order to increase the amount of film deposited on the outward step on the outer periphery of the wafer, a sputter deposition source (target) that is considerably larger than the wafer diameter is arranged, and this sputter deposition source is tapered in a conical shape. There is.
さらにウェハに対向させて平板形のターゲットを配し、
テーバターゲットと平板ターゲットの両方から膜材料を
放出させる様にして均一な厚さの膜を形成させている。Furthermore, a flat target is placed facing the wafer.
A film of uniform thickness is formed by releasing film material from both the Taber target and the flat target.
しかし、平板ターゲットから放出される膜材料がウェハ
外局部の段差における平坦部への成膜寄与を考慮されて
いない為、なお十分な膜被覆率を得るに到っていない。However, since the contribution of the film material ejected from the flat target to the flat part of the step outside the wafer is not taken into account, a sufficient film coverage rate has not yet been achieved.
本発明の目的は、上記した従来のスパッタ電極の欠点を
無−<シ、ウェハ外周部の外向き段差における膜被覆率
の向上を計ったスパッタ電極を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a sputter electrode which eliminates the above-described drawbacks of the conventional sputter electrode and improves the film coverage on the outward step at the outer periphery of the wafer.
現在、ウェハとターゲットを静止対向させてスパッタ成
膜する際、広く用いられているプレーナマグネトロン型
スパッタ電極を第1図に示す。原理としては、アノード
6とカソードであるターゲット2間の電界とターゲット
面上に形成したトンネル状磁界4によって、高密度のド
ーナツ状プラズマ7を発生させる様にしたものである。FIG. 1 shows a planar magnetron sputtering electrode that is currently widely used when sputtering film formation with a wafer and a target stationary facing each other. The principle is that a high-density doughnut-shaped plasma 7 is generated by an electric field between an anode 6 and a target 2, which is a cathode, and a tunnel-shaped magnetic field 4 formed on the target surface.
ターゲット2はこのドーナツ状プラズマ7の直下の円環
状部分8が主としてスパッタリングを受け、膜材料を放
出し、対向するウェハ1へ膜を形成する。The annular portion 8 of the target 2 directly under the donut-shaped plasma 7 is mainly subjected to sputtering, ejecting film material and forming a film on the opposing wafer 1.
いま、ウェハ上の段差被覆特性を第2図を用いて説明す
る。ウェハ外局部の外向き段差9(段差側壁部に立てた
法線がウェハの中心方向と逆を向いている段差)へ膜を
形成するのに寄与するターゲット部分は実線で示す弧A
に(12−1)のみである。Now, the characteristics of covering steps on a wafer will be explained using FIG. 2. The target portion that contributes to forming a film on the outward step 9 of the external local part of the wafer (the step in which the normal to the side wall of the step faces in the opposite direction to the center of the wafer) is represented by an arc A shown by a solid line.
(12-1) only.
これに対し、内向き段差10(段差側壁部に立てた法線
がウェハ中心方向を向いている段差)へ膜を形成するの
に寄与するターゲット部分は、破線で示す弧Aに(12
−2)であり、平坦部11には環状部分1−2が全て寄
与する。段差被覆率を議論において、段差側壁部と平坦
部の膜付着量を考慮する際、単に上述の寄与面積だけで
なく、段差側壁部や平坦部から成膜に寄与するターゲッ
ト部分を見込む立体角にも依存することに注意しなけれ
ばならない。このため、ウェハ径と同程度の大きさのプ
ラズマリングを発生させて成膜すると、原理的にウェハ
外周部の外向き段差の膜被覆率はウェハ中心部の段差に
比べ低下する。On the other hand, the target portion that contributes to forming a film on the inward step 10 (the step whose normal to the side wall of the step is directed toward the wafer center) is located along the arc A (12
-2), and the annular portion 1-2 entirely contributes to the flat portion 11. When discussing the step coverage rate and considering the amount of film deposited on the step sidewalls and flat areas, it is important to consider not only the above-mentioned contributing area, but also the solid angle from which the target area that contributes to film formation is viewed from the step sidewalls and flat areas. It should be noted that it also depends on For this reason, if a plasma ring having the same size as the wafer diameter is generated to form a film, in principle, the film coverage of the outward step at the outer periphery of the wafer is lower than that of the step at the center of the wafer.
したがってウェハ外局部の外向き段差の膜被覆率の向上
を計る為には、
1) ウェハ径よりも大きなプラズマリングを発生させ
、平坦部に寄与するターゲット面積に対する外向き段差
の成膜に寄与するターゲット面積の相対比を大きくする
こと、
2)外向き段差に寄与するターゲット(第2図で実線部
分)を見込む立体角を大きくすること、
が必要である。これを実現する方法は、第3図に示す様
に、ウェハ径よりも十分大きく、かつウェハ中心方向に
傾斜を付けたすりばち状のターゲット2−1を用いて、
成膜を行なえばよ−しかし、このままでは、ウェハ外局
付近の膜厚が厚くなり、(第4図参照)所定の膜厚均一
性が得られない。(実用上膜厚均一性は±5チが要求さ
れている。)
そこで均一な膜厚分布を得るには、第4図に示す様な膜
厚分布を得る成膜と、ウェハ中心部の膜厚が厚い第5図
に示す様な膜厚分布を得る成膜を合成すればよい。第5
図に示す様な膜厚分布を得るには、ウェハ径よりも小さ
なプラズマリングを発生させ、成膜すればよいにの様な
考え方で均一な膜厚分布を得ながら、段差被覆率の向上
を計ったのが月刊紙[真空J1985年第28巻筒5号
P181〜P183に記載されたスパッタ電極である。Therefore, in order to improve the film coverage of the outward steps in the outer part of the wafer, 1) Generate a plasma ring larger than the wafer diameter and contribute to the film formation of the outward steps with respect to the target area that contributes to the flat area. It is necessary to increase the relative ratio of target areas; and 2) to increase the solid angle from which the target (solid line in Figure 2) contributing to the outward step is viewed. As shown in FIG. 3, the method for achieving this is to use a dovetail-shaped target 2-1 that is sufficiently larger than the wafer diameter and inclined toward the wafer center.
If the film is formed, however, the film thickness near the outer part of the wafer becomes thicker (see FIG. 4), and the desired film thickness uniformity cannot be obtained. (In practice, film thickness uniformity of ±5 inches is required.) Therefore, in order to obtain a uniform film thickness distribution, it is necessary to form a film to obtain a film thickness distribution as shown in Figure 4, and to form a film in the center of the wafer. It is sufficient to synthesize a film that has a thick film thickness distribution as shown in FIG. Fifth
In order to obtain the film thickness distribution shown in the figure, it is necessary to generate a plasma ring that is smaller than the wafer diameter and then deposit the film.While obtaining a uniform film thickness distribution, it is possible to improve the step coverage. The measurement was made using the sputtering electrode described in the monthly paper [Shinku J, 1985, Vol. 28, No. 5, P181-P183.
ところが、この方式では、小プラズマリングを発生させ
るターゲット面が平板であるため、小プラズマリング発
生時に、ウェハ外周部における平坦部、内向き段差側壁
部には成膜を行なうが、外向き段差側壁部へは成膜を行
なわない為、相対的に外向き段差の膜被覆率が低下する
。However, in this method, since the target surface on which the small plasma rings are generated is a flat plate, when the small plasma rings are generated, the film is formed on the flat part of the outer periphery of the wafer and on the inward step sidewalls, but on the outward step sidewalls. Since no film is formed on the outer surface, the film coverage of the outward steps is relatively reduced.
そこで本発明では、小プラズマリングを発生させるター
ゲット面にウェハ中心を向く傾斜を付けることにより、
小プラズマリング発生時に、ウェハ外周部における平坦
部、内向き段差側壁部も、外向き段差側壁部と同様成膜
され表い様にし、この結果、従来よりも高い膜被覆率を
得られる様にした。Therefore, in the present invention, the target surface that generates the small plasma ring is sloped toward the wafer center.
When a small plasma ring occurs, the flat part on the wafer's outer periphery and the inward step sidewall are also coated in the same manner as the outward step sidewall, and as a result, a higher film coverage rate than before can be obtained. did.
以下、本発明の一実施例を第6図により説明する。 An embodiment of the present invention will be described below with reference to FIG.
軟鉄材か・らなるセンタヨーク15を中心軸として2つ
のコイル14.15が同心状に巻かれている0内側コイ
ル15と外側コイル14の中間には円環状のヨーク16
(中間ヨークと呼ぶ。)が設けられ、さらに外側コイル
の外周部にも円環状ヨーク17(外周ヨークと呼ぶ。)
が設けられている。各ヨークは円板ヨーク1Bにより一
体化し、磁路を形成している。Two coils 14 and 15 are wound concentrically around a center yoke 15 made of soft iron.A circular yoke 16 is located between the inner coil 15 and the outer coil 14.
(referred to as an intermediate yoke) is provided, and an annular yoke 17 (referred to as an outer peripheral yoke) is also provided on the outer periphery of the outer coil.
is provided. Each yoke is integrated by a disk yoke 1B to form a magnetic path.
核コイ!14.15により中間ヨークと外周ヨーク間で
、ターゲットピースA(2−2)の傾斜面から出て再び
該傾斜面に入る磁界19を形成し、さらに中間ヨークと
センタヨーク間で、ターゲットピースB(2−3)の傾
斜面から出て再び、この傾斜面に入る磁界20を形成し
ている。ターゲットピースA(2−2)、B(2−3)
は水冷されたバッキンググレー)A(5−1)、B(5
−2)に取り付けられ、各ターゲットピースには、それ
ぞれ独立に電源29.30により電圧が印加されている
。Nuclear carp! 14.15, a magnetic field 19 is formed between the intermediate yoke and the outer yoke, exiting from the inclined surface of target piece A (2-2) and entering the inclined surface again, and further between the intermediate yoke and the center yoke. A magnetic field 20 is formed that exits from the inclined surface (2-3) and enters this inclined surface again. Target piece A (2-2), B (2-3)
are water-cooled backing gray) A (5-1), B (5
-2), and a voltage is applied to each target piece independently by a power source 29.30.
この結果、電磁界の作用により、2つのドーナツ状プラ
ズマ20.21 (プラズマリングと呼搗)が形成され
る。各ターゲットピースはセンタヨークを軸とした軸対
称回転体形をしており、被スパツタ面は軸方向を向いた
傾斜面(傾斜角θl。As a result, two donut-shaped plasmas 20, 21 (plasma ring and throat) are formed due to the action of the electromagnetic field. Each target piece has an axially symmetrical rotating body shape with the center yoke as its axis, and the surface to be sputtered is an inclined surface facing in the axial direction (angle of inclination θl).
θ2)を有している。各プラズマリングからターゲット
ピース面に衝突するイオンの量を、各ターゲットヒース
に印加する電力量によって制御することにより、各ター
ゲットから放出される成膜材料の量をコントロールし、
対向するウェハ面上に均一な厚さの膜を形成する(各タ
ーゲットへ電力を供給する電源:29.so)。θ2). By controlling the amount of ions that collide with the target piece surface from each plasma ring by the amount of power applied to each target heath, the amount of film forming material released from each target is controlled.
A film of uniform thickness is formed on opposing wafer surfaces (power source for supplying power to each target: 29.so).
各ターゲット裏面の磁石は、永久磁石でもよいが、ター
ゲットの消耗に伴ない磁束密度が増加し、放電インピー
ダンスが低下すると所定の電力を供給できなくなる。本
実施例の様に電磁石で構成すると、放電インピーダンス
を所定の範囲内に設定できる様に磁場を制御できるので
所定の電力が供給できる。この結果一定の成膜速度を維
持できる。The magnet on the back surface of each target may be a permanent magnet, but as the target wears out, the magnetic flux density increases and the discharge impedance decreases, making it impossible to supply a predetermined power. When configured with electromagnets as in this embodiment, the magnetic field can be controlled so that the discharge impedance can be set within a predetermined range, so that a predetermined amount of power can be supplied. As a result, a constant film formation rate can be maintained.
第7図に本発明によって得られた段差被覆率を示す。第
7図の大小プラズマ寸法はそれぞれφ240とφ120
.ターゲット傾斜角はそれぞれ45°と50°、ウェハ
ターゲット間隔はそれぞれ40朋、75絹の場合を代表
例として示す。第7図のウェハとターゲット配置図に破
線で示した平板ターゲットによるよりも、実線で示す傾
斜ターゲットを用いる方が、段差被覆率の向上が計れて
いる。FIG. 7 shows the step coverage obtained by the present invention. The large and small plasma dimensions in Figure 7 are φ240 and φ120, respectively.
.. As a representative example, the target inclination angles are 45° and 50°, the wafer target spacing is 40 mm, and 75 mm. In the wafer and target layout diagram of FIG. 7, the step coverage ratio can be improved by using the inclined target shown by the solid line rather than by using the flat plate target shown by the broken line.
なお、本実施例では、ヨーク部分13.16.17゜1
8をアノードとし、該アノードに正の電位を印加できる
様にしており (電源51)、この結果、プラズマ中か
らウェハ側へ逃げる電子を7ノードに引きつける様にし
て、ウェハへの電子によるダメージを防止している。In addition, in this embodiment, the yoke portion 13.16.17°1
8 is an anode, and a positive potential can be applied to the anode (power supply 51). As a result, electrons escaping from the plasma toward the wafer are attracted to node 7, thereby preventing damage to the wafer due to the electrons. It is prevented.
第8図に第2の実施例を示す。軸対象回転体形のターゲ
ットが、2つの部材2−2.2−5に分割され、各部材
が、ウェハとターゲットの共通の対称軸方向を向いた傾
斜を有する円錐状であり、各ターゲットにそれぞれ独立
の負の高電圧が印加される構造である点は同様である。FIG. 8 shows a second embodiment. A target in the form of an axially symmetrical rotating body is divided into two members 2-2.2-5, each member having a conical shape with an inclination pointing in the direction of a common axis of symmetry of the wafer and the target, and a The structure is similar in that an independent negative high voltage is applied.
′/fJ1の実施例と異なる点は、ターゲット面上にト
ンネル状m場を形成する為のヨーク及び電磁石構造体に
ある。四つの円板状ヨーク22.23゜24.25と円
筒状ヨーク26.27が一体化し、磁路を形成しており
、各円板状ヨーク間にはコイル14、15がターゲット
の対称軸まわりに巻かれている。この様な電磁石構造体
とすることにより、各ターゲット面上にトンネル状磁界
19.20を形成し、外部から印加される電界とによっ
て、2つのドーナツ状グラズマ21を同時に形成する。The difference from the embodiment of '/fJ1 lies in the yoke and electromagnetic structure for forming a tunnel-like m field on the target surface. Four disc-shaped yokes 22.23° 24.25 and a cylindrical yoke 26.27 are integrated to form a magnetic path, and between each disc-shaped yoke, coils 14 and 15 are arranged around the axis of symmetry of the target. wrapped around. By using such an electromagnetic structure, a tunnel-shaped magnetic field 19, 20 is formed on each target surface, and two donut-shaped glasmas 21 are simultaneously formed by an externally applied electric field.
この様にして漿1の実施例と同様の効果が得らnる。In this way, the same effect as in Example 1 with Serum 1 can be obtained.
第9図fこ:1g5の実施例を示す。基本的には第2の
実施例の応用で、軸対称ターゲットをはさんで同時に2
枚のウェハを処理できる様にしたものである。効果とし
て第1の実施例と同様、段差被覆率の向上が計れる一方
、本実施例の特有の効果として同時に2枚のウェハを処
理できる為、従来の2倍の処理能力がある。また、ター
ゲット2−2.2−3とターゲット2−2’。Figure 9 shows an example of 1g5. Basically, it is an application of the second embodiment, with two simultaneous targets across an axisymmetric target.
It is designed to be able to process multiple wafers. As an effect, similar to the first embodiment, the step coverage ratio can be improved, while a unique effect of this embodiment is that two wafers can be processed at the same time, so the processing capacity is twice that of the conventional method. Also, target 2-2.2-3 and target 2-2'.
2−5′を異・なる物質にすれば、ウェハ1とウェハ1
′はそれぞれ物質の異なる膜を形成することが可能であ
る。各ターゲットへの投入電力を変えることにより膜厚
の異なる膜形成も可能である0
〔発明の効果〕
本発明に依れば、ウェハ面上の段差部における段差側壁
部と平坦部への成膜材料の付着!8均一化できるので、
段差部での膜被覆率の向上が計れる。従来のテーバ付タ
ーゲットと平坦ターゲットのH1@−せによるステップ
カバレジ(30チ)に対して、同一寸法のターゲットで
は、平坦ターゲット部分にもテーバを付ける本発明によ
ると39%へ改善できる見込みでンらる。If 2-5' is made of different materials, wafer 1 and wafer 1
' can form films of different materials. It is also possible to form films with different thicknesses by changing the power input to each target.0 [Effects of the Invention] According to the present invention, it is possible to form films on the step sidewalls and flat parts of the step portion on the wafer surface. Adhesion of materials! 8 can be made uniform, so
It is possible to improve the film coverage at the stepped portion. Compared to the conventional step coverage (30 inches) due to the H1@-separation of a tapered target and a flat target, it is expected that this can be improved to 39% with the present invention, in which the flat target part is also tapered, for targets of the same size. Ruru.
この結果、ウェハ上に形成されるLSIの各チップ性能
が安定し、歩留り向上が計れる。As a result, the performance of each LSI chip formed on the wafer is stabilized, and the yield can be improved.
第1図はマグネトロンスパッタ電極の概略図、M2図は
外向き段差のカバレジ低下の原因を示す図、第3図はす
りばち状ターゲットとウェハとの関係を示す図、第4図
は第3図に示すターゲットによるウェハ上の膜厚分布の
図、I!5図は、小さなプラズマリングによって成膜し
た時のウェハ上の膜厚分布の図、第6図は本発明による
スパッタ電極の縦断面図、第7図は本発明による電極で
のステップカバレジを示す図、第8図及び第9図はそれ
ぞれ本発明の第2.第3の実施例としてのスパッタ電極
の縦断面図であるn
1・・・ウェハ 2.2−1.2−2.2−5.2=2
’。
2−3′ ・・・ターゲット 5.5−1.3−2・・
・バッキングプレート 4 、19.20.19’、
20’・・・磁力線7 、21 、21’・・・プラズ
マ 8・・・ターゲットの被スパツタ部分
\〜Figure 1 is a schematic diagram of the magnetron sputtering electrode, Figure M2 is a diagram showing the cause of coverage deterioration due to outward steps, Figure 3 is a diagram showing the relationship between the cone-shaped target and the wafer, and Figure 4 is the same as Figure 3. Diagram of the film thickness distribution on the wafer according to the target shown, I! Figure 5 shows the film thickness distribution on the wafer when deposited using a small plasma ring, Figure 6 is a longitudinal cross-sectional view of the sputter electrode according to the present invention, and Figure 7 shows step coverage with the electrode according to the present invention. 8 and 9 respectively show the second embodiment of the present invention. It is a vertical cross-sectional view of a sputter electrode as a third example.n1...Wafer 2.2-1.2-2.2-5.2=2
'. 2-3'...Target 5.5-1.3-2...
・Backing plate 4, 19.20.19',
20'... Lines of magnetic force 7, 21, 21'... Plasma 8... Part of target to be spattered\~
Claims (1)
形成を行なう成膜方式で、成膜材料であるターゲットの
形状が軸対称回転体形であるスパッタ電極において、該
ターゲットの被膜基板と対面するターゲット面は、ター
ゲットの対称軸方向を向いた複数の傾斜面を有し、かつ
該傾斜面を含む部材ごとに分割され、各部材の1部もし
くは全てが各ターゲット部材から電気的に絶縁され、該
絶縁された部材ごとに独立に電力が投入できる構成とな
つており、さらに各傾斜面上には、各傾斜面から出て、
再びその同一の傾斜面へ入る閉じた磁界を形成したこと
を特長とするスパッタ電極。 2、特許請求範囲第1項記載のスパッタ電極において、
該軸対称回転体形ターゲットをはさんで複数の被膜基板
を設置し、該複数の基板を同時に、またはターゲット面
に対面した基板ごとに別々に膜形成が行なえるスパッタ
電極。 3、特許請求範囲第2項記載のスパッタ電極において、
基板に対向したターゲット材料が異なる物質からなり、
ターゲットに対向する基板ごとに異なる物質の膜形成が
行なえるスパッタ電極。[Scope of Claims] 1. In a film forming method in which a film is formed by placing a coating substrate and a sputter electrode facing each other, and in which a sputter electrode whose target, which is a film forming material, has an axially symmetrical rotating body shape, the coating of the target is The target surface facing the substrate has a plurality of inclined surfaces facing in the direction of the symmetry axis of the target, and is divided into members including the inclined surfaces, so that a part or all of each member is electrically disconnected from each target member. It is configured such that power can be input independently to each insulated member, and furthermore, on each slope, there is a power source that comes out from each slope,
A sputter electrode characterized by forming a closed magnetic field that enters the same slope again. 2. In the sputter electrode according to claim 1,
A sputtering electrode in which a plurality of coated substrates are placed across the axis-symmetric rotating body target, and a film can be formed on the plurality of substrates simultaneously or separately for each substrate facing the target surface. 3. In the sputter electrode according to claim 2,
The target material facing the substrate is made of different substances,
A sputtering electrode that can form a film of a different material on each substrate facing the target.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23520285A JPS6296671A (en) | 1985-10-23 | 1985-10-23 | Sputtering electrode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23520285A JPS6296671A (en) | 1985-10-23 | 1985-10-23 | Sputtering electrode |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6296671A true JPS6296671A (en) | 1987-05-06 |
Family
ID=16982588
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23520285A Pending JPS6296671A (en) | 1985-10-23 | 1985-10-23 | Sputtering electrode |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6296671A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63103065A (en) * | 1986-10-20 | 1988-05-07 | Tokyo Electron Ltd | Film formation by sputtering |
JP2006037127A (en) * | 2004-07-23 | 2006-02-09 | Cyg Gijutsu Kenkyusho Kk | Sputter electrode structure |
EP2081212A1 (en) * | 2008-01-16 | 2009-07-22 | Applied Materials, Inc. | Double-Coating Device with one Process Chamber |
US9175383B2 (en) | 2008-01-16 | 2015-11-03 | Applied Materials, Inc. | Double-coating device with one process chamber |
-
1985
- 1985-10-23 JP JP23520285A patent/JPS6296671A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63103065A (en) * | 1986-10-20 | 1988-05-07 | Tokyo Electron Ltd | Film formation by sputtering |
JP2006037127A (en) * | 2004-07-23 | 2006-02-09 | Cyg Gijutsu Kenkyusho Kk | Sputter electrode structure |
EP2081212A1 (en) * | 2008-01-16 | 2009-07-22 | Applied Materials, Inc. | Double-Coating Device with one Process Chamber |
US9175383B2 (en) | 2008-01-16 | 2015-11-03 | Applied Materials, Inc. | Double-coating device with one process chamber |
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