JPS632117B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video display device, and more particularly to a video display device that can smoothly display kanji characters on the video display device.

Video display devices usually display alphabetical characters, numbers, and kana characters (hereinafter referred to as "kana characters, etc.") in a format of 80 characters horizontally and 24 lines vertically. When displaying kanji with this device,
Kanji codes must be written in the refresh memory using a character code area for two characters, such as kana characters, and read out and displayed at the same time by some means. If you try to display a kanji at the 80th character of The drawback was that you always had to be aware of the end of the line.

The present invention eliminates the above-mentioned drawbacks of conventional video display devices, and provides a video display device that is capable of displaying kanji without any restrictions on the number of displayed characters or the display position. The purpose is to

The above object of the present invention is to distinguish between kana characters, etc. and kanji characters in a refresh memory in a display system of a video display device configured to use approximately twice the area for displaying kanji characters as for displaying kana characters, etc. In addition to writing the code, write 1 kanji character in the area where a 1-character code such as kana characters can be entered.
Two consecutive areas are used for character codes, and a circuit is provided to read out each character code at least one display timing in advance, so that when a code representing the kanji is output, the kanji is read out. This is achieved by a video display device that reads and displays character patterns using the Kanji codes written in the two areas as one Kanji code, based on the information of the first address of the code.

Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 is a block diagram showing a display circuit of a display device according to an embodiment of the present invention. The display circuit of this embodiment includes a refresh memory 1, a JIS8 unit alphanumeric kana character pattern generator (hereinafter simply referred to as a "kana character pattern generator") 2, a kanji pattern generator 3, a parallel/serial conversion register 4, It consists of a cathode ray tube circuit 5, a register circuit 7, a switching circuit and a readout circuit 9. The readout circuit 9 controls the refresh memory 1 and the register circuit 7,
The kanji code is read out from the refresh memory 1 at the timing of reading out at least the character code immediately before it, and set in the register circuit 7. The output of the kana character pattern generator is connected to the parallel/serial conversion register 4 through the switching circuit 8, the output of the register circuit 7 is input to the kanji pattern generator 3, and the output is connected to the parallel/serial conversion register 4 through the switching circuit 8. Connected to 4. The output of the register is connected to the cathode ray tube circuit 5.

FIG. 2 is a diagram of a display screen showing the status of displayed characters. Here, the number of characters displayed in one line is based on the size of the above-mentioned kana characters, etc., and the horizontal character is X, and the vertical is Y.
Line. One section 6 in the figure is a display area for kana character patterns based on JIS 8 unit alphanumeric kana character codes (defined in JIS C6220).

Kanji patterns are displayed using areas 10 ₁ and 10 ₂ that are twice as large as those for patterns such as kana characters.

FIG. 3 shows the contents of the refresh memory 1, which has a storage capacity of 10 bits per address for storing character codes and other purposes. The JIS8 unit code contains a code in only one address, and the two bits 2 ⁹ and 2 ⁸ are set to "0" to distinguish it from the Kanji code described later. The kanji code is the first for two consecutive addresses.
The code is divided into a code and a second code, and the ²⁹ bits of both addresses are set to "1" to indicate that it is a kanji code. ²⁸ bits of the address corresponding to the code are set to "1", and ²⁸ bits of the address corresponding to the second code are set to "0".

Figure 4 shows the configuration of this embodiment in detail.
2 Indicates whether the output from refresh memory 1 is a kanji code or not. 2 Indicates whether the output is ^{a 9-} bit signal and a kanji code, the first or second code. ⁸
The bit signals are input to AND circuits A ₁ and A ₂ respectively. Moreover, the output T _N-1A of the readout circuit 9,
T _N-1B is also input to the AND circuits A ₁ and A ₂ respectively, and the outputs of the refresh memory 1 are set in the registers R ₁ and R ₂ in the register circuit 7. The outputs of registers R ₁ and R ₂ are input to the Kanji pattern generator 3. Further, a ^29- bit signal for distinguishing between a JIS8 unit code and a kanji code is input to the kana character pattern generator ₂ through an inverter circuit N2, and serves as its enable signal. Furthermore, the output of the kanji pattern generator 3 and the output of the kana character pattern generator 2 are the output ²⁹ , ²⁸ bit signals of the refresh memory 1 and the screen display timing.
T _x is connected to AND circuits A ₅ and A ₆ of the switching circuit 8 , and their outputs are connected to the parallel-to-serial conversion circuit 4 . Furthermore, the ^29- bit signal simultaneously converts the shift clock pulse of the parallel-to-serial conversion register 4 into the 12 shift clock.
24 shift clock and switching AND circuit _A3 ,
It is also connected to the input of _A4 , shifts the parallel/serial conversion register 4, and sends the output to the cathode ray tube circuit 5.

Next, the operation of this embodiment will be explained.

Character video displays usually input the character code output from the refresh memory 1 to character pattern generators 2 and 3, and set the character pattern output to the parallel/serial register 4 in synchronization with the scanning of the cathode ray tube circuit 5. It is to be displayed. Here, the above-mentioned kana characters are displayed with 12 dots horizontally and 24 dots vertically, and kanji characters are displayed with 24 dots horizontally and 24 dots vertically. Since the correspondence between the address of refresh memory 1 and the display screen is fixed, the address (1, 1) on the cathode ray tube is
To display the letter “A” at address (2,1) and the letter “B” at address (2,1), write the “A” or “B” code into the corresponding refresh address, respectively, as shown in Figure 3. . In this case, the refresh memory normally outputs at horizontal display timing T _x . For example, to display the character “A” (address (1, ₁ ) in Fig.
At this timing, the code in refresh memory 1 is read out and input to the kana character pattern generator 2, and this output pattern is set in the parallel/serial conversion register.At the same time, the 12-bit shift clock is input, so the 12-bit shift clock is input to the cathode ray tube circuit. A character pattern is displayed.

When displaying kanji in this embodiment, as shown in FIG. 3, two consecutive addresses (X, 1),
(1,2), and addresses (2,2), (3,2)
For the first word of each set, write "1" in both ²⁸ bits and ²⁹ bits, and for the last word, write "0" in ²⁸ bits, 2 As mentioned above, we decided to write “1” in the ^9th bit. With the 2 bits added in this way, the refresh
The memory 1 is refreshed sequentially from horizontal display 1 to X at timings T ₁ to T _x corresponding to the display screens. On the other hand, the readout circuit 9 transfers the address of the refresh memory 1 to the previous display screen address (2,1), (3,1) during the timing _T1 (timing corresponding to the address (1,1)). The character code in the previous destination addresses (2, 1) and (3, 1) can be read. This output is set in registers R ₁ and R ₂ in register 7, as shown in FIG. However, these registers R ₁ and R ₂ do not perform the above setting if the output read from the refresh memory 1 is not a Kanji code (that is, the ^29- bit signal is "1"). Also, register R ₁ contains the first code of the kanji code, register
The second code of the kanji code is set in R ₂ ,
These outputs are combined to generate Kanji pattern generator 3.
is input. The output of the kanji pattern generator 3 is
During the refresh timing T _x when the Kanji code is the first code ( ^28- bit signal is “1”),
It is set in the parallel/serial conversion register 4 through the switching circuit 8, and a 24-bit shift clock is input at the same time, so that a 24-bit character pattern is displayed on the cathode ray tube circuit.

In the above embodiment, the switching circuit 8 converts the outputs of the kanji pattern generator 3 and the kana character pattern generator 2 into the outputs ²⁹ and ²⁸ bit signals of the refresh memory 1 and the screen display timing _Tx.
Although the AND circuits A ₅ and A ₆ are used for switching, such selection can also be performed by various other means.

As described above, in the present invention, in a display system of a video display device configured to use approximately twice the area when displaying kanji characters as when displaying kana characters, etc., the refresh memory stores kana characters, etc. and kanji characters. In addition, two consecutive areas shall be used for one-character code of Kanji, and each area for one-character code such as kana characters shall be used as a unit, and each character code shall be A circuit is provided that reads out the display timing in advance, and when the code representing the kanji is output, the kanji code written in the two areas is converted into one kanji code and the character is read using the first address information of the kanji code. Since the pattern is read and displayed, it is possible to completely eliminate restrictions on the number of kanji characters or the display position, and there is no need to be conscious of the end of the display line, which is an excellent effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a diagram of a display screen showing the status of displayed characters, FIG. 3 is a diagram showing the contents of a refresh memory, and FIG. 4 is a circuit diagram showing details of the configuration of the embodiment. 1: Refresh memory, 2: Kana character pattern generator, 3: Kanji pattern generator, 4: Parallel/serial conversion register, 5: CRT circuit, 7: Register circuit, 8: Switching circuit, 9: Readout circuit, A ₁ to _A6 : AND circuit, _R1 , _R2 : Register, _N1 to _N4 : Inverter circuit.

Claims (1)

[Scope of Claims] 1. A refresh memory that stores character codes and kanji codes, a character pattern generator that generates a character pattern corresponding to the character code, and a kanji pattern that generates a kanji pattern that corresponds to the kanji code. In a video display device equipped with a generator, the character code is stored in the refresh memory;
A kanji code in which the size of one character code is one unit and the size of multiple units is configured as one kanji code, and first control information that distinguishes the character code and the kanji code; 1
When the control information of indicates a kanji code, the second control information indicating the order of each kanji code constituting one kanji code
a first one corresponding to the character code or kanji code to be displayed stored in the refresh memory in synchronization with the display timing;
If the second control information is read together with a character code or a kanji code, and the first control information indicates a kanji code, the subsequent kanji codes are set to be the same in response to the second control information indicating the first kanji code. At the display timing, read from the refresh memory and set the first and subsequent kanji codes as 1.
A video display device characterized in that the kanji pattern generator is given as a kanji code to obtain and display pattern information of kanji characters approximately twice as many as the characters.