JPS644059A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPS644059A JPS644059A JP62157655A JP15765587A JPS644059A JP S644059 A JPS644059 A JP S644059A JP 62157655 A JP62157655 A JP 62157655A JP 15765587 A JP15765587 A JP 15765587A JP S644059 A JPS644059 A JP S644059A
- Authority
- JP
- Japan
- Prior art keywords
- type semiconductor
- insulating film
- electrodes
- manufacture
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 4
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 238000002955 isolation Methods 0.000 abstract 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
PURPOSE:To simplify a manufacturing process, by forming first and second MISFET sidewalls at the same time. CONSTITUTION:Ions of n-type impurities are implanted into a P type semiconductor substrate 1 so as to form an (n) well NW. After a field insulating film 2 is formed to perform element isolation, a gate insulation film 3 is formed. Next, gate electrodes G1 to A3 and insulating films 4 are formed in prescribed shapes. Electrodes G1 and G2 are used as masks to form n<-> type semiconductor region 5 in the substrate 1. An electrode G3 is used as a mask to form a p<-> type semiconductor region 6 in the well NW. Next an insulating film 7 is formed. The insulating film 7 is provided with anisotropic etching, so that a sidewall 8 for a MISFETQ1, a MISFETQ2, and a sidewall 8 for the Q3 are formed on side planes of the electrodes G1 to G3 at the same time.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62157655A JPS644059A (en) | 1987-06-26 | 1987-06-26 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62157655A JPS644059A (en) | 1987-06-26 | 1987-06-26 | Manufacture of semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS644059A true JPS644059A (en) | 1989-01-09 |
Family
ID=15654474
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62157655A Pending JPS644059A (en) | 1987-06-26 | 1987-06-26 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS644059A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08250601A (en) * | 1996-03-21 | 1996-09-27 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
US5917211A (en) * | 1988-09-19 | 1999-06-29 | Hitachi, Ltd. | Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same |
-
1987
- 1987-06-26 JP JP62157655A patent/JPS644059A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5917211A (en) * | 1988-09-19 | 1999-06-29 | Hitachi, Ltd. | Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same |
JPH08250601A (en) * | 1996-03-21 | 1996-09-27 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
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