JPS6450139A - Cache memory access system - Google Patents

Cache memory access system

Info

Publication number
JPS6450139A
JPS6450139A JP62206170A JP20617087A JPS6450139A JP S6450139 A JPS6450139 A JP S6450139A JP 62206170 A JP62206170 A JP 62206170A JP 20617087 A JP20617087 A JP 20617087A JP S6450139 A JPS6450139 A JP S6450139A
Authority
JP
Japan
Prior art keywords
store
read
cache memory
address
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62206170A
Other languages
Japanese (ja)
Inventor
Itaru Okano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62206170A priority Critical patent/JPS6450139A/en
Publication of JPS6450139A publication Critical patent/JPS6450139A/en
Pending legal-status Critical Current

Links

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To decrease the number of times of an access by synthesizing a store so as to be written by a cache memory access of one, when the store to the same write unit of a cache memory has been detected in a store buffer. CONSTITUTION:A register 4 holds a read pointer for the time of reading out a store buffer, and when read-out of one entry is completed, a value which has been brought to +1 by a +1 adder 5 is loaded. From a buffer 1, a data of an entry shown by the register 4 is always read out. A read address which has been selected by a selector 6 is compared with the contents of a cache store buffer by comparators 7-10. When one or more comparators detect the coincidence of the address, the read address concerned is inhibited, and after a store in the store buffer has been reflected on a cache memory, a read request is restarted. When an entry which can be allowed to degenerate is detected by comparing the address, its face is reported to a degeneracy control logic 20.
JP62206170A 1987-08-19 1987-08-19 Cache memory access system Pending JPS6450139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62206170A JPS6450139A (en) 1987-08-19 1987-08-19 Cache memory access system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62206170A JPS6450139A (en) 1987-08-19 1987-08-19 Cache memory access system

Publications (1)

Publication Number Publication Date
JPS6450139A true JPS6450139A (en) 1989-02-27

Family

ID=16518967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62206170A Pending JPS6450139A (en) 1987-08-19 1987-08-19 Cache memory access system

Country Status (1)

Country Link
JP (1) JPS6450139A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02207351A (en) * 1989-02-03 1990-08-17 Digital Equip Corp <Dec> Method and apparatus for increasing data storage rate of computer system in which width of data path is predetermined
JP2012043202A (en) * 2010-08-19 2012-03-01 Nec Computertechno Ltd Store merge device, information processing device, store merge method, and program

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02207351A (en) * 1989-02-03 1990-08-17 Digital Equip Corp <Dec> Method and apparatus for increasing data storage rate of computer system in which width of data path is predetermined
JP2012043202A (en) * 2010-08-19 2012-03-01 Nec Computertechno Ltd Store merge device, information processing device, store merge method, and program

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